ETC AT77C101B

Features
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Sensitive Layer Over a 0.8 µm CMOS Array
Image Zone: 0.4 x 14 mm = 0.02" x 0.55"
Image Array: 8 x 280 = 2240 pixels
Pixel Pitch: 50 µm x 50 µm = 500 dpi
Pixel Clock: up to 2 MHz Enabling up to 1780 Frames per Second
Die Size: 1.7 x 17.3 mm
Operating Voltage: 3V to 5.5V
Naturally Protected Against ESD: > 16 kV Air Discharge
Power Consumption: 20 mW at 3.3V, 1 MHz, 25°C
Operating Temperature Range: 0°C to +70°C: C suffix
Resistant to Abrasion: >1 Million Finger Sweeps
Chip-On-Board (COB), Chip-On-Board (COB) with Connector, or 20-lead Ceramic DIP
Available for Development, with Specific Protective Layer
Applications
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PDA (Access Control, Data Protection)
Cellular Phones, SmartPhone (Access e-business)
Notebook, PC-add on (Access Control, e-business)
PIN Code Replacement
Automated Teller Machine, POS
Building Access
Electronic Keys (Cars, Home,...)
Portable Fingerprint Imaging for Law Enforcement
TV Access
Figure 1. FingerChip™ Packages
Chip-on-Board Package
with connector
Chip-on-Board Package
(COB)
Thermal
Fingerprint
Sensor with
0.4 mm x 14 mm
(0.02" x 0.55")
Sensing Area
and
Digital Output
(On-chip ADC)
AT77C101B
FingerChip™
Sweep your finger
to make life easier
Real size
Note:
AT77C101B part number replaces FCD4B14 and refers to same sensor.
Rev. 2150A–BIOM–02/02
1
Table 1. Pin Description for Chip-On-Board Package: AT77C101B-CB01C
Pin Number
Name
Type
1
GND
GND
2
AVE
Analog output
3
AVO
Analog output
4
TPP
Power
5
TPE
Digital input
6
VCC
Power
7
GND
GND
8
RST
Digital input
9
PCLK
Digital input
10
OE
Digital input
11
ACKN
Digital output
12
De0
Digital output
13
Do0
Digital output
14
De1
Digital output
15
Do1
Digital output
16
De2
Digital output
17
Do2
Digital output
18
De3
Digital output
19
Do3
Digital output
20
FPL
GND
21
GND
GND
Die Attach is connected to pins 1, 7 and 21, and must be grounded. FPL pin must be
grounded.
2
GND
AVE
AVO
TPP
TPE
VCC
GND
RST
PCLK
OE
ACKN
De0
Do0
De1
Do1
De2
Do2
De3
Do3
FPL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
21
AT77C101B
2150A–BIOM–02/02
AT77C101B
Table 2. Pin Description for COB with Connector Package: AT77C101B-CB02C(1)
Note:
Pin Number
Name
Type
1
FPL
GND
2
Not connected
3
Not connected
4
DE3
Digital output
5
DO3
Digital output
6
DE2
Digital output
7
DO2
Digital output
8
DE1
Digital output
9
DO1
Digital output
10
DE0
Digital output
11
DO0
Digital output
12
AVE
Analog output
13
AVO
Analog output
14
TPP
Power
15
TPE
Digital input
16
VCC
Power
17
GND
GND
18
RST
Digital input
19
PCLK
Digital input
20
OE
Digital input
21
ACKN
Digital output
1. “Ref Connector: FH18-21S-0.3SHW (HiROSE)” on page 4
3
2150A–BIOM–02/02
Figure 2. COB with Flex(2)
Flex with metallizations up
Flex with metallizations down
Figure 3. Flex Output Side
Flex Output
(FingerChip Connector side)
Metallizations up
1
3
2
Notes:
4
1. Ref Connector: FH18-21S-0.3SHW (HiROSE)
2. Flex is not provided by ATMEL
AT77C101B
2150A–BIOM–02/02
AT77C101B
Table 3. Pin Description For DIP Ceramic Package: FCD4B14CC
Pin Number
Name
Type
1
GND
GND
2
AVE
Analog output
3
TPP
Power
4
VCC
Power
5
RST
Digital input
6
OE
Digital input
7
De0
Digital output
8
De1
Digital output
9
De2
Digital output
10
De3
Digital output
11
FPL
GND
12
Do3
Digital output
13
Do2
Digital output
14
Do1
Digital output
15
Do0
Digital output
16
GND
GND
17
ACKN
Digital output
18
PCLK
Digital input
19
TPE
Digital input
20
AVO
Analog output
GND
AVE
TPP
VCC
RST
OE
De0
De1
De2
De3
1
22
33
4
55
66
77
8
99
10
20
19
18
17
16
15
14
13
12
11
AVO
TPE
PCLK
ACKN
GND
Do0
Do1
Do2
Do3
FPL
Die Attach is connected to pins 1 and 16, and must be grounded. FPL pin must be
grounded.
5
2150A–BIOM–02/02
Description
AT77C101B is part of the Atmel FingerChip monolithic fingerprint sensor family for
which, no optics, no prism and no light source are required.
AT77C101B is a single chip, high performance, low cost sensor based on temperature
physical effects for fingerprint sensing.
AT77C101B has a linear shape, which captures a fingerprint image by sweeping the finger across the sensing area. After capturing several images, Atmel proprietary software
can reconstruct a full 8-bit fingerprint image, if needed.
AT77C101B has a small surface combined with CMOS technology, and a Chip-OnBoard or ceramic dual-in-line package assembly. These facts contribute to a low-cost
device.
AT77C101B delivers a programmable number of images per second, while an integrated Analog to Digital Converter delivers a digital signal adapted to interfaces such as
an EPP parallel port, USB microcontroller or directly to microprocessors. Thus, no frame
grabber or glue interface is necessary to send the frames. These facts make
AT77C101B an easy device to include in any system for identification or verification
applications.
Table 1. Absolute Maximum Ratings(1)
Parameter
Symbol
Comments
Value
Unit
Positive supply voltage
VCC
GND to 6.5
V
Temperature stabilization power
TPP
GND to 6.5
V
Front plane
FPL
GND to VCC
V
Digital input voltage
RST PCLK
GND to VCC
V
Storage temperature
Tstg
-50 to +85
°C
Do not solder
Forbidden
°C
DIP: socket mandatory
1. Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
Lead temperature (soldering, 10 seconds)
Note:
Tleads
Table 2. Recommended Conditions Of Use
Parameter
Symbol
Positive supply voltage
VCC
Front plane
FPL
Comments
Min
Typ
Max
Unit
3V
5V
5.5V
V
Must be grounded
GND
V
Digital input voltage
CMOS levels
V
Digital output voltage
CMOS levels
V
Digital load
CL
Analog load
CA
RA
Not connected
Operating temperature range
Tamb
Civil: “C” grade
Maximum current on TPP
ITPP
6
50
pF
pF
kΩ
0 to +70
0
°C
100
mA
AT77C101B
2150A–BIOM–02/02
AT77C101B
Table 3. Resistance
Parameter
Min Value
Standard Method
On pins. HBM (Human Body Model) CMOS I/O
2 kV
MIL-STD-883- method 3015.7
On die surface (Zapgun)
Air discharge
±16 kV
NF EN 6100-4-2
200 000
MIL E 12397B
4 hours
Internal method
ESD
MECHANICAL ABRASION
Number of cycles without lubricant multiply by a factor of 20 for
correlation with a real finger
CHEMICAL RESISTANCE
Cleaning agent, acid, grease, alcohol, diluted acetone
Table 4. Specifications
Explanation Of Test Levels
I
100% production tested at +25°C
II
100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample)
III
Sample tested only
IV
Parameter is guaranteed by design and/or characterization testing
V
Parameter is a typical value only
VI
100% production tested at temperature extremes
D
100% probe tested on wafer at Tamb = +25°C
Parameter
Test Level
Resolution
IV
50
µm
Size
IV
8x280
pixel
Yield: number of bad pixels
I
Equivalent resistance on TPP pin
I
Min
23
Typ
30
Max
Unit
15
bad pixels
47
Ω
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2150A–BIOM–02/02
Table 5. 5V Power Supply = +5V; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50%;
Cload 120 pF on digital outputs, analog outputs disconnected unless otherwise specified.
Parameter
Symbol
Test level
Min
Typ
Max
Unit
4.5
5
5.5
V
ICC
I
IV
7
5
10
6
mA
mA
PCC
I
IV
35
25
50
30
mW
mW
ICCNAP
I
10
µA
VAVx
I
2.9
V
Power Requirements
Positive supply voltage
VCC
Digital positive supply current on VCC pin
Cload = 0
Power dissipation on VCC
Cload = 0
Current on VCC in NAP mode
Analog Output
Voltage range
0
Digital Inputs
Logic compatibility
CMOS
Logic “0” voltage
VIL
I
0
1.2
V
Logic “1” voltage
VIH
I
3.6
VCC
V
Logic “0” current
IIL
I
-10
0
µA
Logic “1”current
IIH
I
0
10
µA
1.5
V
Digital Outputs
Logic compatibility
Logic “0” voltage
VOL
I
(1)
VOH
I
Logic “1” voltage
Note:
1. With IOL = 1 mA and IOH = -1 mA
8
CMOS
(1)
3.5
V
AT77C101B
2150A–BIOM–02/02
AT77C101B
.
Table 6. 3.3V Power supply = +3.3V; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50%;
Cload 120 pF on digital outputs, analog outputs disconnected unless otherwise specified
Parameter
Symbol
Test Level
Min
Typ
Max
Unit
3.0
3.3
3.6
V
Power Requirements
Positive supply voltage
VCC
Digital positive supply current on VCC pin
Cload= 0
ICC
I
IV
6
5
10
6
mA
mA
Power dissipation on VCC
Cload = 0
PCC
I
IV
20
17
33
20
mW
mW
ICCNAP
I
10
µA
VAVx
I
2.9
V
Current on VCC in NAP mode
Analog Output
Voltage range
0
Digital Inputs
Logic compatibility
CMOS
Logic “0” voltage
VIL
I
0
0.8
V
Logic “1” voltage
VIH
I
2.3
VCC
V
Logic “0” current
IIL
I
-10
0
µA
Logic “1”current
IIH
I
0
10
µA
0.6
V
Digital Outputs
Logic compatibility
Logic “0” voltage
CMOS
(1)
VOL
I
(1)
VOH
I
Logic “1” voltage
Note:
1. With IOL = 1 mA and IOH = -1 mA
2.4
V
9
2150A–BIOM–02/02
.
Table 7. Switching Performances. Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50%
Cload 120 pF on digital and analog outputs unless otherwise specified
Parameter
Symbol
Test Level
Min
Typ
Max
Unit
Clock frequency
fPCLK
I
0.5
1
2
MHz
Clock pulse width (high)
tHCLK
I
250
ns
Clock pulse width (low)
tLCLK
I
250
ns
Clock setup time (high)/reset falling edge
tSetup
I
No data change
tNOOE
IV
100
ns
Reset pulse width high
tHRST
IV
50
ns
Parameter
Symbol
Test Level
Min
Output delay from PCLK to ACKN rising edge
tPLHACKN
Output delay from PCLK to ACKN falling edge
0
ns
Table 8. 5.0V All Power Supplies = +5V
Max
Unit
I
90
ns
tPHLACKN
I
85
ns
tPDATA
I
75
ns
tPAVIDEO
I
260
ns
Output delay from OE to data high-Z
tDATAZ
IV
25
ns
Output delay from OE to data output
tZDATA
IV
29
ns
Parameter
Symbol
Test Level
Output delay from PCLK to ACKN rising edge
tPLHACKN
Output delay from PCLK to ACKN falling edge
Output delay from PCLK to Data output Dxi
Output delay from PCLK to Analog output Avx
Typ
Table 9. 3.3V All Power Supplies = +3.3V
Max
Unit
I
110
ns
tPHLACKN
I
100
ns
tPDATA
I
90
ns
tPAVIDEO
I
250
ns
Output delay from OE to data high-Z
tDATAZ
IV
34
ns
Output delay from OE to data output
tZDATA
IV
47
ns
Output delay from PCLK to Data output Dxi
Output delay from PCLK to Analog output AVx
10
Min
Typ
AT77C101B
2150A–BIOM–02/02
AT77C101B
Figure 4. Reset
tHRST
Reset RST
Clock PCLK
tSETUP
Figure 5. Read One Byte/Two Pixels
fPCLK
tHCLK
tLCLK
Clock
PCLK
Acknowledge
ACKN
tPLHACKN
Data output
Do0-3, De0-3
Video analog output
AVO, AVE
tPHLACKN
Data #N-1
Data #N
Data #N+1
Data #N
Data #N+1
t PDATA
Data #N+2
tPAVIDEO
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2150A–BIOM–02/02
Figure 6. Output Enable
Output Enable
OE
Data output
Do0-3, De0 -3
Hi-Z
tZDATA
tDATAZ
Data output
Hi-Z
Figure 7. No Data Change
tNOOE
PCLK
OE
Note:
12
OE must not change during TNOOE after the PCLK falls. This is to ensure that the output drivers of the data are not driving current, to reduce the noise level on the power supply.
AT77C101B
2150A–BIOM–02/02
AT77C101B
Figure 8. AT77C101B Block Diagram
clock
PCLK
ACKN
reset
RST
line sel
column selection
even
4-bit
ADC
1 dummy column
1
8 lines of 280 columns of pixels
Functional Description
chip
temperature
sensor
TPE
TPP
8
latches
8
4-bit
ADC
odd
chip temperature
stabilization
De0-3
amp
2240
8
4
Do0-3
4
output
enable
analog
output
AVE AVO
OE
The circuit is divided into two main sections: sensor and data conversion. One particular
column among 280+1 is selected in the sensor array (1), then each pixel of the selected
column sends its electrical information to amplifiers (2) (one per line), then two lines at a
time are selected (odd and even) so that two particular pixels send their information to
the input of two 4-bit Analog-to-Digital Converters (3), so 2 pixels can be read for each
clock pulse (4).
Figure 9. Functional Description
1
2
column selection
line sel
8 lines of 280 columns of pixels
3
even
4-bit
ADC
4
4
8
latches
amp
8
1 dummy column
odd
4-bit
ADC
De0-3
Do0-3
4
chip
temperature
sensor
Sensor
Each pixel is a sensor in itself. The sensor detects a temperature differential between
the beginning of acquisition and the reading of information: this is the integration time.
The integration time begins with a reset of the pixel to a predefined initial state. Note that
the integration time reset has nothing to do with the reset of the digital section.
Then, at a rate depending on the sensitivity of the pyroelectric layer, on the temperature
variation between the reset and the end of the integration time, and on the duration of
the integration time, electrical charges are generated at the pixel level.
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2150A–BIOM–02/02
Analog-to-Digital
Converter/
Reconstructing an 8-bit
Fingerprint Image
An Analog-to-Digital Converter (ADC) is used to convert the analog signal coming from
the pixel into digital data that can be used by a processor.
Start Sequence
A reset is not necessary between each frame acquisition.
As the data rate for parallel port and USB is in the range of 1 MB per second, and at
least a rate of 500 frames per second is needed to reconstruct the image with a fair
sweeping speed for the finger, two 4-bit ADCs have been used to output 2 pixels at a
time on 1 byte.
Start sequence must consist of:
1. Set the RST pin to high
2. Set the RST pin to low
3. Send 4 clock pulses (due to pipe-line)
4. Send clock pulses to skip the first frame
Note that the first frame never contains relevant information because the integration
time is not correct.
Figure 10. Start Sequence
4+1124 clock pulses to skip the first frame
Reset RST
Clock PCLK
1
Reading the Frames
2
3
4
1
1124
1
A frame consists of 280 true columns + 1 dummy column of 8 pixels. As two pixels are
output at a time, a system must send 281x4 = 1124 clock pulses to read one frame.
Reset must be low when reading the frames.
Read One Byte/Output
Enable
Clock is taken into account on the falling edge and data are output on the rising edge.
For each clock pulse, after the start sequence, a new byte is output on the Do0-3, De03 pins. This byte contains 2 pixels: 4-bit on Do0-3 (odd pixels), 4-bit on De0-3 (even
pixels).
To output the data, the output enable (OE) pin must be low. When OE is high, the Do03 and De0-3 pins are in high-impedance state. This facilitates an easy connection to a
microprocessor bus without additional circuitry since data output can be enabled using a
chip select signal. Note that the AT77C101B is always sending data: there is no data
exchange to perform using read/write mode.
Power Supply Noise
14
IMPORTANT: When a falling edge is applied on OE (i.e when the Output Enable
becomes active), then some current is drained from the power supply to drive the 8 outputs, producing some noise. It is important to avoid such noise just after the falling edge
of the clock PCLK, when the pixels information is evaluated: the timing diagram figure 5
and time TNOOE defines the interval time where the power supply must be as quiet as
possible.
AT77C101B
2150A–BIOM–02/02
AT77C101B
Video Output
An analog signal is also available on pins AVE and AVO. Note that video output is available one clock pulse before the corresponding digital output (one clock pipe-line delay
for the analog to digital conversion).
Pixel Order
After a reset, pixel number one is located on the upper left corner, looking at the chip
with bond pads to the right. For each column of 8 pixels, pixels 1-3-5-7 are output on
odd data Do0-3 pins, pixels 2-4-6-8 are output on even data De0-3 pins. Most significant
bit is bit #3, least significant is bit #0.
Figure 11. Pixel Order
Pixel #2233 (280,1)
Pixel #1 (1,1)
B ond pads
Pixel #8 (1,8)
Synchronization: The
Dummy Column
Pixel #2240 (280,8)
A dummy column has been added to the sensor to act as a specific pattern to detect the
first pixel. So, 280 true columns + 1 dummy column are read for each frame.
The 4 bytes of the dummy column contain a fixed pattern on the two first bytes, and temperature information on the last two bytes.
Dummy Byte
Odd
Even
Dummy Byte 1 DB1:
111X
0000
Dummy Byte 2 DB2:
111X
0000
Dummy Byte 3 DB3:
rrrr
nnnn
Dummy Byte 4 DB4:
tttt
pppp
Note:
x represents 0 or 1
The sequence 111X0000 111X0000 appears on every frame (exactly every 1124 clock
pulses), so it is an easy pattern to recognize for synchronization purposes.
15
2150A–BIOM–02/02
Thermometer
The dummy bytes DB3 and DB4 contain some internal and temperature information.
The even nibble nnnn in DB3 can be used to measure an increase (or decrease) of the
chip temperature, using the difference between two measures of the same physical
device. The following table gives values in Kelvin.
nnnn
Decimal
nnnn
Binary
Temperature differential with code 8
in Kelvin
15
1111
11.2
14
1110
8.4
13
1101
7
12
1100
5.6
11
1011
4.2
10
1010
2.8
9
1001
1.4
8
1000
0
7
0111
-1.4
6
0110
-2.8
5
0101
-4.2
4
0100
-5.6
3
0011
-7
2
0010
-8.4
1
0001
-11.2
0
0000
< -16.8
For code 0 and 15, the absolute value is a minimum (saturation).
When the image contrast becomes low because of a low temperature difference
between the finger and the sensor, it is recommended to use the temperature stabilization circuitry to increase the temperature of two codes (i.e. from 8 to 10), to get at least
an increase >1.4 Kelvin of the sensor. This enables to recover enough contrast to get a
proper fingerprint for recognition purpose.
16
AT77C101B
2150A–BIOM–02/02
AT77C101B
Integration Time and
Clock Jitter
The AT77C101B is not very sensitive to clock jitter (clock variation). The most important
requirement is a regular integration time that ensures the frame reading rate is also as
regular as possible, in order to get consistent fingerprint slices.
If the integration time is not regular, contrast will vary from one frame to another.
Note that it is possible to introduce some waiting time between each set of 1124 clock
pulses, but the overall time of one frame read must be regular. This waiting time is generally the time needed by the processor to perform some calculation over the frame (to
detect the finger, for instance).
Figure 12. Read One Frame
Reset RST is low
1
Column 1
2
3
Column 2
4
5
Column 280
6
1119
Dummy Column 281
1120
1121
1122
1123
1124
7&8
DB1
DB2
DB3
DB4
Clock PCLK
Pixels 1 & 2
3&4
5&6
7&8
1&2
3&4
Figure 13. Regular Integration Time
REGULAR INTEGRATION TIME
Frame n
Frame n+1
Frame n+2
Frame n+3
Clock PCLK
1124 pulses
1124 pulses
1124 pulses
1124 pulses
17
2150A–BIOM–02/02
Power Management
Nap Mode
Several strategies are possible to reduce power consumption when not in use.
The simplest and most efficient is to cut the power supply, using external means.
A nap mode is also implemented in the AT77C101B. To activate this nap mode, the user
must:
1. Set the reset RST pin to high. Doing this, all analog sections of the device are
internally powered down.
2. Set the clock PCLK pin to high (or low), thus stopping the entire digital section.
3. Set the TPE pin to low or disconnect TPP to stop the temperature stabilization
feature.
4. Set Output Enable OE pin to high, so that output are forced in HiZ.
Figure 14. Nap Mode
Nap mode
Reset RST
Nap
Clock PCLK
In Nap Mode, all internal transistors are in shut mode. Only leakage current is drained in
power supply, generally less than the tested value.
Static Current
Consumption
When the clock is stopped (set to 1) and the reset is low (set to 0), the analog sections
of the device drain some current and the digital section does not consume current if the
outputs are connected to a standard CMOS input (= no current is drained in the I/O). In
this case the typical current value is 5 mA. This current does not depend on the voltage
(i.e. it is almost the same from 3V to 5.5V).
Dynamic Current
Consumption
When the clock is running, the digital sections are consuming current, and particularly
the outputs if they are heavily loaded. In any case, it should be less than the testing
machine (120 pF load on each I/O), 50 pF maximum is recommended.
Connected to a USB interface chip (see application note 26 related to the FCDEMO4
kit) at 5V, and running at about 1 MHz, the AT77C101B consumes less than 7 mA on
VCC pin.
Temperature
Stabilization Power
Consumption (TPP pin)
When the TPE pin is set to 1, current is drained via the TPP pin. The current is limited by
the internal equivalent resistance given in table 4 and a possible external resistor.
Most of the time, TPE is set to 0 and no current is drained in TPP. When the image contrast becomes low because of a low temperature differential (less than one Kelvin), then
it is recommended to set TPE to 1 during a short time so that the dissipated power in the
chip elevates the temperature, enabling to recover contrast. The necessary time to
increase the chip temperature of one Kelvin depends on the dissipated power, the thermal capacity of the silicon sensor and the thermal resistance between the sensor and
the surroundings.
As a rule of thumb, dissipating 300 mW in the chip elevates the temperature of 1 Kelvin
in one second. With the 30Ω typical value, 300 mW is 3V applied on TPP.
18
AT77C101B
2150A–BIOM–02/02
AT77C101B
Packaging: Mechanical Data
Figure 15. Product Reference: AT77C101B-CB01C
Top view (all dimensions in mm)
0.3 A
+0.07
17.51 -0.01 at 0.4 height from B ref.
0.89 ± 0.3
5.45 ±0.30
14
0.35
2.32 ± 0.5
5.90 max
2.95 ± 0.50
9 ± 0.5
A
1.66
+0.07
-0.01
at 0.4 height from B ref.
0.83 ± 0.50
5.20 max
0.2 min
26.6 ± 0.5
Dam & Fill
B
1.5 max
0.2 max
0.8
max
0.83 ± 0.11
Figure 16. Product Reference: AT77C101B-CB01C
Bottom view (all dimensions in mm)
1 ± 0.08
1.15 ± 0.15
3.5 ± 0.08
0.5 ±0.08
2.15 ± 0.15
1 ± 0.15
1.5 ± 0.08
6.30 ± 0.1
+0.08
R0.75 -0.12 (x3)
2 ± 0.08
2 ± 0.15
0.75
23.85 ± 0.1
+0.33
-0.25
+0.15
1.5 -0.23 (x3)
19
2150A–BIOM–02/02
Figure 17. Product reference: AT77C101B-CB02C
All dimensions in mm
9.85 ± 0.3
5.2 max
4.1 ± 0.2
+0.04
14.35 -0.01
0.8 MAX
5.9 max
8.9 ± 0.5
FLEX OUTPUT
8.8 ± 0.2
2.9 ± 0.5
26.6 ± 0.3
+0.15
1.5 -0.23 (x 3)
0.83 ± 0.11
1.9 ± 0.4
1.5 MAX
0.2 min
2.39 ± 0.5
1.25 ± 0.5
COUPE AA
4.1 ± 0.5
+0.33
0.75 -0.25
20
FLEX OUTPUT
6.3 ± 0.1
1.78 ± 0.5 (x 2)
+0.07
1.66 -0.01
+0.08
R0.75 -0.12 (x 3)
AT77C101B
2150A–BIOM–02/02
AT77C101B
Figure 18. Product Reference: FCD4B14CC (For Development Only)
1.1 ± 0.1
0.25 max
DIL (all dimensions in mm)
0.08
60°
4.75 ± 0.1
0.81 ± 0.05
0.46 ± 0.05
2.54 ± 0.13
25.4 ± 0.25
0.75 max
0.08
(0.90)
(0.20)
NO.1
7.87 ± 0.25
9.36 ± 0.15 6.34 ± 0.15
0.1 min
NO.20
NO.11
7.5 ± 0.25
(2.45)
(7.62)
6.5 max
3.15 ± 0.32
0.25 ± 0.05
22.86 ± 0.13
NO.10
5.4 max
21
2150A–BIOM–02/02
Ordering Information
Package Device
AT77C
101B-
CBXX
Atmel prefix
FingerChip family
C
—
Quality level:
— : standard
Device type
Package
CB01: Chip On Board (COB)
CB02: COB with connector
Note:
22
Temperature range
Com: 0° to +70°C
AT77C101B part number replaces FCD4B14 and refers to same sensor.
AT77C101B
2150A–BIOM–02/02
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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2150A–BIOM–02/02
0M