ETC BU208A/D

ON Semiconductor
BU208A
Horizontal Deflection
Transistor
5.0 AMPERES
NPN SILICON
POWER TRANSISTOR
700 VOLTS
. . . designed for use in televisions.
•
•
•
•
Collector–Emitter Voltages VCES 1500 Volts
Fast Switching — 400 ns Typical Fall Time
Low Thermal Resistance 1C/W Increased Reliability
Glass Passivated (Patented Photoglass). Triple Diffused Mesa
Technology for Long Term Stability
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MAXIMUM RATINGS
Symbol
BU208A
Unit
Collector–Emitter Voltage
Rating
VCEO(sus)
700
Vdc
Collector–Emitter Voltage
VCES
1500
Vdc
Emitter–Base Voltage
VEB
5.0
Vdc
Collector Current — Continuous
— Peak
IC
ICM
5.0
7.5
Vdc
Base Current — Continuous
— Peak (Negative)
IB
IBM
4.0
3.5
Adc
Total Power Dissipation @ TC = 95C
Derate above 95C
PD
12.5
0.625
Watts
W/C
TJ, Tstg
–65 to +115
C
Symbol
Max
Unit
RθJC
1.6
C/W
TL
275
C
Operating and Storage Junction
Temperature Range
CASE 1–07
TO–204AA
(TO–3)
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Case
Maximum Lead Temperature for Soldering
Purpose, 1/8″ from Case for 5 Seconds
NOTES:
1. Pulsed 5.0 ms, Duty Cycle 10%.
2. See page 3 for Additional Ratings on A Type.
3. Figures in ( ) are Standard Ratings ON Semiconductor Guarantees are Superior.
 Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 9
1
Publication Order Number:
BU208A/D
BU208A
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ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
VCEO(sus)
700
—
—
Vdc
ICES
—
—
1.0
mAdc
5
—
—
7
—
—
hFE
2.25
—
—
Collector–Emitter Saturation Voltage
(IC = 4.5 Adc, IB = 2 Adc)
VCE(sat)
—
—
1
Vdc
Base–Emitter Saturation Voltage
(IC = 4.5 Adc, IB = 2 Adc)
VBE(sat)
—
—
1.5
Vdc
fT
—
4
—
MHz
Cob
—
125
—
pF
Storage Time (see test circuit fig. 1)
(IC = 4.5 Adc, IB1 = 1.8 Adc, LB = 10 µH)
ts
—
8
—
µs
Fall time (see test circuit fig. 1)
(IC = 4.5 Adc, IB1 = 1.8 Adc, LB = 10 µH)
tf
—
0.4
—
µs
OFF CHARACTERISTICS
Collector–Emitter Sustaining Voltage
(IC = 100 mAdc, L = 25 mH)
Collector Cutoff Current1
(VCE = rated VCES, VBE = 0)
ALL TYPES
Emitter Base Voltage1
(IC = 0, IE = 10 mAdc)
(IC = 0, IE = 100 mAdc)
VEBO
Vdc
ON CHARACTERISTICS1
DC Current Gain
(IC = 4.5 Adc, VCE = 5 Vdc)
DYNAMIC CHARACTERISTICS
Current–Gain Bandwidth Product
(IC = 0.1 Adc, VCE = 5 Vdc, ftest = 1 MHz)
Output Capacitance
(VCB = 10 Vdc, IE = 0, ftest = 1 MHz)
SWITCHING CHARACTERISTICS
1Pulse
test: PW = 300 µs; Duty cycle 2%.
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2
BU208A
+40 V
7 mH
+40 V
0.5 µF
1K
250 µF
400 mA
1K
6.5 mH
Ly = 1.3 mH
1 µF
1N5242 (12 V)
100 Ω
10 K
LB
3
1
TBA920
14
10 nF
2
15
820
220
680 nF
10 nF
MPSU04
RB
0.56
1A
1500 V
22 nF
22 nF
T.U.T.
680 µF
10 K
16
100
2K7
3K3
Figure 1. Switching Time Test Circuit
80
POWER DISSIPATION (W)
2K
60
40
20
0
40
80
120
TC, CASE TEMPERATURE (°C)
Figure 2. Power Derating
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3
160
200
0.3 A
FUSE
130 V
POWER
SUPPLY
BU208A
BASE DRIVE
The Key to Performance
By now, the concept of controlling the shape of the turn–off base
current is widely accepted and applied in horizontal deflection
design. The problem stems from the fact that good saturation of the
output device, prior to turn–off, must be assured. This is
accomplished by providing more than enough IB1 to satisfy the
lowest gain output device hFE at the end of scan ICM. Worst–case
component variations and maximum high voltage loading must
also be taken into account.
If the base of the output transistor is driven by a very low
impedance source, the turn–off base current will reverse very
quickly as shown in Figure 3. This results in rapid, but only partial
collector turn–off, because excess carriers become trapped in the
high resistivity collector and the transistor is still conductive. This
is a high dissipation mode, since the collector voltage is rising very
rapidly. The problem is overcome by adding inductance to the base
circuit to slow the base current reversal as shown in Figure 4, thus
allowing access carrier recombination in the collector to occur
while the base current is still flowing.
Choosing the right LB Is usually done empirically since the
equivalent circuit is complex, and since there are several important
variables (ICM, IB1, and hFE at ICM). One method is to plot fall time
as a function of L B, at the desired conditions, for several devices
within the hFE specification. A more informative method is to plot
power dissipation versus I B1 for a range of values of L B.
This shows the parameter that really matters, dissipation,
whether caused by switching or by saturation. For very low LB a
very narrow optimum is obtained. This occurs when IB1 hFE ICM, and therefore would be acceptable only for the “typical”
device with constant ICM. As LB is increased, the curves become
broader and flatter above the IB1. hFE = ICM point as the turn off
“tails” are brought under control. Eventually, if LB is raised too far,
the dissipation all across the curve will rise, due to poor initiation
of switching rather than tailing. Plotting this type of curve family
for devices of different hFE, essentially moves the curves to the
left, or right according to the relation IB1 hFE = constant. It then
becomes obvious that, for a specified ICM, an LB can be chosen
which will give low dissipation over a range of hFE and/or IB1. The
only remaining decision is to pick IB1 high enough to
accommodate the lowest hFE part specified. Neither LB nor IB1 are
absolutely critical. Due to the high gain of ON Semiconductor
devices it is suggested that in general a low value of IB1 be used to
obtain optimum efficiency — eg. for BU208A with ICM = 4.5 A
use IB1 1.5 A, at ICM = 4 A use IB1 1.2 A. These values are
lower than for most competition devices but practical tests have
showed comparable efficiency for ON Semiconductor devices
even at the higher level of IB1.
An LB of 10 µH to 12 µH should give satisfactory operation of
BU208A with ICM of 4 to 4.5 A and IB1 between 1.2 and 2 A.
TEST CIRCUIT WAVEFORMS
IB
IB
IC
IC
(TIME)
(TIME)
Figure 3.
Figure 4.
TEST CIRCUIT OPTIMIZATION
power input can be caused by a variety of problems, but it is the
dissipation in the transistor that is of fundamental importance.
Once the required transistor operating current is determined, fixed
circuit values may be selected.
The test circuit may be used to evaluate devices in the
conventional manner, i.e., to measure fall time, storage time, and
saturation voltage. However, this circuit was designed to evaluate
devices by a simple criterion, power supply input. Excessive
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4
BU208A
hFE, DC CURRENT GAIN
13
VCE(sat) , COLLECTOR-EMITTER SATURATION
VOLTAGE (V)
14
VCE = 5 V
12
11
10
9
8
7
6
5
4
0.01 0.02
0.05
0.1 0.2
0.5
1.0 2.0
IC, COLLECTOR CURRENT (A)
5.0
10
0.5
0.4
0.3
IC/IB = 3
0.2
0.1
0
0.1
Figure 5. DC Current Gain
VCE(sat) , COLLECTOR-EMITTER SATURATION
VOLTAGE (V)
VBE, BASE-EMITTER VOLTAGE (V)
1.6
1.4
1.3
1.2
1.1
IC/IB = 2
0.9
0.8
0.7
0.6
0.1
0.2
0.5
1.0
2.0
10
5.0
2.4
IC = 2 A
IC, COLLECTOR CURRENT (A)
ICM(max.)
0.2
0.1
0.05
TC ≤ 95°C
BONDING WIRE LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
DUTY CYCLE ≤ 1%
0.02
0.01
0.005
0.002
0.001
1
2
5
10 20
50 100 200
IC = 4 A
1.6
IC = 4.5 A
1.2
0.8
0.4
0.2
0.5
1.0
2.0
5.0
IB, BASE CURRENT CONTINUOUS (A)
Figure 8. Collector Saturation Region
1 ms
2 ms
D.C.
BU208,A1
500 1000
10
IC = 3.5 A
1 µs
2
5
10
20
50
100
200
300
IC(max.)
0.5
5.0
IC = 3 A
2.0
Figure 7. Base–Emitter Saturation Voltage
2
1
0.5
1.0
2.0
IC, COLLECTOR CURRENT (A)
2.8
0.1
IC, COLLECTOR CURRENT (A)
15
10
5
0.2
Figure 6. Collector–Emitter Saturation Voltage
1.5
1.0
IC/IB = 2
2000
1Pulse
VCE, COLLECTOR-EMITTER VOLTAGE (V)
Figure 9. Maximum Forward Bias Safe Operating Area
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width ≤ 20 µs. Duty cycle ≤ 0.25. RBE ≤ 100 Ohms.
10
BU208A
PACKAGE DIMENSIONS
CASE 1–07
TO–204AA (TO–3)
ISSUE Z
A
N
C
–T–
E
D
SEATING
PLANE
K
2 PL
0.13 (0.005)
U
T Q
M
M
Y
M
–Y–
L
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. ALL RULES AND NOTES ASSOCIATED WITH
REFERENCED TO-204AA OUTLINE SHALL APPLY.
2
H
G
B
M
T Y
1
–Q–
0.13 (0.005)
M
DIM
A
B
C
D
E
G
H
K
L
N
Q
U
V
INCHES
MIN
MAX
1.550 REF
--1.050
0.250
0.335
0.038
0.043
0.055
0.070
0.430 BSC
0.215 BSC
0.440
0.480
0.665 BSC
--0.830
0.151
0.165
1.187 BSC
0.131
0.188
STYLE 1:
PIN 1. BASE
2. EMITTER
CASE: COLLECTOR
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MILLIMETERS
MIN
MAX
39.37 REF
--26.67
6.35
8.51
0.97
1.09
1.40
1.77
10.92 BSC
5.46 BSC
11.18
12.19
16.89 BSC
--21.08
3.84
4.19
30.15 BSC
3.33
4.77
BU208A
Notes
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7
BU208A
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BU208A/D