Philips Semiconductors Product specification PowerMOS transistor TOPFET DESCRIPTION Monolithic temperature and overload protected power MOSFET in a 3 pin plastic surface mount envelope, intended as a general purpose switch for automotive systems and other applications. APPLICATIONS BUK109-50GS QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID PD Tj RDS(ON) Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance VIS = 10 V MAX. UNIT 50 29 75 150 50 V A W ˚C mΩ General controller for driving lamps motors solenoids heaters FEATURES Vertical power DMOS output stage Low on-state resistance Overload protection against over temperature Overload protection against short circuit load Latched overload protection reset by input 10 V input level Low threshold voltage also allows 5 V control Control of power MOSFET and supply of overload protection circuits derived from input ESD protection on input pin Overvoltage clamping for turn off of inductive loads FUNCTIONAL BLOCK DIAGRAM DRAIN O/V CLAMP POWER INPUT MOSFET RIG LOGIC AND PROTECTION SOURCE Fig.1. Elements of the TOPFET. PINNING - SOT404 PIN PIN CONFIGURATION DESCRIPTION mb 1 input 2 drain 3 source mb SYMBOL drain June 1996 D TOPFET I P 2 1 S 3 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET BUK109-50GS LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER CONDITIONS VDSS VIS = 0 V VIS ID ID IDRM PD Tstg Tj Continuous off-state drain source voltage1 Continuous input voltage Continuous drain current Continuous drain current Repetitive peak on-state drain current Total power dissipation Storage temperature Continuous junction temperature2 Tmb ≤ 25 ˚C; VIS = 10 V Tmb ≤ 100 ˚C; VIS = 10 V Tmb ≤ 25 ˚C; VIS = 10 V Tmb ≤ 25 ˚C normal operation Tsold Lead temperature during soldering MIN. MAX. UNIT - 50 V 0 -55 - 11 29 18 120 75 150 150 V A A A W ˚C ˚C - 250 ˚C OVERLOAD PROTECTION LIMITING VALUES With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload. SYMBOL VISP PARAMETER CONDITIONS MIN. MAX. UNIT 5 - V Protected drain source supply voltage VIS = 10 V - 50 V Short circuit load protection Protected drain source supply voltage4 VIS = 10 V VIS = 5 V Instantaneous overload dissipation Tmb = 25 ˚C - 20 35 1.3 V V kW 3 Protection supply voltage for valid protection Over temperature protection VDDP(T) VDDP(P) PDSM OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL PARAMETER CONDITIONS IDROM EDSM Repetitive peak clamping current Non-repetitive clamping energy EDRM Repetitive clamping energy VIS = 0 V Tmb ≤ 25 ˚C; IDM = 27 A; VDD ≤ 20 V; inductive load Tmb ≤ 95 ˚C; IDM = 8 A; VDD ≤ 20 V; f = 250 Hz MIN. MAX. UNIT - 29 625 A mJ - 40 mJ MIN. MAX. UNIT - 2 kV ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage Human body model; C = 250 pF; R = 1.5 kΩ 1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 3 The input voltage for which the overload protection circuits are functional. 4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum. For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS. June 1996 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET BUK109-50GS THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT - 1.3 1.67 K/W - 50 - K/W MIN. TYP. MAX. UNIT 50 - - V Thermal resistance Rth j-mb Junction to mounting base Rth j-a Junction to ambient minimum footprint FR4 PCB (see fig. 33) STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(CL)DSS Drain-source clamping voltage VIS = 0 V; ID = 10 mA V(CL)DSS Drain-source clamping voltage IDSS IDSS IDSS RDS(ON) VIS = 0 V; IDM = 2 A; tp ≤ 300 µs; δ ≤ 0.01 Zero input voltage drain current VDS = 12 V; VIS = 0 V Zero input voltage drain current VDS = 50 V; VIS = 0 V Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C - - 70 V - 0.5 1 10 10 20 100 µA µA µA Drain-source on-state resistance - 35 45 50 60 mΩ mΩ IDM = 13 A; tp ≤ 300 µs; δ ≤ 0.01 VIS = 10 V VIS = 5 V OVERLOAD PROTECTION CHARACTERISTICS TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input. SYMBOL PARAMETER CONDITIONS 1 Tmb = 25 ˚C; L ≤ 10 µH VDD = 13 V; VIS = 10 V VDD = 13 V; VIS = 10 V EDS(TO) td sc Short circuit load protection Overload threshold energy Response time Tj(TO) Over temperature protection Threshold junction temperature VIS = 10 V; from ID ≥ 1 A2 MIN. TYP. MAX. UNIT - 0.4 0.8 - J ms 150 - - ˚C 1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for PDSM, which is always the case when VDS is less than VDSP maximum. Refer to OVERLOAD PROTECTION LIMITING VALUES. 2 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID ensures this condition. June 1996 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET BUK109-50GS INPUT CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VIS(TO) IIS VISR Input threshold voltage Input supply current Protection reset voltage1 VDS = 5 V; ID = 1 mA VIS = 10 V; normal operation 1.0 2.0 1.5 0.4 2.6 2.0 1.0 3.5 V mA V VISR Protection reset voltage Tj = 150 ˚C 1.0 - - IISL V(BR)IS RIG Input supply current Input clamp voltage Input series resistance VIS = 10 V; protection latched II = 10 mA to gate of power MOSFET 1.0 11 - 2.5 13 4 4.0 - mA V kΩ MIN. TYP. MAX. UNIT 10 16 - S - 80 - A MIN. TYP. MAX. UNIT TRANSFER CHARACTERISTICS Tmb = 25 ˚C SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 10 V; IDM = 13 A tp ≤ 300 µs; δ ≤ 0.01 ID(SC) Drain current2 VDS = 13 V; VIS = 10 V SWITCHING CHARACTERISTICS Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figures and test circuits. SYMBOL PARAMETER CONDITIONS td on Turn-on delay time VDD = 13 V; VIS = 10 V - 1.5 - µs tr Rise time resistive load RL = 2.1 Ω - 6 - µs td off Turn-off delay time VDD = 13 V; VIS = 0 V - 18 - µs tf Fall time resistive load RL = 2.1 Ω - 9 - µs td on Turn-on delay time VDD = 10 V; VIS = 10 V - 2 - µs tr Rise time inductive load IDM = 6 A - 1 - µs td off Turn-off delay time VDD = 10 V; VIS = 0 V - 22 - µs tf Fall time inductive load IDM = 6 A - 1 - µs REVERSE DIODE LIMITING VALUE SYMBOL PARAMETER CONDITIONS IS Continuous forward current Tmb ≤ 25 ˚C; VIS = 0 V MIN. MAX. UNIT - 29 A 1 The input voltage below which the overload protection circuits will be reset. 2 During overload before short circuit load protection operates. June 1996 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET BUK109-50GS REVERSE DIODE CHARACTERISTICS Tmb = 25 ˚C SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VSDS Forward voltage IS = 29 A; VIS = 0 V; tp = 300 µs - 1.0 1.5 V trr Reverse recovery time not applicable1 - - - - MIN. TYP. MAX. UNIT - 2.5 - nH - 7.5 - nH ENVELOPE CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Ld Internal drain inductance Ls Internal source inductance Measured from upper edge of tab to centre of die Measured from source lead soldering point to source bond pad 120 Normalised Power Derating PD% 1000 ID & IDM / A 110 BUK109-50GS Overload protection characteristics not shown 100 90 /ID 80 DS 100 S RD 60 50 10 us 100 us 40 10 1 ms 30 DC 20 10 10 ms 100 ms 0 0 20 40 60 80 100 Tmb / C 120 1 140 100 VDS / V Fig.4. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% 10 1 Fig.2. Normalised limiting power dissipation. PD% = 100⋅PD/PD(25 ˚C) = f(Tmb) 120 tp = N (O 70 V )= 10 BUK109-50GS Zth / (K/W) 110 100 90 D= 1 80 0.5 70 0.2 60 50 0.1 40 0.1 30 0.05 PD 0.02 20 10 0 0 20 40 60 80 Tmb / C 100 120 0.01 1E-07 140 Fig.3. Normalised continuous drain current. ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V tp D= T 0 1E-05 1E-03 t/s tp T t 1E-01 1E+01 Fig.5. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 1 The reverse diode of this type is not intended for applications requiring fast reverse recovery. June 1996 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET BUK109-50GS ID / A BUK109-50GS ID / A BUK109-50GS 11 100 100 VIS / V 10 9 8 7 6 50 50 5 4 3 2 0 0 4 8 12 16 VDS / V 20 24 0 28 0 32 ID / A BUK109-50GS 90 4 6 VIS / V 8 10 12 Fig.9. Typical transfer characteristics, Tj = 25 ˚C. ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs Fig.6. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VIS; tp = 250 µs & tp < td sc 100 2 20 gfs / S BUK109-50GS VIS = 10 V 80 15 8V 70 60 6V 50 10 40 4V 30 5 20 10 0 0 0 2 1 4 3 5 0 20 40 VDS / V Fig.7. Typical on-state characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VIS; tp = 250 µs RDS(ON) / mOhm 5 80 100 Fig.10. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 10 V; tp = 250 µs BUK109-50GS VIS / V = 4 60 ID / A 6 7 8 a Normalised RDS(ON) = f(Tj) 9 10 11 100 1.5 1.0 50 0.5 0 0 0 20 40 60 ID / A 80 100 Fig.8. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VIS; tp = 250 µs June 1996 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.11. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 13 A; VIS = 10 V 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET 100 BUK109-50GS BUK109-50GS td sc / ms 30 10 ID / A BUK109-50GS 20 typ. PDSM 1 10 0.1 0 0.1 1 PDS / kW 10 50 Fig.12. Typical overload protection characteristics. td sc = f(PDS); conditions: VIS ≥ 5 V; Tj = 25 ˚C. 60 VIS / V 70 Fig.15. Typical clamping characteristics, 25 ˚C. ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs VIS(TO) / V PDSM% 120 max. 2 100 typ. 80 60 min. 1 40 20 0 0 -60 -40 -20 0 20 40 60 Tmb / C 80 100 120 140 -60 Fig.13. Normalised limiting overload dissipation. PDSM% =100⋅PDSM/PDSM(25 ˚C) = f(Tmb) 1 Energy & Time -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.16. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V BUK109-50GS 1.0 II / mA BUK109-50GS Time / ms 0.5 0.5 Energy / J Tj(TO) 0 0 -60 -20 20 60 100 Tmb / C 140 180 220 0 4 6 8 10 12 14 VIS / V Fig.14. Typical overload protection characteristics. Conditions: VDD = 13 V; VIS = 10 V; SC load = 30 mΩ June 1996 2 Fig.17. Typical DC input characteristics, Tj = 25 ˚C. IIS = f(VIS); normal operation 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET 5 BUK109-50GS BUK109-50GS RESISTIVE TURN-ON BUK109-50GS IIS / mA VDS / V VIS / V 4 td on 10 3 PROTECTION LATCHED tr ID / A 90% 5 2 RESET NORMAL 10% 1 10% 0 0 0 0 2 4 6 8 VIS / V 10 12 BUK109-50GS RESISTIVE TURN-OFF BUK109-50GS IS / A 20 Fig.21. Typical switching waveforms, resistive load. VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C. Fig.18. Typical DC input characteristics, Tj = 25 ˚C. IISL = f(VIS); overload protection operated ⇒ ID = 0 A 120 10 time / us 14 td off 100 VDS / V 10 90% 80 tf ID / A 60 90% 5 VIS / V 40 10% 20 0 0 0 0 0.2 0.4 0.6 0.8 VSD / V 1 1.2 1.4 10 30 20 1.6 50 40 time / us Fig.22. Typical switching waveforms, resistive load. VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C. Fig.19. Typical reverse diode current, Tj = 25 ˚C. IS = f(VSDS); conditions: VIS = 0 V; tp = 250 µs VDD VDD = VCL RL LD t p : adjust for correct ID TOPFET I P D TOPFET I D.U.T. P RI VIS D D.U.T. RI VIS S ID measure S ID measure 0V 0V 0R1 0R1 Fig.20. Test circuit for resistive load switching times. June 1996 Fig.23. Test circuit for inductive load switching times. 8 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET BUK109-50GS V(CL)DSS BUK109-50GS INDUCTIVE TURN-ON VDS 10 VDD VIS / V + 0 L ID td on ID / A VDS 0 90% 5 TOPFET tr 10% - D VIS 0 VDS / V -ID/100 D.U.T. I P 10% R 01 shunt Schottky 0 RIS 0 10 time / us S 20 Fig.27. Clamping energy test circuit, RIS = 50 Ω. EDSM = 0.5 ⋅ LID2 ⋅ V(CL)DSS /(V(CL)DSS − VDD ) Fig.24. Typical switching waveforms, inductive load. VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C. BUK109-50GS INDUCTIVE TURN-OFF 10 VDD 1 mA VDS / V td off Idss 90% 100 uA tf ID / A 90% 5 10 uA typ. VIS / V 1 uA 10% 0 10 0 30 20 40 100 nA 50 0 time / us Fig.25. Typical switching waveforms, inductive load. VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C. 120 20 40 60 80 Tj / C 100 120 140 Fig.28. Typical off-state leakage current. IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V. Iiso normalised to 25 C EDSM% 110 100 1.5 90 80 70 60 50 1 40 30 20 10 0 0.5 0 20 40 60 80 Tmb / C 100 120 140 -60 Fig.26. Normalised limiting clamping energy. EDSM% = f(Tmb); conditions: ID = 27 A; VIS = 10 V June 1996 -20 20 60 Tj / C 100 140 180 Fig.29. Normalised input current (normal operation). IIS/IIS25 ˚C = f(Tj); VIS = 10 V 9 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET BUK109-50GS Iisl normalised to 25 C 50 1.5 VDDP(P) / V BUK109-50GS 40 max 30 1 20 10 0 0.5 -60 -20 20 60 Tj / C 100 140 0 180 Fig.30. Normalised input current (protection latched). IISL/IISL25 ˚C = f(Tj); VIS = 10 V June 1996 2 4 6 VIS / V 8 10 Fig.31. Maximum drain source supply voltage for SC load protection. VDDP(P) = f(VIS); Tmb ≤ 150 ˚C 10 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET BUK109-50GS MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.32. SOT404 : centre pin connected to mounting base. Notes 1. Epoxy meets UL94 V0 at 1/8". MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.33. SOT404 : minimum pad sizes for surface mounting. Notes 1. Plastic meets UL94 V0 at 1/8". June 1996 11 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor TOPFET BUK109-50GS DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1996 12 Rev 1.000