SHARC® Embedded Processor ADSP-21261 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, four serial ports, a digital applications interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU) On-chip memory—1M bit of on-chip SRAM and a dedicated 3M bit of on-chip mask-programmable ROM The ADSP-21261 is available in commercial and industrial temperature grades. For complete ordering information, see Ordering Guide on Page 44. Serial ports offer left-justified sample-pair and I2S support via 12 programmable and simultaneous receive or transmit pins, which support up to 24 transmit or 24 receive I2S channels of audio when all four serial ports (SPORTs) are enabled or six full duplex TDM streams of up to 128 channels per frame At 150 MHz (6.67 ns) core instruction rate, the ADSP-21261 operates at 900 MFLOPS peak/600 MFLOPS sustained performance whether operating on fixed- or floating-point data 300 MMACS sustained performance at 150 MHz Super Harvard Architecture—three independent buses for dual data fetch, instruction fetch, and nonintrusive, zerooverhead I/O Transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle, sustained 1.8G byte/s bandwidth at 150 MHz core instruction rate and 900M byte/s is available via DMA DUAL PORTED MEMORY BLOCK 0 CORE PROCESSOR INSTRUCTION CACHE 32 ⴛ 48-BIT TIMER DAG1 8 ⴛ 4 ⴛ 32 DAG2 8 ⴛ 4 ⴛ 32 SRAM 0.5M BIT PROG RAM SEQ UENCER ADDR DUAL PORTED MEMORY BLOCK 1 SRAM 0.5M BIT RO M 1.5M BIT ROM 1.5M BIT ADDR DATA DATA 32 PM ADDRESS BUS 32 DM ADDRESS BUS 64 PM DATA BUS 64 DM DATA BUS IOA (18) DMA CONTRO LLER PX REGI STER PROCESSING ELEMENT (PEX) IOD (32) 4 18 C HA NNE LS PRO CESSING ELEMENT (PEY) GPIO FLAGS/ IRQ /TIMEXP 4 SPI PORT (1) AD D R ES S/ D A TA BU S /GPIO 6 CON TR OL/GPIO SERIAL PORTS (4) JTAG TEST & EMULATION 20 SIGNAL RO UTI NG UNIT S INPUT DATA PORTS (8) PARALLEL DATA ACQUISITION PORT IOP REGISTERS (MEMORY MAPPED) 16 3 PARALLEL PORT CO NTROL, STATUS, DATA BUFFERS PRECISION CLOCK GENERATORS (2) 3 TIMERS (3) DIGITAL APPLICATIONS INTERFACE I/O PROCESSOR Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. ADSP-21261 ADDITIONAL KEY FEATURES 1M bit on-chip dual-ported SRAM (0.5M bit block 0, 0.5M bit block 1) for simultaneous access by core processor and DMA 3M bit on-chip dual-ported mask-programmable ROM (1.5M bit in block 0 and 1.5M bit in block 1) Dual data address generators (DAGs) with modulo and bitreverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing Single-instruction, multiple-data (SIMD) architecture provides: Two computational processing elements Concurrent execution—each processing element executes the same instruction, but operates on different data Parallelism in buses and computational units allows single cycle executions (with or without SIMD) of a multiply operation; an ALU operation; a dual memory read or write; and an instruction fetch Accelerated FFT butterfly computation through a multiply with add and subtract instruction DMA controller supports: 18 zero-overhead DMA channels for transfers between the ADSP-21261 internal memory and serial ports (eight), the input data port (IDP) (eight), the SPI-compatible port (one), and the parallel port (one) 32-bit background DMA transfers at core clock speed, in parallel with full-speed processor execution JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Also available in lead-free packages Digital applications interface includes four serial ports, two precision clock generators, an input data port, three programmable timers, and a signal routing unit Asynchronous parallel/external port provides: Access to asynchronous external memory 16 multiplexed address/data lines that can support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data 50M byte/s transfer rate for 150 MHz core rate 256 word page boundaries External memory access in a dedicated DMA channel 8-bit to 32-bit and 16-bit to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Rev. 0 | Serial ports provide: Four dual data line serial ports that operate at up to 37.5M bit/s for a 150 MHz core on each data line—each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample-pair and I2S support, programmable direction for up to 16 simultaneous receive or transmit channels using two I2S-compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the SHARC core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit (SRU) provides configurable and flexible connections between all DAI components, four serial ports, two precision clock generators, three timers, an input data port/parallel data acquisition port, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins (DAI_Px) Serial peripheral interface (SPI) Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open-drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM-based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/divider ratios Page 2 of 44 | March 2006 ADSP-21261 TABLE OF CONTENTS General Description ................................................. 4 Reset ............................................................. 20 ADSP-21261 Family Core Architecture ...................... 4 Interrupts ....................................................... 20 SIMD Computational Engine ............................... 4 Core Timer ..................................................... 20 Independent, Parallel Computation Units ................ 4 Timer PWM_OUT Cycle Timing ......................... 21 Data Register File ............................................... 5 Timer WDTH_CAP Timing ............................... 21 Single-Cycle Fetch of Instruction and Four Operands ............................................... 5 DAI Pin-to-Pin Direct Routing ............................ 22 Instruction Cache .............................................. 5 Flags ............................................................. 24 Data Address Generators with Zero-Overhead Hardware Circular Buffer Support ...................... 5 Memory Read—Parallel Port ............................... 25 Flexible Instruction Set ....................................... 6 ADSP-21261 Memory and I/O Interface Features ......... 6 Dual-Ported On-Chip Memory ............................. 6 DMA Controller ................................................ 6 Digital Applications Interface (DAI) ....................... 6 Serial Ports ....................................................... 6 Serial Peripheral (Compatible) Interface .................. 7 Parallel Port ..................................................... 7 Timers ............................................................ 8 Program Booting ............................................... 8 Phase-Locked Loop ............................................ 8 Power Supplies .................................................. 8 Target Board JTAG Emulator Connector .................... 8 Development Tools ............................................... 8 Evaluation Kit ..................................................... 10 Designing an Emulator-Compatible DSP Board (Target) ........................................... 10 Precision Clock Generator (Direct Pin Routing) ...... 23 Memory Write—Parallel Port ............................. 27 Serial Ports ..................................................... 29 Input Data Port (IDP) ....................................... 32 Parallel Data Acquisition Port (PDAP) .................. 33 SPI Protocol—Master ........................................ 34 SPI Protocol—Slave .......................................... 34 JTAG Test Access Port and Emulation .................. 36 Output Drive Currents ......................................... 37 Test Conditions .................................................. 37 Capacitive Loading .............................................. 37 Environmental Conditions .................................... 38 Thermal Characteristics ........................................ 38 136-Ball BGA Pin Configurations ............................... 39 144-Lead LQFP Pin Configurations ............................ 42 Package Dimensions ............................................... 43 Surface Mount Design .......................................... 44 Ordering Guide ..................................................... 44 Additional Information ......................................... 10 Pin Function Descriptions ........................................ 11 Address Data Pins as Flags ..................................... 14 REVISION HISTORY 3/06—Rev. 0: Initial Release Boot Modes ........................................................ 14 Core Instruction Rate to CLKIN Ratio Modes ............. 14 Address Data Modes ............................................. 14 ADSP-21261 Specifications ....................................... 15 Recommended Operating Conditions ....................... 15 Electrical Characteristics ........................................ 15 Absolute Maximum Ratings ................................... 16 ESD Sensitivity .................................................... 16 Timing Specifications ........................................... 17 Power-Up Sequencing ....................................... 18 Clock Input ..................................................... 19 Clock Signals ................................................... 19 Rev. 0 | Page 3 of 44 | March 2006 ADSP-21261 GENERAL DESCRIPTION The ADSP-21261 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices Super Harvard Architecture. The ADSP-21261 is source code compatible with the ADSP-2126x, ADSP-21160, and ADSP-21161 DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. Like other SHARC DSPs, the ADSP-21261 is a 32-bit/40-bit floating-point processor optimized for high performance signal processing applications with its dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface. As shown in the Functional Block Diagram on Page 1, the ADSP-21261 uses two computational units to deliver a five to 10 times performance increase over previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21261 DSP achieves an instruction cycle time of 6.67 ns at 150 MHz. With its SIMD computational hardware, the ADSP-21261 can perform 900 MFLOPS running at 150 MHz. Table 1 shows performance benchmarks for the ADSP-21261. Table 1. ADSP-21261 Benchmarks (at 150 MHz) • JTAG test access port • 8- or 16-bit parallel port that supports interfaces to off-chip memory peripherals • DMA controller • Four full-duplex serial ports • SPI-compatible interface • Digital applications interface that includes two precision clock generators (PCG), an input data port (IDP), four serial ports, eight serial interfaces, a 20-bit synchronous parallel input port, 10 interrupts, six flag outputs, six flag inputs, three programmable timers, and a flexible signal routing unit (SRU) Figure 2 shows one sample configuration of a SPORT using the precision clock generator to interface with an I2S ADC and an I2S DAC with a much lower jitter clock than the serial port would generate itself. Many other SRU configurations are possible. ADSP-21261 FAMILY CORE ARCHITECTURE Speed Benchmark Algorithm (at 150 MHz) 1024 Point Complex FFT (Radix 4, with reversal) 46 μs FIR Filter (per tap)1 2.5 ns 1 IIR Filter (per biquad) 10 ns Matrix Multiply (pipelined) [3×3] × [3×1] 22.5 ns [4×4] × [4×1] 40 ns Divide (y/×) 15 ns Inverse Square Root 22.5 ns 1 • On-chip dual-ported, mask-programmable ROM (3M bit) Assumes two files in multichannel SIMD mode. The ADSP-21261 continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. The block diagram of the ADSP-21261 on Page 1 illustrates the following architectural features: • Two processing elements, each containing an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle • Three programmable interval timers with PWM generation, PWM capture/pulse width measurement, and external event counter capabilities • On-chip dual-ported SRAM (1M bit) Rev. 0 | The ADSP-21261 is code compatible at the assembly level with the ADSP-2126x, ADSP-2136x, ADSP-2116x, and the first generation ADSP-2106x SHARC DSPs. The ADSP-21261 shares architectural features with the ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC family of DSPs, as detailed in the following sections. SIMD Computational Engine The ADSP-21261 contains two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing Page 4 of 44 | March 2006 ADSP-21261 ADS P-21261 CLKOUT CLKI N XTAL CLOCK 2 2 3 ADDR BOOTCFG1– 0 DATA FLAG 3– 1 RD OE WR WE FLAG0 CS PARALLE L PO RT RAM, ROM BOOT ROM I/O DEVICE DATA SRU ADDRESS DAI_ P1 DAI_P 2 DAI_P 3 SCLK0 SFS0 DAC (OP TIONAL) CLK FS S DAT LATCH AD15 –0 CONTROL ADC (OPTI ONAL) CLK FS S DAT ALE CLK_ CFG 1– 0 SD0A SD0B DAI_ P1 8 DAI_ P19 DAI_P 20 S PORT0 SP ORT1 SPO RT2 S PORT3 CLK FS DAI RESE T PCG A P CGB J TAG 6 Figure 2. ADSP-21261 System Sample Configuration element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit single precision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats. Data Register File A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2126x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Single-Cycle Fetch of Instruction and Four Operands The ADSP-21261 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With the ADSP-21261’s separate program and data memory buses and on-chip instruction cache, Rev. 0 | the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-21261 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The ADSP-21261’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21261 contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Page 5 of 44 | March 2006 ADSP-21261 Flexible Instruction Set Digital Applications Interface (DAI) The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the ADSP-21261 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. The digital applications interface provides the ability to connect various peripherals to any of the SHARC’s DAI pins (DAI_P20–1). ADSP-21261 MEMORY AND I/O INTERFACE FEATURES The ADSP-21261 adds the following architectural features to the SIMD SHARC family core: Dual-Ported On-Chip Memory The ADSP-21261 contains one megabit of internal SRAM and three megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data storage (see memory map, Figure 3). Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor. The dual-ported memory, in combination with three separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle. The ADSP-21261’s SRAM can be configured as a maximum of 48K words of 32-bit data, 46K words of 16-bit data, 31.5K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. DMA Controller The ADSP-21261’s on-chip DMA controller allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-21261’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) port, the IDP (input data port), parallel data acquisition port (PDAP), or the parallel port. Eighteen channels of DMA are available on the ADSP-21261—one for the SPI, eight via the serial ports, eight via the input data port, and one via the processor’s parallel port. Programs can be downloaded to the ADSP21261 using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Rev. 0 | Connections are made using the signal routing unit (SRU, shown in the block diagram on Page 1). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI also includes four serial ports, two precision clock generators (PCGs), an input data port (IDP), six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-21261 core, configurable as either eight channels of I2S or serial data, or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-21261’s serial ports. For complete information on using the DAI, see the ADSP-2126x SHARC DSP Peripherals Manual. Serial Ports The ADSP-21261 features four full-duplex synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as the Analog Devices AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has its own dedicated DMA channel. Serial ports are enabled via eight programmable and simultaneous receive or transmit pins that support up to 18 transmit or 18 receive channels of serial data when all six SPORTs are enabled, or four full-duplex TDM streams of 128 channels per frame. The serial ports operate at up to one-quarter of the DSP core clock rate, providing each with a maximum data rate of 37.5M bit/s for a 150 MHz core. Serial port data can be automatically transferred to and from on-chip memory via a dedicated DMA. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in four modes: • Standard DSP serial mode • Multichannel (TDM) mode • I2S mode • Left-justified sample pair mode Page 6 of 44 | March 2006 ADSP-21261 INTERNAL MEMORY SPACE LONG WORD ADDRESSING NORMAL WORD ADDRESSING SHORT WORD ADDRESSING IOP REGISTERS 0x0000 0000–0x0003 FFFF IOP REGISTERS 0x0000 0000–0x0003 FFFF IOP REGISTERS 0x0000 0000–0x0003 FFFF BLOCK 0 SRAM (0.5M B IT) 0x0004 0000–0x0004 1FFF BLOCK 0 SRAM ( 0.5M BIT) 0x0008 0000–0x0008 3FFF B LOCK 0 SRAM (0.5M BIT) 0x0010 0000–0x0010 7FFF RESERVED 0x0004 2000–0x0005 7FFF RESERVED 0x0008 4000 - 0x000A FFFF R ESERVED 0x0010 8000–0x0015 FFFF BLOCK 0 R OM (1.5M B IT) 0x0005 8000–0x0002 FFFF BLOCK 0 ROM (1.5M BIT) 2 0x000B 0000–0x000B BFFF BLOCK 0 ROM (1.5M BIT) 0x0016 0000–0x0017 7FFF RESERVED 0x0005 3000–0x0005 FFFF BLOCK 1 SRAM (0.5M B IT) 0x0006 0000–0x0006 1FFF RESERVED 0x0006 2000–0x0007 7FFF BLOCK 1 ROM (1.5M BIT) 0x0007 8000–0x0007 DFFF RESERVED 0x0007 E000–0x0007 FFFF RESERVED 0x000B C000–0x000B FFFF RESERVED 0x0017 8FFF–0x0017 FFFF BLOCK 1 SRAM (0.5M B IT) 0x000C 0000–0x000C 3FFF B LOCK 1 SRAM (0.5M BIT) 0x0018 0000–0x0018 7FFF RESERVED 0x000C 4000–0x000E FFFF RESERVED 0x0018 8000–0x001D FFFF BLOCK 1 ROM (1.5M BIT) 3 0x000F 0000–0x000F BFFF BLOCK 1 ROM ( 1.5M BIT) 0x001E 0000–0x001F 7FFF RESERVED 0x000F C000–0x000F FFFF R ESERVED 0x000 EXTERNAL MEMORY SPACE RESERVED 0x0020 0000–0x00FF FFFF EXTERN AL DMA ADDRESS SPACE 1 0x0100 0000–0x02FF FFFF 1 EXTERNAL MEMORY IS NOT DIRECTLY A CCESSIBLE BY THE CORE. DMA MUST BE U SED TO READ OR WRITE TO THIS MEM O R Y US ING THE S P I O R P ARA LL EL P OR T. 2 B LOC K 0 ROM HA S A 48-BIT ADDRESS RA NGE ( 0xA0000–0xA7 FFFF). 3 B LOC K 1 ROM HA S A 48-BIT ADDRESS RA NGE ( 0xE0000–0xE7 FFFF). RESERVED 0x0300 0000–0x3FFF FFFF Figure 3. ADSP-21261 Memory Map Serial Peripheral (Compatible) Interface Serial peripheral interface is an industry-standard synchronous serial link, enabling the ADSP-21261 SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21261 SPI-compatible peripheral implementation also features programmable baud rates up to Rev. 0 | 37.5 MHz, clock phases, and polarities. The ADSP-21261 SPIcompatible port uses open-drain drivers to support a multimaster configuration and to avoid data contention. Parallel Port The parallel port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15–0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8- or 16bit, the maximum data transfer rate is one-third the core clock speed. As an example, a clock rate of 200 MHz is equivalent to 66M byte/s, and a clock rate of 150 MHz is equivalent to 50M byte/s. Page 7 of 44 | March 2006 ADSP-21261 DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (address latch enable) pins are the control pins for the parallel port. in Figure 4 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip. 100nF Timers 10nF 1nF AVDD VDDINT The ADSP-21261 has a total of four timers: a core timer able to generate periodic software interrupts, and three generalpurpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: ADSP-21261 HI Z FERRITE BEAD CHIP • Pulse waveform generation mode AVSS LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS • Pulse width count/capture mode Figure 4. Analog Power Filter Circuit • External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired output signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently. Program Booting The internal memory of the ADSP-21261 boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOTCFG1–0) pins. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Phase-Locked Loop The ADSP-21261 uses an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power-up, the CLKCFG1–0 pins are used to select ratios of 16:1, 8:1, and 3:1. After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from 1 to 32 and software configurable divisor values of 1, 2, 4, 8, and 16. Power Supplies The ADSP-21261 has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 4. (A recommended ferrite chip is the muRata BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified Rev. 0 | TARGET BOARD JTAG EMULATOR CONNECTOR Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21261 processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate emulator hardware user’s guide. DEVELOPMENT TOOLS The ADSP-21261 is supported by a complete set of CROSSCORE®† software and hardware development tools, including Analog Devices emulators and VisualDSP++®‡ development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21261. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The ADSP-21261 SHARC DSP has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in † ‡ CROSSCORE is a registered trademark of Analog Devices, Inc. VisualDSP++ is a registered trademark of Analog Devices, Inc. Page 8 of 44 | March 2006 ADSP-21261 complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: • View mixed C/C++ and assembly code (interleaved source and object information) • Insert breakpoints • Set conditional breakpoints on registers, memory, and stacks • Trace instruction execution • Perform linear or statistical profiling of program execution • Fill, dump, and graphically plot the contents of memory VisualDSP++ Component Software Engineering (VCSE) is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. It also is used for downloading components from the Web, dropping them into the application, and publishing component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with a drag of the mouse, and examine runtime stack and heap usage. The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Thirdparty software tools include DSP libraries, real-time operating systems, and block diagram design tools. • Perform source level debugging • Create custom debugger windows The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: • Control how the development tools process inputs and generate outputs • Maintain a one-to-one correspondence with the tools’ command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK. Rev. 0 | Page 9 of 44 | March 2006 ADSP-21261 EVALUATION KIT ADDITIONAL INFORMATION ®† Analog Devices offers a range of EZ-KIT Lite evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. This data sheet provides a general overview of the ADSP-21261 architecture and functionality. For detailed information on the ADSP-2126x family core architecture and instruction set, refer to the ADSP-2126x DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor incircuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows incircuit programming of the on-board flash device to store userspecific boot code, enabling the board to run as a standalone unit, without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting an Analog Devices JTAG emulator to the EZ-KIT Lite board enables high speed, nonintrusive emulation. DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. † EZ-KIT Lite is a registered trademark of Analog Devices, Inc. Rev. 0 | Page 10 of 44 | March 2006 ADSP-21261 PIN FUNCTION DESCRIPTIONS ADSP-21261 pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for the following: • DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI, and AD15–0 (NOTE: These pins have internal pull-up resistors.) The following symbols appear in the Type column of Table 2: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state. Table 2. Pin Function Descriptions Pin AD15–0 Type I/O/T RD O WR O ALE O FLAG3–0 I/O/A State During and After Reset AD15–0 pins are driven low both during and after reset Function Parallel Port Address/Data. The ADSP-21261 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address Data Modes on Page 14 for details of the AD pin operation. For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 external address bits, A23–8; ALE is used in conjunction with an external latch to retain the values of the A23–8. For 16-bit mode: ALE is automatically asserted whenever a change occurs in the address bits, A15–0; ALE is used in conjunction with an external latch to retain the values of the A15–0. To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port. See Table 3 on Page 14 for a list of how the AD15–0 pins map to the flag pins. When configured in the IDP_PDAP_CTL register, the IDP Channel 0 can use these pins for parallel input data. Output only, driven Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or high1 16-bit data from an external memory device. When AD15–0 are flags, this pin remains deasserted. Output only, driven Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or high1 16-bit data to an external memory device. When AD15–0 are flags, this pin remains deasserted. Output only, driven Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a low1 new address on the parallel port address pin. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD15–0 are flags, this pin remains deasserted. Three-state Flag Pins. Each FLAG pin is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. These pins can be used as an SPI slave select output during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0. When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1. When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2. When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which indicates that the system timer has expired. Rev. 0 | Page 11 of 44 | March 2006 ADSP-21261 Table 2. Pin Function Descriptions (Continued) State During and After Reset Three-state with programmable pull-up Pin DAI_P20–1 Type I/O/T SPICLK I/O Three-state with pull-up enabled SPIDS I Input only MOSI I/O (O/D) Three-state with pull-up enabled MISO I/O (O/D) Three-state with pull-up enabled BOOTCFG1–0 I Input only Function Digital Applications Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the SRU may be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators, and timers to the DAI_P20–1 pins. These pins have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register. Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master can transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode. Serial Peripheral Interface Slave Device Select. An active low signal used to select the DSP as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode the DSP’s SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to VDDEXT on the master device. For ADSP-21261 to ADSP-21261 SPI interaction, any of the master ADSP-21261’s flag pins can be used to drive the SPIDS signal on the ADSP-21261 SPI slave device. SPI Master Out Slave In. If the ADSP-21261 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21261 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an ADSP-21261 SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode. SPI Master In Slave Out. If the ADSP-21261 is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21261 is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an ADSP-21261 SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI slaves, the DSP’s MISO pin may be disabled by setting (=1) Bit 5 (DMISO) of the SPICTL register. Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins must be valid before reset is asserted. See Table 4 on Page 14 for a description of the boot modes. Rev. 0 | Page 12 of 44 | March 2006 ADSP-21261 Table 2. Pin Function Descriptions (Continued) Pin CLKIN Type I State During and After Reset Input only XTAL O Output only2 CLKCFG1–0 I Input only RSTOUT/CLKOUT O Output only RESET I/A Input only TCK I Input only3 TMS I/S TDI I/S TDO TRST O I/A Three-state with pull-up enabled Three-state with pull-up enabled Three-state4 Three-state with pull-up enabled EMU O (O/D) VDDINT P VDDEXT P AVDD P AVSS GND G G Three-state with pull-up enabled Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21261 clock input. It configures the ADSP-21261 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21261 to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or operated below the specified frequency. Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See Table 5 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. Reset Out/Local Clock Out. Drives out the core reset signal to an external device. CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out. Processor Reset. Resets the ADSP-21261 to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21261. Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5 kΩ internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21261. TRST has a 22.5 kΩ internal pull-up resistor. Emulation Status. Must be connected to the Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ internal pullup resistor. Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor (13 pins on the BGA package, 32 pins on the LQFP package). I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the LQFP package). Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplies on Page 8. Analog Power Supply Return. Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package). 1 RD, WR, and ALE are continuously driven by the DSP and will not be three-stated. Output only is a three-state driver with its output path always enabled. 3 Input only is a three-state driver, with both output path and pull-up disabled. 4 Three-state is a three-state driver, with pull-up disabled. 2 Rev. 0 | Page 13 of 44 | March 2006 ADSP-21261 ADDRESS DATA PINS AS FLAGS ADDRESS DATA MODES To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port. Table 6 shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23–A8 when asserted, followed by address bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit data transfers, ALE latches address bits A15–A0 when asserted, followed by data bits D15–D0 when deasserted. Table 3. AD15–0 to FLAG Pin Mapping AD Pin AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Flag Pin FLAG8 FLAG9 FLAG10 FLAG11 FLAG12 FLAG13 FLAG14 FLAG15 FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 Table 6. Address/Data Mode Selection EP Data Mode 8-bit 8-bit 16-bit 16-bit BOOT MODES Table 4. Boot Mode Selection BOOTCFG1–0 00 01 10 11 Booting Mode SPI Slave Boot SPI Master Boot Parallel Port Boot via EPROM Internal Boot Mode (ROM code only) CORE INSTRUCTION RATE TO CLKIN RATIO MODES Table 5. Core Instruction Rate/CLKIN Ratio Selection CLKCFG1–0 00 01 10 11 Core to CLKIN Ratio 3:1 16:1 8:1 Reserved Rev. 0 | Page 14 of 44 | March 2006 ALE Asserted Deasserted Asserted Deasserted AD7–0 Function A15–8 D7–0 A7–0 D7–0 AD15–8 Function A23–16 A7–0 A15–8 D15–8 ADSP-21261 ADSP-21261 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter1 Min Max Unit VDDINT Internal (Core) Supply Voltage 1.14 1.26 V AVDD Analog (PLL) Supply Voltage 1.14 1.26 V VDDEXT External (I/O) Supply Voltage 3.13 3.47 V 2.0 VDDEXT + 0.5 V –0.5 +0.8 VIH VIL 2 High Level Input Voltage @ VDDEXT = max 2 Low Level Input Voltage @ VDDEXT = min 3 V VIH_CLKIN High Level Input Voltage @ VDDEXT = max 1.74 VDDEXT + 0.5 V VIL_CLKIN Low Level Input Voltage @ VDDEXT = min –0.5 +1.19 V 0 +70 °C TAMB Ambient Operating Temperature 4, 5 1 Specifications subject to change without notice. Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, and TRST. 3 Applies to input pin CLKIN. 4 See Thermal Characteristics on Page 38 for information on thermal specifications. 5 See Engineer-to-Engineer Note (No. 216) for further information. 2 ELECTRICAL CHARACTERISTICS Parameter1 Test Conditions 2 VOH High Level Output Voltage VOL 2 Low Level Output Voltage Min @ VDDEXT = min, IOH = –1.0 mA @ VDDEXT = min, IOL = 1.0 mA 4, 5 3 Max 2.4 3 V 0.4 V 10 μA IIH High Level Input Current IIL Low Level Input Current 4 @ VDDEXT = max, VIN = 0 V 10 μA IILPU Low Level Input Current Pull-Up5 @ VDDEXT = max, VIN = 0 V 200 μA IOZH Three-State Leakage Current 6, 7, 8 @ VDDEXT = max, VIN = VDDEXT max 10 μA @ VDDEXT = max, VIN = 0 V 10 μA @ VDDEXT = max, VIN = 0 V 200 μA tCCLK = 6.67 ns, VDDINT = 1.2 V, TAMB = +25°C 375 mA AVDD = max 10 mA fIN = 1 MHz, TCASE = 25°C, VIN = 1.2 V 4.7 pF IOZL IOZLPU IDD-INTYP AIDD CIN @ VDDEXT = max, VIN = VDDEXT max Unit Three-State Leakage Current 6 Three-State Leakage Current Pull-Up Supply Current (Internal) Supply Current (Analog) Input Capacitance 9, 10, 11 11 12, 13 7 1 Specifications subject to change without notice. Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, and XTAL. 3 See Output Drive Currents on Page 37 for typical drive current capabilities. 4 Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, and CLKIN. 5 Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, and TDI. 6 Applies to three-statable pins: FLAG3–0. 7 Applies to three-statable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, MISO, and MOSI. 8 Applies to open-drain output pins: EMU, MISO, and MOSI. 9 Typical internal current data reflects nominal operating conditions. 10 See Engineer-to-Engineer Note (No. 216) for further information. 11 Characterized, but not tested. 12 Applies to all signal pins. 13 Guaranteed, but not tested. 2 Rev. 0 | Page 15 of 44 | March 2006 ADSP-21261 ABSOLUTE MAXIMUM RATINGS Parameter Internal (Core) Supply Voltage (VDDINT)1 Analog (PLL) Supply Voltage (AVDD)1 External (I/O) Supply Voltage (VDDEXT)1 Input Voltage –0.5 V to VDDEXT1 Output Voltage Swing –0.5 V to VDDEXT1 Load Capacitance1 Storage Temperature Range1 Junction Temperature Under Bias 1 Rating –0.3 V to +1.4 V –0.3 V to +1.4 V –0.3 V to +3.8 V +0.5 V +0.5 V 200 pF –65°C to +150°C 125°C Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD SENSITIVITY CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21261 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 16 of 44 | March 2006 ADSP-21261 TIMING SPECIFICATIONS The ADSP-21261’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’s internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1–0 pins. To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports). The ADSP-21261’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP’s internal clock (the clock source for the parallel port logic and I/O pads). Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control (Table 7 and Table 8). Table 7. ADSP-21261 CLKOUT and CCLK Clock Generation Operation Timing Requirements CLKIN CCLK Description Input Clock Core Clock CLKOUT CLKIN XTAL 1 PLL 3:1, 8:1, 16:1 CCLK (CORE CLOCK) Figure 5. Core Clock and System Clock Relationship to CLKIN Switching characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Calculation 1/tCK 1/tCCLK Description1 CLKIN Clock Period (Processor) Core Clock Period Serial Port Clock Period = (tCCLK) × SR SPI Clock Period = (tCCLK) × SPIR where: SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV) SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register) DAI_Px = serial port clock SPICLK = SPI clock Figure 5 shows core to CLKIN ratios of 3:1, 8:1, and 16:1 with external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP-2126x SHARC DSP Core Manual. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 30 on Page 37 under Test Conditions for voltage reference levels. Rev. 0 | PLLICLK CLKCFG1–0 Table 8. Clock Periods Timing Requirements tCK tCCLK tSCLK tSPICLK XTAL OSC Page 17 of 44 | March 2006 ADSP-21261 Power-Up Sequencing The timing requirements for DSP startup are given in Table 9 and Figure 6. Table 9. Power-Up Sequencing (DSP Startup) Parameter Min Max Unit Timing Requirements tRSTVDD RESET Low Before VDDINT/VDDEXT On tIVDDEVDD VDDINT On Before VDDEXT 0 1 ns –50 +200 0 200 ms tCLKVDD CLKIN Valid After VDDINT/VDDEXT Valid tCLKRST CLKIN Valid Before RESET Deasserted 102 μs tPLLRST PLL Control Setup Before RESET Deasserted 203 μs ms Switching Characteristic tCORERST DSP Core Reset Deasserted After RESET Deasserted 4096tCK 4, 5 1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer’s data sheet for startup time. Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Based on CLKIN cycles. 4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I/O pins. 5 The 4096 cycle count depends on tSRST specification in Table 11. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum. 2 RESET tRSTVDD VDDINT tIVDDEVDD VDDEXT tCLKVDD CLKIN tCLKRST CLKCFG1–0 tPLLRST RSTOUT* *MULTIPLEXED WITH CLKOUT Figure 6. Power-Up Sequencing Rev. 0 | Page 18 of 44 | March 2006 tCORERST ADSP-21261 Clock Input See Table 10 and Figure 7. Table 10. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low CLKIN Width High tCKH tCKRF CLKIN Rise/Fall (0.4 V–2.0 V) tCCLK CCLK Period3 Min Max Unit 201 7.51 7.51 1602 802 802 3 10 ns ns ns ns ns 6.66 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL. Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL. 3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. 1 2 tCK CLKIN tCKH tCKL Figure 7. Clock Input Clock Signals The ADSP-21261 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21261 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 8 shows the component connections used for a crystal operating in fundamental mode. Note that the 150 MHz clock rate is achieved using a 9.375 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN). CLKIN C1 1M⍀ X1 XTAL C2 NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL SELECTION MUST COMPLY WITH CLKCFG1–0 = 10 OR = 01. Figure 8. 150 MHz Operation with a 9.375 MHz Fundamental Mode Crystal Rev. 0 | Page 19 of 44 | March 2006 ADSP-21261 Reset See Table 11 and Figure 9. Table 11. Reset Parameter Timing Requirements tWRST RESET Pulse Width Low1 tSRST RESET Setup Before CLKIN Low 1 Min Max Unit 4tCK 8 ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 9. Reset Interrupts The timing specification in Table 12 and Figure 10 applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1 pins when configured as interrupts. Table 12. Interrupts Parameter Timing Requirement tIPW IRQx Pulse Width Min Max 2 × tCCLK +2 DAI_P20–1 (FLAG2–0) (IRQ2–0) Unit ns tIPW Figure 10. Interrupts Core Timer The timing specification in Table 13 and Figure 11 applies to FLAG3 when it is configured as the core timer (CTIMER). Table 13. Core Timer Parameter Switching Characteristic CTIMER Pulse Width tWCTIM Min Max 4 × tCCLK – 1 FLAG3 (CTIMER) tWCTIM Figure 11. Core Timer Rev. 0 | Page 20 of 44 | March 2006 Unit ns ADSP-21261 Timer PWM_OUT Cycle Timing The timing specification in Table 14 and Figure 12 applies to Timer PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 14. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min Max Unit 2 tCCLK – 1 2(231 – 1) tCCLK ns Min Max Unit 2 tCCLK 2(231 – 1) tCCLK ns tPWMO DAI_P20–1 (TIMER) Figure 12. Timer PWM_OUT Timing Timer WDTH_CAP Timing The timing specification in Table 15 and Figure 13 applies to Timer WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 15. Timer Width Capture Timing Parameter Timing Requirement tPWI Timer Pulse Width tPWI DAI_P20–1 (TIMER) Figure 13. Timer Width Capture Timing Rev. 0 | Page 21 of 44 | March 2006 ADSP-21261 DAI Pin-to-Pin Direct Routing See Table 16 and Figure 14 for direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 16. DAI Pin-to-Pin Direct Routing Parameter Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid Min Max Unit 1.5 10 ns DAI_Pn DAI_Pm tDPIO Figure 14. DAI Pin-to-Pin Direct Routing Rev. 0 | Page 22 of 44 | March 2006 ADSP-21261 cases where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P07 – DAI_P20). Precision Clock Generator (Direct Pin Routing) The timing in Table 17 and Figure 15 is valid only when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other Table 17. Precision Clock Generator (Direct Pin Routing) Parameter Timing Requirements tPCGIW Input Clock Pulse Width tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input Clock PCG Trigger Hold After Falling Edge of PCG Input Clock tHTRIG Min 20 2 2 Switching Characteristics PCG Output Clock and Frame Sync Active Edge Delay After PCG Input tDPCGIO Clock Falling Edge 2.5 tDTRIG PCG Output Clock and Frame Sync Delay After PCG Trigger 2.5 + 2.5 × tPCGOW Output Clock Pulse Width 40 tPCGOW tSTRIG DAI_Pn PCG_TRIGx_I tHTRIG tPCGIW DAI_Pm PCG_EXTx_I (CLKIN) tDPCGIO DAI_Py PCG_CLKx_O tPCGOW DAI_Pz PCG_FSx_O tDTRIG Figure 15. Precision Clock Generator (Direct Pin Routing) Rev. 0 | Page 23 of 44 | March 2006 Max Unit ns ns ns 10 ns 10 + 2.5 × tPCGOW ns ns ADSP-21261 Flags The timing specifications in Table 18 and Figure 16 apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface. See Table 2 on Page 11 for more information on flag use. Table 18. Flags Parameter Timing Requirement tFIPW FLAG3–0 IN Pulse Width Min Switching Characteristic tFOPW FLAG3–0 OUT Pulse Width Unit 2 × tCCLK + 3 ns 2 × tCCLK – 1 ns DAI_P20–1 (FLAG3–0IN) (AD15–0) tFIPW DAI_P20–1 (FLAG3–0OUT ) (AD15–0) tFOPW Figure 16. Flags Rev. 0 | Max Page 24 of 44 | March 2006 ADSP-21261 Memory Read—Parallel Port The specifications in Table 19, Table 20, Figure 17, and Figure 18 are for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21261 is accessing external memory space. Table 19. 8-Bit Memory Read Cycle Parameter Timing Requirements tDRS Address/Data7–0 Setup Before RD High tDRH Address/Data7–0 Hold After RD High Address 15–8 to Data Valid tDAD Min Unit D + 0.5 × tCCLK – 3.5 ns ns ns 3.3 0 Switching Characteristics ALE Pulse Width tALEW tALERW ALE Deasserted to Read/Write Asserted tADAS Address/Data15–0 Setup Before ALE Deasserted1 tADAH Address/Data15–0 Hold After ALE Deasserted1 tALEHZ ALE Deasserted1 to Address/Data7–0 in High Z tRW RD Pulse Width Address/Data15–8 Hold After RD High tADRH D = (data cycle duration) × tCCLK H = tCCLK (if a hold cycle is specified, else H = 0) 1 Max 2 × tCCLK – 2 1 × tCCLK – 0.5 2.5 × tCCLK – 2.0 0.5 × tCCLK – 0.8 0.5 × tCCLK – 0.8 D–2 0.5 × tCCLK – 1 + H 0.5 × tCCLK + 2.0 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low. ALE tALEW tALERW RD tRW WR tALEHZ tADAS AD15–8 tADAH tADRH VALID ADDRESS VALID ADDRESS tDRS AD7–0 VALID ADDRESS tDAD Figure 17. 8-Bit Memory Read Cycle Rev. 0 | Page 25 of 44 | March 2006 tDRH VALID DATA ns ns ns ns ns ns ns ADSP-21261 Table 20. 16-Bit Memory Read Cycle Parameter Timing Requirements tDRS tDRH Min Address/Data15–0 Setup Before RD high Address/Data15–0 Hold After RD high Max Unit 3.3 0 ns ns 2 × tCCLK – 2 1 × tCCLK – 0.5 2.5 × tCCLK – 2.0 0.5 × tCCLK – 0.8 0.5 × tCCLK – 0.8 D–2 ns ns ns ns ns ns Switching Characteristics ALE Pulse Width tALEW tALERW ALE Deasserted to Read/Write Asserted tADAS Address/Data15–0 Setup Before ALE Deasserted1 Address/Data15–0 Hold After ALE Deaserted1 tADAH tALEHZ ALE Deasserted1 to Address/Data15–0 in High Z tRW RD Pulse Width D = (data cycle duration) × tCCLK H = tCCLK (if a hold cycle is specified, else H = 0) 1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low. ALE tALEW tALERW RD tRW WR tADAH tADAS AD15–0 tDRS VALID DATA VALID ADDRESS tALEHZ Figure 18. 16-Bit Memory Read Cycle Rev. 0 | tDRH Page 26 of 44 | March 2006 0.5tCCLK + 2.0 ADSP-21261 Memory Write—Parallel Port Use the specifications in Table 21, Table 22, Figure 19, and Figure 20 for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21261 is accessing external memory space. Table 21. 8-Bit Memory Write Cycle Parameter Switching Characteristics tALEW ALE Pulse Width tALERW ALE Deasserted to Read/Write Asserted Address/Data15–0 Setup Before ALE Deasserted1 tADAS tADAH Address/Data15–0 Hold After ALE Deasserted1 tWW WR Pulse Width tADWL Address/Data15–8 to WR Low tADWH Address/Data15–8 Hold After WR High tALEHZ ALE Deasserted1 to Address/Data15–0 in High Z Address/Data7–0 Setup Before WR High tDWS tDWH Address/Data7–0 Hold After WR High tDAWH Address/Data to WR High D = (data cycle duration) × tCCLK H = tCCLK (if a hold cycle is specified, else H = 0) 1 Min Max 2 × tCCLK – 2 1 × tCCLK – 0.5 2.5 × tCCLK – 2.0 0.5 × tCCLK – 0.8 D–2 0.5 × tCCLK – 1.5 0.5 × tCCLK – 1 + H 0.5 × tCCLK – 0.8 D 0.5 × tCCLK – 1.5 + H D On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low. tALERW ALE tALEW tDAWH WR tWW RD tALEHZ tADAS AD15–8 tADWL tADWH tADAH VALID ADDRESS VALID ADDRESS tDWS AD7–0 VALID ADDRESS tDWH VALID DATA Figure 19. 8-Bit Memory Write Cycle Rev. 0 | Page 27 of 44 | March 2006 0.5tCCLK + 2.0 Unit ns ns ns ns ns ns ns ns ns ns ns ADSP-21261 Table 22. 16-Bit Memory Write Cycle Parameter Switching Characteristics tALEW ALE Pulse Width ALE Deasserted to Read/Write Asserted tALERW tADAS Address/Data 15–0 Setup Before ALE Deasserted1 tADAH Address/Data15–0 Hold After ALE Deasserted1 tWW WR Pulse Width tALEH ALE Deasserted1 to Address/Data15–0 in High Z tDWS Address/Data15–0 Setup Before WR High tDWH Address/Data15–0 Hold After WR High D = (data cycle duration) × tCCLK H = tCCLK (if a hold cycle is specified, else H = 0) 1 Min Max 2 × tCCLK – 2 1 × tCCLK – 0.5 2.5 × tCCLK – 2.0 0.5 × tCCLK – 0.8 D–2 0.5 × tCCLK – 0.8 D 0.5 × tCCLK – 1.5 + H On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low. ALE tALEW tALERW tWW WR RD tALEH tADAS AD15–0 tADAH VALID ADDRESS tDWS VALID DATA Figure 20. 16-Bit Memory Write Cycle Rev. 0 | Page 28 of 44 | March 2006 tDWH 0.5tCCLK + 2.0 Unit ns ns ns ns ns ns ns ns ADSP-21261 Serial Ports To determine whether communication is possible between two devices at clock speed n, the specifications in Table 23, Table 24, Table 25, Table 26, Figure 21, and Figure 22 must be confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay and data setup and hold; and 3) SCLK width. Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 23. Serial Ports—External Clock Parameter Timing Requirements tSFSE FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)1 tHFSE FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode)1 Receive Data Setup Before Receive SCLK1 tSDRE tHDRE Receive Data Hold After SCLK1 tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE FS Delay After SCLK (Internally Generated FS in Either Transmit or Receive Mode)2 tHOFSE FS Hold After SCLK (Internally Generated FS in Either Transmit or Receive Mode)2 tDDTE Transmit Data Delay After Transmit SCLK2 tHDTE Transmit Data Hold After Transmit SCLK2 1 2 Min Max Unit 2.5 ns 2.5 2.5 2.5 7 20 ns ns ns ns ns 7 ns 7 ns ns ns 2 2 Referenced to sample edge. Referenced to drive edge. Table 24. Serial Ports—Internal Clock Parameter Timing Requirements tSFSI FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)1 tHFSI FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode)1 tSDRI Receive Data Setup Before SCLK1 tHDRI Receive Data Hold After SCLK1 Switching Characteristics tDFSI FS Delay After SCLK (Internally Generated FS in Transmit Mode)2 tHOFSI FS Hold After SCLK (Internally Generated FS in Transmit Mode)2 tDFSI FS Delay After SCLK (Internally Generated FS in Receive Mode)2 FS Hold After SCLK (Internally Generated FS in Receive Mode)2 tHOFSI tDDTI Transmit Data Delay After SCLK2 tHDTI Transmit Data Hold After SCLK2 tSCLKIW Transmit or Receive SCLK Width 1 Referenced to the sample edge. 2 Referenced to drive edge. Rev. 0 | Page 29 of 44 | March 2006 Min Max Unit 6 ns 1.5 6 1.5 ns ns ns 3 –1.0 3 –1.0 3 –1.0 0.5tSCLK – 2 0.5tSCLK + 2 ns ns ns ns ns ns ns ADSP-21261 Table 25. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SCLK1 Data Disable from External Transmit SCLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SCLK1 1 Min Max Unit 7 ns ns ns Max Unit 7 ns ns 2 –1 Referenced to drive edge. Table 26. Serial Ports—External Late Frame Sync Parameter Min Switching Characteristics tDDTLFSE Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 01 tDDTENFS Data Enable for MCE = 1, MFD = 01 0.5 1 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0. EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DAI_P20–1 (SCLK) DRIVE SAMPLE tSFSE/I DRIVE tHFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 1ST BIT 2ND BIT tDDTLFSE LATE EXTERNAL TRANSMIT FS DAI_P20–1 (SCLK) DRIVE SAMPLE tSFSE/I DRIVE tHFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 1ST BIT 2ND BIT tDDTLFSE NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P[20:1] PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS. Figure 21. External Late Frame Sync1 1 This figure reflects changes made to support left-justified sample pair mode. Rev. 0 | Page 30 of 44 | March 2006 ADSP-21261 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKIW tSCLKW DAI_P20–1 (SCLK) DAI_P20–1 (SCLK) tDFSI tDFSE tHFSI tSFSI tHOFSI DAI_P20–1 (FS) tHFSE tSFSE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) tSDRE tHDRE DAI_P20–1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE SAMPLE EDGE tSCLKIW tSCLKW DAI_P20–1 (SCLK) DAI_P20–1 (SCLK) tDFSI tDFSE tHOFSI tHFSI tSFSI tHOFSE DAI_P20–1 (FS) tSFSE tHFSE DAI_P20–1 (FS) tDDTI tHDTI tDDTE tHDTE DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DRIVE EDGE DAI_P20–1 SCLK (EXT) SCLK tDDTEN DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20–1 SCLK (INT) tDDTIN DAI_P20–1 (DATA CHANNEL A/B) Figure 22. Serial Ports Rev. 0 | Page 31 of 44 | March 2006 tDDTTE ADSP-21261 Input Data Port (IDP) The timing requirements for the IDP are given in Table 27 and Figure 23. IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 27. Input Data Port (IDP) Parameter Timing Requirements tSISFS FS Setup Before SCLK Rising Edge1 tSIHFS FS Hold After SCLK Rising Edge1 SData Setup Before SCLK Rising Edge1 tSISD tSIHD SData Hold After SCLK Rising Edge1 tIDPCLKW Clock Width tIDPCLK Clock Period 1 Min 2.5 2.5 2.5 2.5 7 20 Max Unit ns ns ns ns ns ns DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either CLKIN or any of the DAI pins. tIDPCLK SAMPLE EDGE DAI_P20–1 (SCLK) tIDPCLKW tSISFS tSIHFS DAI_P20–1 (FS) tSISD tSIHD DAI_P20–1 (SDATA) Figure 23. Input Data Port (IDP) Rev. 0 | Page 32 of 44 | March 2006 ADSP-21261 Note that the most significant 16 bits of external PDAP data can be provided through either the parallel port AD15–0 or the DAI_P20–5 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DAI_P20–1 pins or at the AD15–0 pins. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 28 and Figure 24. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Peripherals Manual. Table 28. Parallel Data Acquisition Port (PDAP) 1 Parameter Timing Requirements tSPCLKEN PDAP_CLKEN Setup Before PDAP_CLK Sample Edge1 tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge1 tPDSD tPDHD PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge1 tPDCLKW Clock Width tPDCLK Clock Period Min Max Unit 2.5 2.5 2.5 2.5 7 20 ns ns ns ns ns ns Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word tPDSTRB PDAP Strobe Pulse Width 2 × tCCLK 1 × tCCLK – 1 ns ns Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG. SAMPLE EDGE t PDCLK tPDCLKW DAI_P20–1 (PDAP_CLK) t SPCLKEN tHPCLKEN DAI_P20–1 (PDAP_CLKEN) tPDSD t PDHD DATA DAI_P20–1 (PDAP_STROBE) tPDSTRB tPDHLDD Figure 24. Parallel Data Acquisition Port (PDAP) Rev. 0 | Page 33 of 44 | March 2006 ADSP-21261 SPI Protocol—Master Table 29. SPI Protocol—Master Parameter Timing Requirements tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid Min Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM Serial Clock High Period tSPICLM Serial Clock Low Period tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) FLAG3–0 OUT (SPI Device Select) Low to First SPICLK Edge tSDSCIM tHDSM Last SPICLK Edge to FLAG3–0 OUT High tSPITDM Sequential Transfer Delay Max 5 2 ns ns 8 × tCCLK 4 × tCCLK – 2 4 × tCCLK – 2 ns ns ns ns ns ns ns ns 3 10 4 × tCCLK – 2 4 × tCCLK – 1 4 × tCCLK – 1 FLAG3–0 (OUTPUT) tS D S C I M tS P I C H M t S P IC LM t S P IC LM tS P I C H M t S P IC LK M tHDSM tS P I T D M SPICLK (CP = 0) (OUTPUT) SPICLK (CP = 1) (OUTPUT) t HDSPIDM tDDSPIDM MOSI (OUTPUT) MSB LSB t S S P ID M CPHASE = 1 tSSPIDM MISO (INPUT) MSB VALID LSB VALID tDDSPIDM MOSI (OUTPUT) CPHASE = 0 tHSPIDM tHSPIDM tHDSPIDM MSB tSSPIDM MISO (INPUT) LSB t H S P ID M MSB VALID LSB VALID Figure 25. SPI Protocol—Master SPI Protocol—Slave See Table 30 and Figure 26. Rev. 0 | Page 34 of 44 | March 2006 Unit ADSP-21261 Table 30. SPI Protocol—Slave Parameter Timing Requirements tSPICLKS tSPICHS tSPICLS tSDSCO tHDS tSSPIDS tHSPIDS tSDPPW Min Serial Clock Cycle Serial Clock High Period Serial Clock Low Period SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0 Data Input Valid to SPICLK Edge (Data Input Setup Time) SPICLK Last Sampling Edge to Data Input Not Valid SPIDS Deassertion Pulse Width (CPHASE = 0) Switching Characteristics tDSOE SPIDS Assertion to Data Out Active tDSDHI SPIDS Deassertion to Data High Impedance tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) Max 4 × tCCLK 2 × tCCLK – 2 2 × tCCLK – 2 ns ns ns 2 × tCCLK + 1 2 × tCCLK + 1 2 × tCCLK 2 2 2 × tCCLK ns ns ns ns ns ns 0 0 5 5 7.5 2 × tCCLK – 2 5 × tCCLK + 2 SPIDS (INPUT) t S P IC H S tSPICLS tSPICL KS tHDS SPICLK (CP = 0) (INPUT) tSPICLS tSDSCO SPICLK (CP = 1) (INPUT) tDSDHI tDDSPIDS MISO (OUTPUT) tSDPPW tSPICHS tDDSPIDS tDSOE tHDSPIDS MSB LSB tHSPIDS tSSPIDS CPHASE = 1 MOSI (INPUT) tSSPIDS LSB VALID MSB VALID tDSOV MISO (OUTPUT) LSB MSB CPHASE = 0 MOSI (INPUT) tHDSPIDS tDDSPIDS tD S O E tHSPIDS tSSPIDS MSB VALID LSB VALID Figure 26. SPI Protocol—Slave Rev. 0 | Page 35 of 44 | March 2006 Unit tDSDHI ns ns ns ns ns ADSP-21261 JTAG Test Access Port and Emulation See Table 31 and Figure 27. Table 31. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High TDI, TMS Hold After TCK High tHTAP tSSYS System Inputs Setup Before TCK High1 tHSYS System Inputs Hold After TCK High1 tTRSTW TRST Pulse Width Min 20 5 6 7 8 4tCK Switching Characteristics tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low2 1 2 Max ns ns ns ns ns ns 7 10 System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, and FLAG3–0. System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, and ALE. tTCK TCK tSTAP tHTAP TMS TDI tDTDO TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 27. JTAG Test Access Port and Emulation Rev. 0 | Page 36 of 44 | March 2006 Unit ns ns ADSP-21261 OUTPUT DRIVE CURRENTS CAPACITIVE LOADING Figure 28 shows typical I-V characteristics for the output drivers of the ADSP-21261. The curves represent the current drive capability of the output drivers as a function of output voltage. Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 29). Figure 33 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 31, Figure 32, and Figure 33 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20%–80%, V = Min) vs. Load Capacitance. 40 V OH 3.3V, 25°C 20 12 10 3.11V, 70°C 3.47V, 0°C 0 –10 10 RISE AND FALL TIMES (ns) SOURCE (VDDEXT) CURRENT (mA) 30 3.3V, 25°C 3.11V, 70°C –20 V OL –30 3.47V, 0°C –40 0 0.5 1.0 1.5 2 2.5 SWEEP (V DDEXT ) VOLTAGE (V) 3.0 3.5 RISE y = 0.0904x + 1.9426 FALL 8 6 4 y = 0.0722x + 1.4042 2 Figure 28. ADSP-21261 Typical Drive 0 0 20 TEST CONDITIONS 40 60 80 100 120 Figure 31. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max) Timing is measured on signals when they cross the 1.5 V level as described in Figure 30. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. 12 RISE 10 50⍀ TO OUTPUT PIN 1.5V 30pF Figure 29. Equivalent Device Loading for AC Measurements (Includes All Fixtures) RISE AND FALL TIMES (ns) y = 0.0915x + 2.2207 FALL 8 6 y = 0.0728x +1.6336 4 2 0 0 20 40 60 80 LOAD CAPACITANCE (pF) Figure 32. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) 1.5V 120 LOAD CAPACITANCE (pF) The ac signal specifications (timing parameters) appear in Table 9 on Page 18 through Table 31 on Page 36. These include output disable time, output enable time, and capacitive loading. INPUT OR OUTPUT 100 1.5V Figure 30. Voltage Reference Levels for AC Measurements Rev. 0 | Page 37 of 44 | March 2006 ADSP-21261 Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. 7 OUTPUT DELAY OR HOLD (ns) 6 Table 32. Thermal Characteristics for 136-Ball BGA1 5 Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT 4 y = 0.0904x - 2.712 3 2 1 0 –1 –2 –3 –4 0 20 40 60 80 100 1 120 Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 31.0 27.3 26.0 6.99 0.16 0.30 0.35 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W The thermal characteristics values provided in this table are modeled values. Table 33. Thermal Characteristics for 144-Lead LQFP1 LOAD CAPACITANCE (pF) Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) ENVIRONMENTAL CONDITIONS The ADSP-21261 processor is rated for performance over the commercial temperature range, TAMB = 0°C to 70°C. THERMAL CHARACTERISTICS Table 32 and Table 33 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. The junction-tocase measurement complies with MIL-STD-883. All measurements use a 2S2P JEDEC test board. 1 Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 32.5 28.9 27.8 7.8 0.5 0.8 1.0 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W The thermal characteristics values provided in this table are modeled values. To determine the junction temperature of the device while on the application PCB, use: T J = T CASE + ( Ψ JT × PD ) where: TJ = junction temperature (°C) TCASE = case temperature (°C) measured at the top center of the package ΨJT = junction-to-top (of package) characterization parameter = typical value from the tables below PD = power dissipation. See EE Note No. EE-216 Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approximation of TJ by the equation: T J = T A + ( θ JA × PD ) where: TA = ambient temperature (°C) Rev. 0 | Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Page 38 of 44 | March 2006 ADSP-21261 136-BALL BGA PIN CONFIGURATIONS Table 34 shows the ADSP-21261’s pin names and their default function after reset (in parentheses). Figure 34 on Page 41 shows the BGA package pin assignments. Table 34. 136-Ball BGA Pin Assignments Pin Name CLKCFG0 XTAL TMS TCK TDI CLKOUT TDO EMU MOSI MISO SPIDS VDDINT GND GND VDDINT GND GND GND GND GND GND GND GND FLAG3 Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 E01 E02 E04 E05 E06 E09 E10 E11 E13 E14 Pin Name CLKCFG1 GND VDDEXT CLKIN TRST AVSS AVDD VDDEXT SPICLK RESET VDDINT GND GND GND FLAG1 FLAG0 GND GND GND GND GND GND FLAG2 DAI_P20 (SFS45) Ball No. B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 F01 F02 F04 F05 F06 F09 F10 F11 F13 F14 Rev. 0 | Pin Name BOOTCFG1 BOOTCFG0 GND GND GND VDDINT Ball No. C01 C02 C03 C12 C13 C14 Pin Name VDDINT GND GND GND GND GND GND GND GND VDDINT Ball No. D01 D02 D04 D05 D06 D09 D10 D11 D13 D14 AD7 VDDINT VDDEXT DAI_P19 (SCLK45) G01 G02 G13 G14 AD6 VDDEXT DAI_P18 (SD5B) DAI_P17 (SD5A) H01 H02 H13 H14 Page 39 of 44 | March 2006 ADSP-21261 Table 34. 136-Ball BGA Pin Assignments (Continued) Pin Name AD5 AD4 GND GND GND GND GND GND VDDINT DAI_P16 (SD4B) AD15 ALE RD VDDINT VDDEXT AD8 VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT GND DAI_P10 (SD2B) Ball No. J01 J02 J04 J05 J06 J09 J10 J11 J13 J14 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 Pin Name AD3 VDDINT GND GND GND GND GND GND GND DAI_P15 (SD4A) AD14 AD13 AD12 AD11 AD10 AD9 DAI_P1 (SD0A) DAI_P3 (SCLK0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) DAI_P8 (SFS1) DAI_P9 (SD2A) DAI_P11 (SD3A) Ball No. K01 K02 K04 K05 K06 K09 K10 K11 K13 K14 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Rev. 0 | Pin Name AD2 AD1 GND GND GND GND GND GND GND DAI_P14 (SFS23) Page 40 of 44 | March 2006 Ball No. L01 L02 L04 L05 L06 L09 L10 L11 L13 L14 Pin Name AD0 WR GND GND DAI_P12 (SD3B) DAI_P13 (SCLK23) Ball No. M01 M02 M03 M12 M13 M14 ADSP-21261 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P KEY VDDINT GND AVDD VDDEXT AVSS I/O SIGNALS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary) Rev. 0 | Page 41 of 44 | March 2006 ADSP-21261 144-LEAD LQFP PIN CONFIGURATIONS Table 35 shows the ADSP-21261’s pin names and their default function after reset (in parentheses). Table 35. 144-Lead LQFP Pin Assignments Pin Name VDDINT CLKCFG0 CLKCFG1 BOOTCFG0 BOOTCFG1 GND VDDEXT GND VDDINT GND VDDINT GND VDDINT GND FLAG0 FLAG1 AD7 GND VDDINT GND VDDEXT GND VDDINT AD6 AD5 AD4 VDDINT GND AD3 AD2 VDDEXT GND AD1 AD0 WR VDDINT LQFP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name VDDINT GND RD ALE AD15 AD14 AD13 GND VDDEXT AD12 VDDINT GND AD11 AD10 AD9 AD8 DAI_P1 (SD0A) VDDINT GND DAI_P2 (SD0B) DAI_P3 (SCLK0) GND VDDEXT VDDINT GND DAI_P4 (SFS0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) VDDINT GND VDDINT GND DAI_P8 (SFS1) DAI_P9 (SD2A) VDDINT LQFP Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name VDDEXT GND VDDINT GND DAI_P10 (SD2B) DAI_P11 (SD3A) DAI_P12 (SD3B) DAI_P13 (SCLK23) DAI_P14 (SFS23) DAI_P15 (SD4A) VDDINT GND GND DAI_P16 (SD4B) DAI_P17 (SD5A) DAI_P18 (SD5B) DAI_P19 (SCLK45) VDDINT GND GND VDDEXT DAI_P20 (SFS45) GND VDDINT FLAG2 FLAG3 VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT VDDINT Rev. 0 | Page 42 of 44 | March 2006 LQFP Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name GND VDDINT GND VDDINT GND VDDINT GND VDDEXT GND VDDINT GND VDDINT RESET SPIDS GND VDDINT SPICLK MISO MOSI GND VDDINT VDDEXT AVDD AVSS GND CLKOUT EMU TDO TDI TRST TCK TMS GND CLKIN XTAL VDDEXT LQFP Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 ADSP-21261 PACKAGE DIMENSIONS The ADSP-21261 is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 35 and Figure 36. 10.40 BSC SQ 12.00 BSC SQ 0.80 BSC TYP PIN A1 INDICATOR 0.80 BSC TYP 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TOP VIEW 1.70 MAX A B C D E F G H J K L M N P DETAIL A BOTTOM VIEW 1. DIMENSIONS ARE IN MILIMETERS (MM). 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.15 MM OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR THE BALL DIAMETER. 4. CENTER DIMENSIONS ARE NOMINAL. 0.25 MIN SEATING PLANE 0.50 0.45 0.40 (BALL DIAMETER) 0.12 MAX (BALL COPLANARITY) DETAIL A Figure 35. 136-Ball Mini-BGA [CSP_BGA] (BC-136-3) 22.00 BSC SQ 20.00 BSC SQ 109 144 108 1 PIN 1 INDICATOR 0.50 BSC TYP (LEAD PITCH) 0.27 0.22 TYP 0.17 SEATING PLANE 0.08 MAX (LEAD COPLANARITY) 1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB. 0.15 0.05 0.75 0.60 TYP 0.45 1.45 1.40 1.35 1.60 MAX 73 36 72 37 DETAIL A DETAIL A TOP VIEW (PINS DOWN) Figure 36. 144-Lead LQFP (ST-144-2) Rev. 0 | Page 43 of 44 | March 2006 2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL. ADSP-21261 SURFACE MOUNT DESIGN Table 36 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 36. BGA Data for Use with Surface Mount Design Ball Attach Package Type 136-Ball Mini-BGA Solder Mask (BC-136-3) Defined Solder Mask Opening 0.40 mm diameter Ball Pad Size 0.53 mm diameter ORDERING GUIDE 1 2 Model ADSP-21261SKBC-150 Temperature Range1 0°C to +70°C Instruction Rate 150 MHz On-Chip SRAM 1M bit ADSP-21261SKBCZ1502 0°C to +70°C 150 MHz 1M bit ADSP-21261SKSTZ1502 0°C to +70°C 150 MHz 1M bit Operating ROM Voltage 3M bit 1.2 V Internal 3.3 V External 3M bit 1.2 V Internal 3.3 V External 3M bit 1.2 V Internal 3.3 V External Ranges shown represent ambient temperature. Z = Pb-free part. © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04932-0-3/06(0) Rev. 0 | Page 44 of 44 | March 2006 Package Description 136-Ball BGA Package Option BC-136-3 136-Ball BGA BC-136-3 144-Lead LQFP ST-144-2