ETC CS1087/D

CS1087
Vacuum Fluorescent
Display Tube Driver
The VFD Driver is a microprocessor interface IC that drives a
multiplexed VF (Vacuum Fluorescent) display tube. It consists of a
32–bit shift register, a 32–bit transparent data latch, a metal mask
ROM, six 20 mA anode output drivers, twenty–three 2 mA anode
output drivers, and three 50 mA grid drivers with output enables. The
metal mask programmable ROM (at factory request) allows the 29
anode outputs and 3 grid outputs to be assigned to any of the 32 serial
data bits.
1
PLCC–44
FN SUFFIX
CASE 777
Chip Select
ORDERING INFORMATION
Clock
12 V
Regulator
DIP–40
WIDE BODY
N SUFFIX
CASE 711
40
Features
Metal Mask ROM
Six 20 mA Anode drivers
Twenty–three, 2 mA Anode drivers
Three, 50 mA Grid drivers
Power On Reset
Display Dimming Possible
•
•
•
•
•
•
VIGN
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Device
CS1087XN40
Data Out
SPI Functions
5V
CS1087XFN44
GND
CS1087XFNR44
Anodes
1:29
0.1 µF
VBAT
µP
PORT
PORT
PORT
GND PORT
Shipping
DIP–40
WIDE BODY
9 Units/Rail
PLCC–44
PLCC–44
23 Units/Rail
500 Tape & Reel
VBB
CS1087
VCC
Package
FILAMENT
VFD
DEVICE MARKING INFORMATION
GRID1GRID2 GRID3 GND
DOUT
DIN GRID1
CLK GRID2
STB GRID3
GREN
GND
See general marking information in the device marking
section on page 7 of this data sheet.
Figure 1. Application Diagram
 Semiconductor Components Industries, LLC, 2001
February, 2001 – Rev. 10
1
Publication Order Number:
CS1087/D
CS1087
ABSOLUTE MAXIMUM RATINGS*
Parameter
Value
Unit
Supply Voltage (VBB)
–0.6 to +18
V
Input Voltages (DIN, CLK, STB, GREN)
–0.6 to +6.0
V
Junction Temperature Range
–40 to +150
°C
Storage Temperature Range
–55 to +150
°C
ESD Susceptibility (Human Body Model)
2.0
kV
ESD Susceptibility (Machine Model)
200
V
260 Peak
230 Peak
°C
Lead Temperature Soldering:
Wave Solder (through hole styles only) Note 1.
Reflow (SMD styles only) Note 2.
1. 10 second maximum.
2. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (8.0 V ≤ VBB ≤ 16.5 V, Gnd = 0 V, –40°C ≤ TJ ≤ 105°C; unless otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
–
8.0
–
16.5
V
VBB Input
VBB Input Voltage
IBB0 Current
No outputs active, VBB = 16.5 V
–
2.0
5.0
mA
Reset Mode
All outputs forced low.
–
6.5
7.5
V
DIN, CLK, STB Inputs
VIL1, Input Low Voltage
–
–
–
1.6
V
VIH, Input High Voltage
–
3.3
–
–
V
–
7.5
20.0
µA
IIL, Input Current
VIN = VIH
GREN Input
VIL, Input Low Voltage
–
–
–
1.6
V
VIH, Input High Voltage
–
3.3
–
–
V
VIN = 3.325 V
–
30
60
µA
IOL
Sink Current
1.0
–
–
mA
IOH
Source Current
50
–
–
mA
VOL
IOUT = 1.0 mA
–
–
0.5
V
VOH
IOUT = –50 mA, VBB = 12 V
VBB – 0.75
–
VBB
V
IIH, Input Pull–down Current
GRID1, GRID2, GRID3 Outputs
AN24 – AN29 Outputs
IOL
Sink Current
400
–
–
µA
IOH
Source Current
20
–
–
mA
VOL
IOUT = 400 µA
–
–
0.5
V
VOH
IOUT = –20 mA, VBB = 12 V
VBB – 0.5
–
VBB
V
AN1 – AN23 Outputs
IOL
Sink Current
100
–
–
µA
IOH
Source Current
2.0
–
–
mA
VOL
IOUT = 100 µA
–
–
0.5
V
VOH
IOUT = –2.0 mA, VBB = 12 V
VBB – 0.5
–
VBB
V
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CS1087
ELECTRICAL CHARACTERISTICS (continued) (8.0 V ≤ VBB ≤ 16.5 V, Gnd = 0 V, –40°C ≤ TJ ≤ 105°C; unless otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
DOUT Output
IOL
Sink Current
1.0
–
–
mA
IOH
Source Current
1.0
–
–
mA
VOL
IOUT = 1.0 mA
–
–
0.5
V
VOH
IOUT = –1.0 mA
3.9
–
5.1
V
AC Characteristics: Input and Output Timing
FC, CLK Frequency
–
0
–
1.0
MHz
TCL, CLK Low Time
–
200
–
–
ns
TCH, CLK High Time
–
200
–
–
ns
TCR, CLK Rise Time
–
–
–
100
ns
TCF, CLK Fall Time
–
–
–
100
ns
TCD, CLK Low to DOUT
Propagation Delay
–
–
–
200
ns
TSC, STB Low to CLK High Time
–
50
–
–
ns
TST, STB High Time
–
500
–
–
ns
TAN, STB High to Anode Output
Propagation Delay
–
–
–
5.0
µs
TGL, Grid Turn On Propagation Delay
VBB = 12 V
–
–
2.0
µs
TG0, Grid Turn Off Propagation Delay
VBB = 12 V
–
–
5.0
µs
TGR, Grid Rise Time
At rated load. Note 3.
0.50
–
2.00
µs
TGF, Grid Fall Time
At rated load. Note 3.
0.35
–
2.00
µs
TAR, Anode Rise Time
At rated load. Note 3.
0.40
–
2.00
µs
TAF, Anode Fall Time
At rated load. Note 3.
0.40
–
2.50
µs
3. Grid and anode rise / fall times are measured from 10% and 90% points. Output currents
are at the maximum rated currents for the respective stages.
PACKAGE LEAD DESCRIPTION
Package Lead Number
Lead Symbol
40L DIP
44L PLCC
(29 Anode Configuration)
1
14
GRID1
50 mA grid output.
2
15
GRID2
50 mA grid output.
3
16
GRID3
50 mA grid output.
4
17
AN1
2.0 mA anode output.
5
18
AN2
2.0 mA anode output.
6
19
AN3
2.0 mA anode output.
7
20
AN4
2.0 mA anode output.
8
21
AN5
2.0 mA anode output.
9
22
AN6
2.0 mA anode output.
10
24
AN7
2.0 mA anode output.
11
25
AN8
2.0 mA anode output.
12
26
AN9
2.0 mA anode output.
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Function
CS1087
PACKAGE LEAD DESCRIPTION (continued)
Package Lead Number
Lead Symbol
40L DIP
44L PLCC
(29 Anode Configuration)
13
27
AN10
2.0 mA anode output.
14
28
AN11
2.0 mA anode output.
15
29
AN12
2.0 mA anode output.
16
30
AN13
2.0 mA anode output.
17
31
AN14
2.0 mA anode output.
18
32
AN15
2.0 mA anode output.
19
33
AN16
2.0 mA anode output.
20
35
GND
Ground connection.
21
36
AN17
2.0 mA anode output.
22
37
AN18
2.0 mA anode output.
23
38
AN19
2.0 mA anode output.
24
39
AN20
2.0 mA anode output.
25
40
AN21
2.0 mA anode output.
26
41
AN22
2.0 mA anode output.
27
42
AN23
2.0 mA anode output.
28
43
AN24
20 mA anode output.
29
44
AN25
20 mA anode output.
30
2
AN26
20 mA anode output.
31
3
AN27
20 mA anode output.
32
4
AN28
20 mA anode output.
33
5
AN29
20 mA anode output.
34
6
DOUT
Shift register data output.
35
7
DIN
Shift register data input.
36
8
CLK
Shift register clock input.
37
9
STB
Transfer contents of shift registers to output stages.
38
10
GREN
39
1, 11, 12, 23, 34
NC
No connection.
40
13
VBB
Supply voltage input.
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4
Function
Grid outputs enable.
CS1087
GRID1 GRID2 GRID3
AN1
AN2
AN3
AN23
AN24
AN25
AN26
AN27
AN28
AN29
VBB
VREG
POR
VREG
GND
VREG
GREN
METAL MASK ROM
VREG
STB
VREG
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
DIN
VREG
VREG
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
R
R
R
R
R
R
R
R
R
R
R
R
R
R
CLK
Output Drive Capability
Grid Outputs: 5 mA
AN24 – AN29: 20 mA
AN1 – AN23: 2.0 mA
Figure 2. Block Diagram
OPERATION DESCRIPTION
The three GRID outputs are gated by the GREN input.
When GREN is low, the GRID outputs are forced low
regardless of the state of the corresponding latch output.
When GREN is high, the GRID outputs correspond to the
state of their respective latch outputs. The anode outputs,
AN1 to AN29 are always enabled.
The DOUT pin is the output of the last stage of the shift
register to allow serial cascading of this IC with other
devices. Data from the last stage of the shift register is
supplied to the DOUT pin delayed by 1/2 CLK cycle. Data on
the DOUT output changes with the falling edges of the CLK
to prevent logic race conditions between the CLK and the
DIN of the next IC in the serial chain.
Upon the initial application of power, the power on reset
function will cause all of the anode and grid driver outputs
to be off and all shift register outputs to be set low. Data is
fed into the shift register through the DIN pin at the rising
edge of the CLK input. Thirty two bits of data are capable of
being stored by the shift register. Once the desired pattern is
stored in the shift register, it can be transferred to the latch
by setting the STB input high. The output of each latch
drives its corresponding output stage. A logic high input to
the shift register/latch will cause the corresponding output
to turn on. A logic low input to the shift register/latch will
cause the corresponding output to turn off. Please note that
if the STB is held high, the outputs of the latch reflect the
outputs of the corresponding shift register bits and will
change if data is shifted in.
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DOUT
CS1087
APPLICATION INFORMATION
Bit #
Pin Name
Bit #
Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
G1
G2
G3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
31
32
Table 3: Bit Pattern, G = Grid, A = Anode.
1
2
3
4
5
6
7
8
9
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 30 BIT 31 BIT 32 BIT 1
BIT 2
BIT 3
PREV
BIT 1
PREV
BIT 2
PREV
BIT 3
PREV
BIT 4
PREV
BIT 5
PREV
BIT 6
PREV
BIT 7
PREV
BIT 8
PREV
BIT 9
PREV
BIT 30
PREV
BIT 2
PREV
BIT 3
30
1
2
3
CLKIN
DIN
DOUT
PREV
BIT 31
PREV
BIT 32
PREV
BIT 1
STB
ANODES
GREN
GRIDS *
* Selected grid goes high only if input bit pattern from shift register to grid is high.
Figure 4. Typical Operation
load. VOH = 5.7 V (max) with no load. Protection or
workarounds for the device may be needed at the application
level. No protection is needed when interfacing with other
parts in this family (CS1087, CS1088, or CS1089).
Care must be taken when interfacing this part to a
microprocessor. The DOUT output VOH is specified at 3.9 V
to 5.1 V at an IOUT of –1.0 mA. Lower current loads will
result in a higher output voltage. VOH = 5.2 V (typ) with no
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CS1087
PIN CONNECTIONS
VBB
NC
GREN
STB
CLK
DIN
DOUT
AN29
AN28
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
AN19
AN18
AN17
MARKING DIAGRAMS
40
DIP–40
WIDE BODY
N SUFFIX
CASE 711
CS1087
AWLYYWW
1
AN20
AN19
AN18
AN17
GND
NC
AN16
AN15
AN14
AN13
AN12
1
GRID1
GRID2
GRID3
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
GND
40
39 38 37 36 35 34 33 32 31 30 29
1
PLCC–44
FN SUFFIX
CASE 777
40
41
42
43
44
1
2
3
4
5
6
28
27
26
25
24
23
22
21
20
19
18
7 8 9 10 11 12 13 14 15 16 17
DIN
CLK
STB
GREN
NC
NC
VBB
GRID1
GRID2
GRID3
AN1
CS1087
AWLYYWW
AN21
AN22
AN23
AN24
AN25
NC
AN26
AN27
AN28
AN29
DOUT
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
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7
AN11
AN10
AN9
AN8
AN7
NC
AN6
AN5
AN4
AN3
AN2
CS1087
PACKAGE DIMENSIONS
DIP–40
WIDE BODY
N SUFFIX
CASE 711–03
ISSUE C
40
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
21
B
1
20
L
A
C
N
J
H
G
F
D
K
M
SEATING
PLANE
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8
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
51.69
52.45
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0
15
0.51
1.02
INCHES
MIN
MAX
2.035
2.065
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0
15
0.020
0.040
CS1087
PACKAGE DIMENSIONS
PLCC–44
FN SUFFIX
CASE 777–02
ISSUE C
SCALE 1:1
–N–
Y
BRK
0.007(0.180)
B
D
M
T
0.007(0.180)
U
L-M
M
N
S
L-M
S
S
T
N
S
Z
–M–
–L–
V
44
W
1
G1
0.010 (0.25)
X
D
VIEW D–D
A
0.007(0.180)
M
T
L-M
S
N
S
R
0.007(0.180)
M
T
L-M
S
N
S
0.007(0.180)
H
S
M
T
T
L-M
S
L-M
S
N
S
Z
J
C
K1
E
0.004 (0.10)
–T– SEATING
G
G1
0.010 (0.25)
T
S
K
PLANE
L-M
S
N
S
F
VIEW S
0.007(0.180)
M
T
L-M
S
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.650
0.656
0.650
0.656
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2
10 0.610
0.630
0.040
---
MILLIMETERS
MIN
MAX
17.40
17.65
17.40
17.65
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--16.51
16.66
16.51
16.66
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2
10
15.50
16.00
1.02
---
PACKAGE THERMAL DATA
DIP–40 WIDE BODY
PLCC–44
Unit
RΘJC
Typical
20
16
°C/W
RΘJA
Typical
45
55
°C/W
Parameter
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N
N
S
S
CS1087
Notes
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CS1087
Notes
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CS1087
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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CS1087/D