1 CY62136BV18 MoBL2™ 128K x 16 Static RAM Features • Low voltage range: — CY62136BV18: 1.75V−1.95V • Ultra-low active, standby power • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • CMOS for optimum speed/power Functional Description The CY62136BV18 is a high-performance CMOS static RAM organized as 131,072 words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. The CY62136BV18 is available in 48-ball FBGA packaging. Logic Block Diagram A3 A2 A1 A0 SENSE AMPS A8 A7 A6 A5 A4 ROW DECODER DATA IN DRIVERS 128K x 16 RAM Array 1024 X 2048 I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A10 A11 A12 A13 A14 A15 A16 BHE WE CE OE BLE MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 10, 2000 CY62136BV18 MoBL2™ Pin Configuration FBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H DC Voltage Applied to Outputs in High Z State[1] ....................................... −0.5V to VCC + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage[1] .................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Storage Temperature ..................................... −65°C to +150°C Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied .................................................. −55°C to +125°C Latch-Up Current.................................................... >200 mA Supply Voltage to Ground Potential..................−0.5V to +2.4V Operating Range Device Range CY62136BV18 Industrial Ambient Temperature VCC −40°C to +85°C 1.75V to 1.95V Product Portfolio Power Dissipation (Industrial) VCC Range Product CY62136BV18 VCC(min) 1.75V VCC(typ) 1.80V [2] Operating (ICC) VCC(max) Power 1.95V LL Typ. [2] 3 mA Max. 7 mA Standby (ISB2) Typ. [2] 1 µA Notes: 1. VIL(min.) = −2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25°C. 2 Max 15 µA CY62136BV18 MoBL2™ Electrical Characteristics Over the Operating Range CY62136BV18 Parameter Description Test Conditions Min. VOH Output HIGH Voltage IOH = −0.1 mA VCC = 1.75V VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.75V VIH Input HIGH Voltage VCC = 1.95V VIL Input LOW Voltage VCC = 1.75V IIX Input Load Current GND < VI < VCC −1 IOZ Output Leakage Current GND < VO < VCC, Output Disabled −1 ICC VCC Operating Supply Current IOUT = 0 mA, f = fMAX = 1/tRC, CMOS levels CE > VCC−0.3V, VIN > VCC−0.3V or VIN < 0.3V, f = fMAX (Address and Data Only), f=0 (OE, WE, BHE, and BLE) ISB2 Automatic CE Power-Down Current— CMOS Inputs CE > VCC−0.3V VIN > VCC−0.3V or VIN < 0.3V, f = 0 VCC = 1.95V Unit V 0.2 V 1.4 VCC + 0.3V V −0.5 0.4 V +1 +1 µA +1 +1 µA 3 7 mA 1 2 mA 100 µA 15 µA IOUT = 0 mA, f = 1 MHz, CMOS Levels Automatic CE Power-Down Current— CMOS Inputs Max. 1.5 VCC = 1.95V ISB1 Typ.[2] LL 1 Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC= VCC(typ) Thermal Resistance Description Test Conditions Symbol BGA Units Thermal Resistance (Junction to Ambient)[3] Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA 55 °C/W ΘJC 16 °C/W Thermal Resistance (Junction to Case)[3] Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 CY62136BV18 MoBL2™ AC Test Loads and Waveforms R1 ALL INPUT PULSES R1 VCC VCC Typ VCC OUTPUT 10% OUTPUT 90% 10% 90% GND R2 30 pF INCLUDING JIG AND SCOPE Fall Time: 1 V/ns Rise Time: 1 V/ns INCLUDING JIG AND SCOPE (b) (a) Equivalent to: R2 5 pF (c) THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 1.8V Unit R1 15294 Ohms R2 11300 Ohms RTH 6500 Ohms VTH 0.85 Volts Data Retention Characteristics (Over the Operating Range) Parameter Conditions[5] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[4] Operation Recovery Time Min. Typ.[2] 1.0 VCC = 1.0V CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V No input may exceed VCC+0.3V LL 1 Max. Unit 1.95 V 7.5 µA 0 ns 100 µs Data Retention Waveform DATA RETENTION MODE VCC VCC(min.) VDR > 1.0 V VCC(min.) tR tCDR CE Notes: 4. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC typ., and output loading of the specified IOL/IOH and 30 pF load capacitance. 4 CY62136BV18 MoBL2™ Switching Characteristics Over the Operating Range[5] 70 ns Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns tLZOE 70 OE LOW to Low Z 70 10 [6] OE HIGH to High Z tLZCE CE LOW to Low Z[6] ns 25 10 Z[6, 7] ns ns 5 [6, 7] tHZOE ns ns ns tHZCE CE HIGH to High tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 70 ns tDBE BLE / BHE LOW to Data Valid 35 ns tLZBE BLE / BHE LOW to Low tHZBE 25 0 Z[6, 7] BLE / BHE HIGH to High ns 5 Z[8] ns ns 25 ns [8, 9] WRITE CYCLE tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 50 ns tBW BLE / BHE LOW to Write End 60 ns tSD Data Set-Up to Write End 30 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High Z[6, 7] WE HIGH to Low Z[6] 25 10 ns ns Switching Waveforms Read Cycle No. 1 [10, 11] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Notes: 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 5 CY62136BV18 MoBL2™ Switching Waveforms (continued) Read Cycle No. 2 [11, 12] tR C CE t PD t HZCE t A CE OE t HZOE t D OE B H E/B LE t LZO E t H ZB E t DB E t LZBE D A TA O U T H IG H IM P E D A N C E H IG H IM P E D A N C E D A TA V A LID t LZCE V CC SU P P LY CURRENT tP U IC C 50% 50% IS B [8, 13, 14] Write Cycle No. 1 (WE Controlled) tWC ADDRESS CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O NOTE 15 DATAIN VALID tHZOE Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied. 6 tHD CY62136BV18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [8, 13, 14] tWC ADDRESS tSCE CE tSA tAW tHA tBW BHE/BLE tPWE WE tSD DATA I/O tHD DATAIN VALID Write Cycle No. 3 (WE Controlled, OE LOW) [9, 14] tWC ADDRESS CE tAW tBW BHE/BLE WE tHA tSA tSD DATA I/O tHD DATAIN VALID NOTE 15 tLZWE tHZWE 7 CY62136BV18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [15] tWC ADDRESS CE tAW tHA tBW BHE/BLE tSA WE tSD DATA I/O tHD DATAIN VALID NOTE 15 tLZWE tHZWE 8 CY62136BV18 MoBL2™ Typical DC and AC Characteristics 1.4 Norm alized Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 35 MoBL2 30 1.2 MoBL2 25 ISB (µA) 1.0 ICC 0.8 0.6 20 15 10 0.4 5 0.2 0.0 1.65 0 1.8 1.95 2.2 SUPPLY VOLTAGE (V) 2.2 1.8 1.95 SUPPLY VOLTAGE (V) 2.4 Access Time vs. Supply Voltage 80 70 MoBL2 60 TAA (ns) 50 40 30 20 10 1.65 2.2 1.95 1.8 SUPPLY VOLTAGE (V) Truth Table CE WE OE BHE BLE Inputs/Outputs H X X X X High Z Deselect/Power-Down Standby (ISB) L H L L L Data Out (I/OO–I/O15) Read Active (ICC) L H L H L Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Deselect/Output Disabled Active (ICC) L H H H L High Z Deselect/Output Disabled Active (ICC) L H H L H High Z Deselect/Output Disabled Active (ICC) L L X L L Data In (I/OO–I/O15) Write Active (ICC) L L X H L Data In (I/OO–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8–I/O15); I/O0 –I/O7 in High Z Write Active (ICC) 9 Mode Power CY62136BV18 MoBL2™ Ordering Information Speed (ns) Ordering Code Package Name 70 CY62136BV18LL-70BAI BA48 Operating Range Package Type 48-Ball Fine Pitch BGA Industrial Document #: 38-01050-** Package Diagrams 48-Ball (7.00 mm x 7.00 mm x 1.10 mm) Fine Pitch BGA BA48 51-85096-A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.