CY62137V MoBL™ CY62137V18 MoBL2™ 128K x 16 Static RAM Features are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). • Low voltage range: — CY62137V18: 1.65V–1.95V — CY62137V: 2.7V-3.6V • Ultra-low active, standby power • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • CMOS for optimum speed/power Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 through I/O15) is written into the location specified on the address pins (A0 through A16). Functional Description The CY62137V and CY62137V18 are high-performance CMOS static RAMs organized as 131,072 words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH) or when CE is LOW and both BLE and BHE are HIGH. The input/output pins (I/O0 through I/O 15) Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The CY62137V and CY62137V18 are available in 48-ball FBGA and standard 44-pin TSOP Type II (forward pinout) packaging. Logic Block Diagram Pin Configurations TSOP II (Forward) Top View SENSE AMPS A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 128K x 16 RAM Array A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A10 A11 A12 A13 A14 A15 A16 BHE WE CE OE BLE 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 62137V–2 CE Power Down Circuit BHE BLE A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 62137V–1 MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 January 20, 2000 CY62137V MoBL™ CY62137V18 MoBL2™ Pin Configuration 48-Ball FBGA 1 2 3 Top View 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H 62137V–3 DC Voltage Applied to Outputs in High Z State ................................... –0.5V to VCC + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage ................................ –0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied .................................................. −55°C to +125°C Latch-Up Current .................................................... >200 mA Supply Voltage to Ground Potential ............... –0.5V to +4.6V Operating Range Device Range Ambient Temperature VCC CY62137V18 Industrial –40°C to +85°C 1.65V to 1.95V CY62137V Industrial –40°C to +85°C 2.7V to 3.6V Product Portfolio Power Dissipation (Industrial) VCC Range Product VCC(min) VCC(typ)  Operating (ICC)  VCC(max) Speed Typ. Max. CY62137V 2.7V 3.0V 3.6V 70 ns 7 mA 15 mA CY62137V18 1.65V 1.80V 1.95V 70 ns 3 mA 7 mA Typ.  Standby (ISB2) Max 1 µA Shaded areas contain preliminary information. Notes: 1. VIL (min) = –2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C. 2 15 µA 15 µA CY62137V MoBL™ CY62137V18 MoBL2™ Electrical Characteristics Over the Operating Range CY62137V Parameter Description Test Conditions Min. Typ. Max. Unit VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V IIX Input Load Current GND < VI < VCC –1 +1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 +1 µA ICC VCC Operating Supply Current IOUT = 0 mA, f = fMAX = 1/tRC, CMOS Levels 7 15 mA 1 2 mA 100 µA 15 µA Max. Unit VCC = 3.6V 2.2 VCC = 2.7V –0.5 VCC = 3.6V IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = fMAX VCC = 3.6V ISB2 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f = 0 VCC = 3.6V LL V 0.4 V VCC + 0.5V V 1 9 CY62137V18 Parameter Description Test Conditions Min. Typ. VOH Output HIGH Voltage IOH = –0.1 mA VCC = 1.65V 1.5 VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V VIH Input HIGH Voltage VIL Input LOW Voltage 0.4 V IIX Input Load Current GND < VI < VCC –1 +1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 +1 µA ICC VCC Operating Supply Current IOUT = 0 mA, f = fMAX = 1/tRC, CMOS Levels 3 7 mA 1 2 mA 100 µA 15 µA VCC = 1.95V 1.4 VCC = 1.65V –0.5 VCC = 1.95V IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = fMAX VCC = 1.95V ISB2 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f = 0 VCC = 1.95V LL V 1 0.2 V VCC + 0.3V V Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 Max. Unit 6 pF 8 pF CY62137V MoBL™ CY62137V18 MoBL2™ AC Test Loads and Waveforms R1 R1 VCC ALL INPUT PULSES VCC OUTPUT VCC Typ OUTPUT INCLUDING JIG AND SCOPE Equivalent to: R2 5 pF R2 30 pF 10% GND < 5 ns < 5 ns INCLUDING JIG AND SCOPE (a) 90% 10% 90% (b) C62137V–5 C62137V–4 THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 3.0V 1.8V Unit R1 1105 15294 Ohms R2 1550 11300 Ohms RTH 645 6500 Ohms VTH 1.75V 0.85V Volts Shaded areas contain preliminary information. Data Retention Characteristics (Over the Operating Range) Parameter Conditions Description Typ. Max. Unit VDR VCC for Data Retention (CY62137V18) 1.0 1.95 V VDR VCC for Data Retention (CY62137V) 1.0 3.6 V ICCDR Data Retention Current 1 µA tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time VCC = 1.0V CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V No input may exceed VCC+0.3V Min. LL 0.1 0 ns 100 µs Data Retention Waveform DATA RETENTION MODE VCC VCC(min.) VDR > 1.0 V VCC(min.) tR tCDR CE C62137V–6 Note: 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to VCC typ., and output loading of the specified IOL/IOH and 30-pF load capacitance. 4 CY62137V MoBL™ CY62137V18 MoBL2™ Switching Characteristics Over the Operating Range 70 ns Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE 70 OE HIGH to High Z tLZCE CE LOW to Low Z ns 70 10 ns 70 ns 35 ns 5 [5, 6] ns 25  10 [5, 6] ns ns ns tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 70 ns tDBE BHE / BLE LOW to Data Valid 70 ns tLZBE BHE / BLE LOW to Low Z tHZBE BHE / BLE HIGH to High Z WRITE CYCLE 25 0 ns ns 10 ns 25 ns [7, 8] tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 50 ns tSD Data Set-Up to Write End 30 ns tHD Data Hold from Write End 0 ns tHZWE [5, 6] WE LOW to High Z 50  ns tLZWE WE HIGH to Low Z 10 ns tBW BHE / BLE LOW to End of Write 60 ns Shaded areas contain preliminary information. Notes: 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. t HZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 8. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 5 CY62137V MoBL™ CY62137V18 MoBL2™ Switching Waveforms Read Cycle No. 1 [9, 10] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID C62137V–7 Read Cycle No. 2 [10, 11] tRC CE tPD tHZCE tACE OE tHZOE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB C62137V–8 Notes: 9. Device is continuously selected. OE, CE=VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 6 CY62137V MoBL™ CY62137V18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [7, 12, 13] tWC ADDRESS CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 14 tHZOE Write Cycle No. 2 (CE Controlled) C62137V–9 [7, 12, 13] tWC ADDRESS tSCE CE tSA tAW BHE/BLE WE tHA tBW tPWE tSD DATA I/O tHD DATAIN VALID C62137V–10 Notes: 12. Data I/O is high-impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 14. During this period, the I/Os are in output state and input signals should not be applied. 7 CY62137V MoBL™ CY62137V18 MoBL2™ Switching Waveforms (continued) [8, 13] Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tAW tBW BHE/BLE WE tHA tSA tSD DATA I/O tHD DATAIN VALID NOTE 14 tLZWE tHZWE C62137V–11 8 CY62137V MoBL™ CY62137V18 MoBL2™ Typical DC and AC Characteristics STANDBY CURRENT vs. AMBIENT TEMPERATURE 1.4 3.0 1.2 2.5 1.0 0.8 0.6 VIN =VCC typ. TA =25°C 0.4 VCC =VCC typ. VIN =VCC typ. 2.0 I CC ISB2 mA NORMALIZED ICC , NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.0 0.5 0.2 0.0 0.0 1.7 2.2 2.7 3.2 -0.5 -55 3.7 NORMALIZED STANDBY CURRENT vs. SUPPLY VOLTAGE NORMALIZED I CC vs. CYCLE TIME NORMALIZED ICC 1.2 ISB2 1.0 0.8 VIN =VCC typ. TA =25°C 0.4 105 1.50 1.4 0.6 25 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) NORMALIZED ISB ISB 1.5 VCC =3.3V TA =25°C 1.00 0.50 0.2 0.0 1.0 0.10 3.7 2.8 1.9 5 1 15 10 CYCLE FREQUENCY (MHz) SUPPLY VOLTAGE (V) Truth Table CE WE OE BHE BLE Inputs/Outputs H X X X X High Z Deselect/Power-Down Standby (ISB) L X X H H High Z Deselect/Power-Down Standby (ISB) L H L L L Data Out (I/OO–I/O15) Read Active (ICC) L H L H L Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8–I/O 15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Deselect/Output Disabled Active (ICC) L H H H L High Z Deselect/Output Disabled Active (ICC) L H H L H High Z Deselect/Output Disabled Active (ICC) L L X L L Data In (I/OO–I/O15) Write Active (ICC) L L X H L Data In (I/OO–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8–I/O15); I/O0 –I/O7 in High Z Write Active (ICC) 9 Mode Power CY62137V MoBL™ CY62137V18 MoBL2™ Ordering Information Speed (ns) 70 Ordering Code CY62137VLL-70ZI Package Name Z44 Operating Range Package Type 44-Pin TSOP II CY62137VLL-70BAI BA48 48-Ball Fine Pitch BGA CY62137V18LL-70BAI BA48 48-Ball Fine Pitch BGA Industrial Shaded areas contain preliminary information. Document #: 38–00738–*B Package Diagrams 48-Ball (7.00 mm x 7.00 mm) FBGA BA48 51-85096-A 10 CY62137V MoBL™ CY62137V18 MoBL2™ Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.