CY62146V MoBL™ CY62146V18 MoBL2™ 256K x 16 Static RAM put/output pins (I/O0 through I/O 15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Features • Low voltage range: — CY62146V18: 1.65V–1.95V • • • • • — CY62146V: 2.7V–3.6V Ultra-low active, standby power Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Functional Description The CY62146V and CY62146V18 are high-performance CMOS static RAMs organized as 262,144 words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH). The in- Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The CY62146V and CY62146V18 are available in 48-Ball FBGA and standard 44-Pin TSOP Type II (forward pinout) packaging. Logic Block Diagram Pin Configurations TSOP II (Forward) Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 SENSE AMPS A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 256K x 16 RAM Array 2048 x 2048 I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A10 A11 A12 A13 A14 A15 A16 A17 BHE WE CE OE BLE 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A17 62146V–2 62146V–1 MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 23, 2000 CY62146V MoBL™ CY62146V18 MoBL2™ Pin Configurations (continued) FBGA Top View 4 3 1 2 BLE OE A0 I/O8 BHE I/O9 5 6 A1 A2 NC A A3 A4 CE I/O0 B I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H 62146V–3 Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current .................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied ............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V Device DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Range Ambient Temperature VCC CY62146V18 Industrial –40°C to +85°C 1.65V to 1.95V CY62146V DC Input Voltage[1] .................................... −0.5V to VCC + 0.5V Industrial –40°C to +85°C 2.7V to 3.6V Shaded areas contain preliminary information. Product Portfolio Power Dissipation (Industrial) VCC Range Product VCC(min.) VCC(typ.)[2] Operating (ICC) VCC(max.) Speed [2] Typ. Maximum CY62146V 2.7V 3.0V 3.6V 70 ns 7 mA 15 mA CY62146V18 1.65V 1.80V 1.95V 70 ns 3 mA 7 mA Standby (ISB2) [2] Typ. Maximum 2 µA Shaded areas contain preliminary information. Notes: 1. VIL(min.) = –2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. . 2 20 µA 20 µA CY62146V MoBL™ CY62146V18 MoBL2™ Electrical Characteristics Over the Operating Range CY62146V Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –1.0 mA VOL Output LOW Voltage IOL = 2.1 mA VIH Input HIGH Voltage VIL IIX IOZ Output Leakage Current ICC VCC Operating Supply Current Min. VCC = 2.7V Typ.[2] Max. V VCC = 2.7V VCC = 3.6V 2.2 Input LOW Voltage VCC = 2.7V –0.5 Input Load Current GND < VI < VCC GND < VO < V CC, Output Disabled Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.3V, VIN > V CC – 0.3V or VIN < 0.3V, f = fMAX ISB2 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.3V VIN > V CC – 0.3V or VIN < 0.3V, f = 0 VCC = 3.6V V V 0.8 V +1 +1 µA –1 +1 +1 µA 7 15 mA 1 2 mA 100 µA 20 µA Max. Unit IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 0.4 VCC + 0.5V –1 VCC = 3.6V IOUT = 0 mA, f = fMAX = 1/tRC, CMOS Levels Unit 2.4 LL 2 Shaded areas contain preliminary information. CY62146V18 Parameter Description Test Conditions Min. VOH Output HIGH Voltage IOH = –0.1 mA VCC = 1.65V VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V VIH Input HIGH Voltage VCC = 1.95V VIL Input LOW Voltage VCC = 1.65V IIX Input Load Current GND < VI < VCC –1 IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 ICC VCC Operating Supply Current IOUT = 0 mA, f = fMAX = 1/tRC, CMOS Levels VCC = 1.95V IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-Down Current— CMOS Inputs CE > V CC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = fMAX ISB2 Automatic CE Power-Down Current— CMOS Inputs CE > V CC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f = 0 VCC = 1.95V LL Typ.[2] 1.5 V 0.2 V 1.4 VCC + 0.3V V –0.5 0.4 V +1 +1 µA +1 +1 µA 3 7 mA 1 2 mA 100 µA 20 µA 2 Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC= VCC(typ.) Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 Max. Unit 6 pF 8 pF CY62146V MoBL™ CY62146V18 MoBL2™ Thermal Resistance Description Thermal Resistance (Junction to Ambient)[3] Test Conditions Symbol Others BGA Unit Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA TBD TBD °C/W ΘJC TBD TBD °C/W Thermal Resistance (Junction to Case)[3] AC Test Loads and Waveforms R1 R1 VCC ALL INPUT PULSES VCC OUTPUT VCC Typ OUTPUT INCLUDING JIG AND SCOPE Equivalent to: R2 5 pF R2 30 pF INCLUDING JIG AND SCOPE (a) (b) 90% 10% 90% 10% GND Rise Time: 1 V/ns Fall Time: 1 V/ns C62146V–5 C62146V–4 THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 3.0V 1.8V Unit R1 1105 15294 Ohms R2 1550 11300 Ohms RTH 645 6500 Ohms VTH 1.75V 0.85V Volts Shaded areas contain preliminary information. Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions Min. Typ.[2] Max. Unit VDR VCC for Data Retention (CY62147V18) 1.0 1.95 V VDR VCC for Data Retention (CY62147V) 1.0 3.6 V ICCDR Data Retention Current 5.5 µA tCDR[3] Chip Deselect to Data Retention Time 0 ns tR[4.] Operation Recovery Time 100 µs VCC= 1.0V CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V No input may exceed VCC + 0.3V LL 0.2 Note: 4. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable VCC(min.) >10 µs. 4 CY62146V MoBL™ CY62146V18 MoBL2™ Data Retention Waveform DATA RETENTION MODE VCC(min.) VCC VCC(min.) VDR > 1.0 V tR tCDR CE C62146V–6 Switching Characteristics Over the Operating Range[5] 70 ns Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns tLZOE 70 OE LOW to Low Z tHZOE CE LOW to Low Z CE HIGH to High Z[6, 7] tPU CE LOW to Power-Up tPD CE HIGH to Power-Down tDBE BHE / BLE LOW to Data Valid tLZBE BHE / BLE LOW to Low Z ns 25 10 ns ns 25 0 ns ns 70 ns 35 ns 5 BHE / BLE HIGH to High Z ns ns 5 [6] tHZCE WRITE CYCLE 10 [7] tLZCE tHZBE 70 [6, 7] OE HIGH to High Z ns ns 25 ns [8, 9] tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 50 ns tBW BHE / BLE Pulse Width 60 ns tSD Data Set-Up to Write End 30 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[6, 7] tLZWE WE HIGH to Low Z ns 25 [6] 10 ns ns Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified I OL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. t HZOE, tHZCE, and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 5 CY62146V MoBL™ CY62146V18 MoBL2™ Switching Waveforms Read Cycle No. 1 [10, 11] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID 62146V–7 Read Cycle No. 2 [11, 12] tRC CE tPD tHZCE tACE OE tHZOE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB 62146V–8 Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 6 CY62146V MoBL™ CY62146V18 MoBL2™ Switching Waveforms (continued) [8, 13, 14] Write Cycle No. 1 (WE Controlled) tWC ADDRESS CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 15 tHZOE Write Cycle No. 2 (CE Controlled) 62146V–9 [8, 13, 14] tWC ADDRESS tSCE CE tSA tAW BHE/BLE WE tHA tBW tPWE tSD DATA I/O tHD DATAIN VALID 62146V–10 Notes: 13. Data I/O is high-impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied. 7 CY62146V MoBL™ CY62146V18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [9, 14] tWC ADDRESS CE tAW tHA tBW BHE/BLE WE tSA tHD tSD DATA I/O DATAIN VALID NOTE 15 tLZWE tHZWE 62146V–11 [15] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) tWC ADDRESS CE tAW tHA tBW BHE/BLE tSA WE tSD DATA I/O tHD DATAIN VALID NOTE 15 tLZWE tHZWE C62146V–12 8 CY62146V MoBL™ CY62146V18 MoBL2™ Typical DC and AC Characteristics Normalized Operating Current vs. Supply Voltage 1.4 Standby Current vs. Supply Voltage 45 MoBL2 MoBL 40 1.2 MoBL2 MoBL 35 ISB (µA) 1.0 ICC 0.8 0.6 30 25 20 0.4 15 0.2 0.0 1.7 2.2 2.7 3.2 SUPPLY VOLTAGE (V) 10 1.0 3.7 3.7 2.8 1.9 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 80 70 MoBL2 MoBL 60 TAA (ns) 50 40 30 20 10 1.0 3.7 2.8 1.9 SUPPLY VOLTAGE (V) Truth Table CE WE OE BHE BLE Inputs/Outputs H X X X X High Z Deselect/Power-Down Standby (ISB) L H L L L Data Out (I/O0–I/O 15) Read Active (ICC) L H L H L Data Out (I/O0–I/O 7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8–I/O 15); I/O0–I/O7 in High Z Read Active (ICC) L H L H H High Z Output Disabled Active (ICC) L H H X X High Z Output Disabled Active (ICC) L L X L L Data In (I/O0–I/O15) Write Active (ICC) L L X H L Data In (I/O0–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) L L X H H High Z Output Disabled Active (ICC) 9 Mode Power CY62146V MoBL™ CY62146V18 MoBL2™ Ordering Information Speed (ns) 70 70 Ordering Code CY62146VLL-70ZI Package Name Z44 Package Type 44-Pin TSOP II CY62146VLL-70BAI BA49 48-Ball Fine Pitch BGA CY62146V18LL-70BAI BA49 48-Ball Fine Pitch BGA Operating Range Industrial Shaded areas contain preliminary information. Document #: 38-00647-C Package Diagrams 48-Ball (7.00 mm x 8.5 mm x 1.5 mm) FBGA BA49 51-85106-A 10 CY62146V MoBL™ CY62146V18 MoBL2™ Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.