345A CY7C1345A/GVT71128E36 128K x 36 Synchronous Flow-Through Burst SRAM Features • • • • • • • • • • • • • • • • eral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), and Global Write (GW). Fast access times: 7.5 and 8 ns Fast clock speed: 117 and 100 MHz Provide high-performance 2-1-1-1 access rate Fast OE access times: 4.0 ns 3.3V –5% and +10% power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid Array) and 100-pin TQFP packages Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE), and Sleep Mode Control (ZZ). The data outputs (DQ), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BW1 controls DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and DQP2. BW3 controls DQ17–DQ24 and DQP3. BW4 controls DQ25–DQ32 and DQP4. BW1, BW2, BW3, and BW4 can be active only with BWE being LOW. GW being LOW causes all bytes to be written. Functional Description The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1345A/GVT71128E36 SRAM integrates 131,072x36 SRAM cells with advanced synchronous periph- The CY7C1345A/GVT71128E36 operates from a +3.3V power supply and all outputs operate on a +2.5V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. The device is ideally suited for 486, Pentium®, 680x0, and PowerPC™ systems and for systems that benefit from a wide synchronous data bus. Selection Guide 7C1345A-117 71128E36-7 7C1345A-100 71128E36-8 7C1345A-100 71128E36-9 7C1345A-100 71128E36-10 Maximum Access Time (ns) 7.5 8 8 8 Maximum Operating Current (mA) 370 320 320 320 Maximum CMOS Standby Current (mA) 10 10 10 10 Cypress Semiconductor Corporation Document #: 38-05123 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 13, 2002 CY7C1345A/GVT71128E36 128K x 36 (CY7C1345A/GVT71128E36) Functional Block Diagram[1] BYTE 1 WRITE BW1# BWE# D Q CLK BYTE 2 WRITE BW2# D Q GW# BYTE 3 WRITE BW3# D Q BYTE 4 WRITE ENABLE D CE2 Q byte 2 write byte 1 write CE# Q byte 3 write D byte 4 write BW4# CE2# ZZ Power Down Logic OE# ADSP# ADSC# CLR ADV# A1-A0 Binary Counter & Logic Output Buffers Address Register 128K x 9 x 4 SRAM Array A16-A2 Input Register DQ1-DQ32, DQP1, DQP2 DQP3, DQP4 MODE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. Document #: 38-05123 Rev. *A Page 2 of 16 CY7C1345A/GVT71128E36 Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE CE2 bW4 BW3 BW2 BW1 CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Pin TQFP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1345A/GVT71128E36 (128K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQP2 DQ16 DQ15 VCCQ VSSQ DQ14 DQ13 DQ12 DQ11 VSSQ VCCQ DQ10 DQ9 VSS NC VCC ZZ DQ8 DQ7 VCCQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VCCQ DQ2 DQ1 DQP1 MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A10 A11 A12 A13 A14 A15 A16 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQP3 DQ17 DQ18 VCCQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VCCQ DQ23 DQ24 NC VCC NC VSS DQ25 DQ26 VCCQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VCCQ DQ31 DQ32 DQP4 Document #: 38-05123 Rev. *A Page 3 of 16 CY7C1345A/GVT71128E36 Pin Configurations (continued) 119-Ball Bump BGA 128Kx36—CY7C1345A/GVT71128E36 Top View 1 2 3 4 5 6 7 A VCCQ A6 A4 ADSP A8 A16 VCCQ B NC CE2 A3 ADSC A9 CE2 NC C NC A7 A2 VCC A12 A15 NC D DQ17 DQP3 VSS NC VSS DQP2 DQ16 E DQ18 DQ19 VSS CE VSS DQ14 DQ15 F VCCQ DQ20 VSS OE VSS DQ13 VCCQ G DQ21 DQ22 BW3 ADV BW2 DQ12 DQ11 H DQ23 DQ24 VSS GW VSS DQ10 DQ9 J VCCQ VCC NC VCC NC VCC VCCQ K DQ25 DQ27 VSS CLK VSS DQ7 DQ8 L DQ26 DQ28 BW4 NC BW1 DQ5 DQ6 M VCCQ DQ29 VSS BWE VSS DQ4 VCCQ N DQ30 DQ31 VSS A1 VSS DQ3 DQ2 P DQ32 DQP4 VSS A0 VSS DQP1 DQ1 R NC A5 MODE VCC NC A13 NC T NC NC A10 A11 A14 NC ZZ U VCCQ NC NC NC NC NC VCCQ Pin Descriptions BGA Pins QFP Pins Pin Name Type Description 4P, 4N, 2A, 3A, 37, 36, 35, 34, A0–A16 InputAddresses: These inputs are registered and must meet the set-up 5A, 6A, 3B, 5B, 33, 32, 100, 99, Synchronous and hold times around the rising edge of CLK. The burst counter 2C, 3C, 5C, 6C, 82, 81, 44, 45, generates internal addresses associated with A0 and A1, during 2R, 6R, 3T, 4T, 46, 47, 48, burst cycle and wait cycle. 5T 49,50 5L, 5G, 3G, 3L 93,94,95,96 BW1, BW2, BW3, BW4 InputByte Write: A byte write is LOW for a Write cycle and HIGH for a Synchronous Read cycle. BW1 controls DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and DQP2. BW3 controls DQ17–DQ24 and DQP3. BW4 controls DQ25–DQ32 and DQP4. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. 4M 87 BWE InputWrite Enable: This active LOW input gates byte write operations Synchronous and must meet the set-up and hold times around the rising edge of CLK. 4H 88 GW InputGlobal Write: This active LOW input allows a full 36-bit Write to Synchronous occur independent of the BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK. 4K 89 CLK InputClock: This signal registers the addresses, data, chip enables, write Synchronous control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. Document #: 38-05123 Rev. *A Page 4 of 16 CY7C1345A/GVT71128E36 Pin Descriptions (continued) BGA Pins QFP Pins Pin Name 4E 98 CE InputChip Enable: This active LOW input is used to enable the device Synchronous and to gate ADSP. 6B 92 CE2 InputChip Enable: This active LOW input is used to enable the device. Synchronous 2B 97 CE2 InputChip Enable: This active HIGH input is used to enable the device. Synchronous 4F 86 OE 4G 83 ADV InputAddress Advance: This active LOW input is used to control the Synchronous internal burst counter. A HIGH on this pin generates wait cycle (no address advance). 4A 84 ADSP InputAddress Status Processor: This active LOW input, along with CE Synchronous being LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. 4B 85 ADSC InputAddress Status Controller: This active LOW input causes device to Synchronous be deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon write control inputs. 3R 31 MODE InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst. 7T 64 ZZ Input-Asynchronous Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). DQ1– DQ32 Input/ Output Data Inputs/Outputs: First Byte is DQ1–DQ8. Second Byte is DQ9–DQ16. Third Byte is DQ17–DQ24. Fourth Byte is DQ25–DQ32. Input data must meet set-up and hold times around the rising edge of CLK. 7P, 7N, 6N, 6M, 52, 53, 56, 57, 6L, 7L, 6K, 7K, 58, 59, 62, 63, 7H, 6H, 7G, 6G, 68, 69, 72-75, 6F, 6E, 7E, 7D, 78, 79, 2, 3, 6-9, 1D, 1E, 2E, 2F, 12, 13, 18, 19, 1G, 2G, 1H, 2H, 22-25, 28, 29 1K, 1L, 2K, 2L, 2M, 1N, 2N, 1P Type Input Description Output Enable: This active LOW asynchronous input enables the data output drivers. 6P, 6D, 2D, 2P 51, 80, 1, 30 DQP1– DQP4 Input/ Output Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity bit for DQ9–DQ16. DQP3 is parity bit for DQ17–DQ24 and DQP4 is parity bit for DQ25–DQ32. 4C, 2J, 4J, 6J, 4R 15, 41,65, 91 VCC Supply Core power Supply: +3.3V –5% and +10% 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 17, 40, 67, 90 VSS Ground Ground: GND 1A, 7A, 1F, 7F, 4, 11, 20, 27, 54, 1J, 7J, 1M, 7M, 61, 70, 77 1U, 7U VCCQ I/O Supply Output Buffer Supply: +2.5V (from 2.375V to VCC) 5, 10, 21, 26, 55, 60, 71, 76 VSSQ I/O Ground Output Buffer Ground: GND 14, 16, 38, 39, 42, 43, 66 NC - 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 2U, 3U, 4U, 5U, 6U Document #: 38-05123 Rev. *A No Connect: These signals are not internally connected. Page 5 of 16 CY7C1345A/GVT71128E36 Burst Address Table (MODE = NC/VCC) Burst Address Table (MODE = GND) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A11 A...A10 A...A01 A...A00 A...A11 A...A00 A...A01 A...A10 Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Address Used CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X X L X X X L-H High-Z Deselected Cycle, Power Down None L X L L X X X X L-H High-Z Deselected Cycle, Power Down None L H X L X X X X L-H High-Z Deselected Cycle, Power Down None L X L H L X X X L-H High-Z Deselected Cycle, Power Down None L H X H L X X X L-H High-Z READ Cycle, Begin Burst External L L H L X X X L L-H Q READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H D READ Cycle, Begin Burst External L L H H L X H L L-H Q READ Cycle, Begin Burst External L L H H L X H H L-H High-Z Next X X X H H L H L L-H Q READ Cycle, Continue Burst READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Q READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H D WRITE Cycle, Continue Burst Next H X X X H L L X L-H D READ Cycle, Suspend Burst Current X X X H H H H L L-H Q READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Q READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D Notes: 2. X means “Don’t Care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + BW1*BW2*BW3*BW3]*GW equals LOW. WRITE = H means [BWE + BW1*BW2*BW3*BW3]*GW equals HIGH. 3. BW1 enables write to DQ1–DQ8 and DQP1. BW2 enables write to DQ9–DQ16 and DQP2. BW3 enables write to DQ17–DQ24 and DQP3. BW4 enables write to DQ25–DQ32 and DQP4. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 5. Suspending burst generates wait cycle. 6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification. Document #: 38-05123 Rev. *A Page 6 of 16 CY7C1345A/GVT71128E36 Partial Truth Table for Read/Write FUNCTION GW BWE BW1 BW2 BW3 BW4 READ H H X X X X READ H L H H H H WRITE one byte H L L H H H WRITE all bytes H L L L L L WRITE all bytes L X X X X X Maximum Ratings Power Dissipation.......................................................... 1.6W Short Circuit Output Current ....................................... 20 mA (Above which the useful life may be impaired. For user guidelines only, not tested.) . Operating Range Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V Range VIN ..........................................................–0.5V to +VCC+0.5V Ambient Temperature VCC[9,10] 0°C to +70°C 3.3V –5%/+10% Com’l Storage Temperature (plastic)..................... –55°C to +125°C Junction Temperature ............................................... +125°C Electrical Characteristics Over the Operating Range[11] Parameter VIHD Description Input High (Logic 1) Test Conditions Voltage[12, 13] VIH VIl All other Current[14] Input Leakage ILO Output Leakage Current Voltage[12, 15] VOH Output High VOL Output Low Voltage[12, 15] VCC Supply Voltage[12] VCCQ I/O Supply Voltage Max. Unit 1.7 VCC+0.3 V 1.7 4.6 V –0.3 0.7 V 0V < VIN < VCC –2 2 µA Output(s) disabled, 0V < VOUT < VCC –2 2 µA IOH = –2.0 mA 1.7 Input Low (Logic 0) Voltage[12, 13] ILI Parameter Data Inputs (DQxx) Min. V IOL = 2.0 mA 0.7 V 3.135 3.6 V 2.375 VCC V -7 -8 Typ. 117 MHz 100 MHz -9 90 MHz -10 50 MHz Unit 320 290 200 mA 10 10 10 10 mA 10 20 20 20 20 mA 40 80 70 60 40 mA Description Conditions ICC Power Supply Current: Operating[16, 17, 18] Device selected; all inputs < VILor > VIH; cycle time > tKC Min.; VCC = Max.; outputs open 150 370 ISB2 CMOS Standby[17, 18] Device deselected; VCC = Max.; all inputs < VSS + 0.2 or > VCC – 0.2; all inputs static; CLK frequency = 0 5 ISB3 TTL Standby[17, 18] Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 ISB4 Clock Running[17, 18] Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC Min. Notes: 9. Please refer to waveform (c) 10. Power Supply ramp-up should be monotonic. 11. Values in table are associated with the operating frequencies listed. 12. All voltages referenced to VSS (GND). 13. Overshoot: VIH < +6.0V for t < tKC /2. Undershoot: VIL < –2.0V for t < tKC /2. 14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA. 15. AC I/O curves are available upon request. 16. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 17. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active. 18. Typical values are measured at 3.3V, 25°C and 20-ns cycle time. Document #: 38-05123 Rev. *A Page 7 of 16 CY7C1345A/GVT71128E36 Thermal Consideration Parameter Description ΘJA Thermal Resistance - Junction to Ambient ΘJC Thermal Resistance - Junction to Case Conditions TQFP Typ. Unit Still air, soldered on 4.25 x 1.125 inch 4-layer PCB 25 °C/W 9 °C/W Capacitance Parameter Description CI Input Capacitance Test Conditions [19] [19] CO Input/Output Capacitance (DQ) Typ. Max. Unit 4 5 pF 7 8 pF TA = 25°C, f = 1 MHz, VCC= 3.3V Typical Output Buffer Characteristics Output High Voltage Pull-up Current Output Low Voltage Pull-down Current VOH (V) IOH (mA) Min. IOH (mA) Max. VOL (V) IOL (mA) Min. IΟL (mA) Max. –0.5 –38 –105 –0.5 0 0 0 –38 –105 0 0 0 0.8 –38 –105 0.4 10 20 1.25 –26 –83 0.8 20 40 1.5 –20 –70 1.25 31 63 2.3 0 –30 1.6 40 80 2.7 0 –10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80 AC Test Loads and Waveforms tP U ALL INPUT PULSES 2.5V Z0 = 50Ω RL = 50Ω Vt = 1.25V (a) 10% 90% 0V Rise Time: 1.8 V/ns 90% 10% = 200us V c c ty p V c c m in F o r p ro p e r R E S E T b rin g V c c d o w n t o 0 V Fall Time: 1.8 V/ns (b) (c) Note: 19. This parameter is sampled. 20. Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for t<200 ms. Document #: 38-05123 Rev. *A Page 8 of 16 CY7C1345A/GVT71128E36 Switching Characteristics Over the Operating Range[21] -7 117 MHz Parameter Description Min. Max. -8 100 MHz Min. Max. -9 90 MHz Min. Max. -10 50 MHz Min. Max. Unit Clock tKC Clock Cycle Time 8.5 10 11 20 ns tKH Clock HIGH Time 3 4 4.5 4.5 ns tKL Clock LOW Time 3 4 4.5 4.5 ns Output Times tKQ Clock to Output Valid tKQX Clock to Output Invalid 7.5 8 8.5 10 ns 2 2 2 2 ns tKQLZ Clock to Output in Low-Z[19, 22, 23] 0 0 0 0 ns tKQHZ Clock to Output in High-Z[19, 22, 23] 2 tOEQ Valid[24] tOELZ tOEHZ OE to Output OE to Output in 2 4.0 Low-Z[19, 22, 23] OE to Output in High-Z 3.5 0 [19, 22, 23] 3.5 2 4.0 0 3.5 3.5 2 4.0 0 3.5 3.5 ns 4.0 ns 0 3.5 ns 3.5 ns Set-Up Times tS Address, Controls and Data In[25] 1.5 2.0 2.0 2.0 ns Address, Controls and Data In[25] 0.5 0.5 0.5 0.5 ns Hold Times tH Notes: 21. Test conditions as specified with the output loading as shown in AC Test Loads unless otherwise noted. Values in table are associated with the operating frequencies listed. 22. Measured at ±200 mV from steady state. 23. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 24. OE is a “Don’t Care” when a byte write enable is sampled LOW. 25. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “Don’t Care” as defined in the truth table. Document #: 38-05123 Rev. *A Page 9 of 16 CY7C1345A/GVT71128E36 Timing Diagrams Read Timing[26] KC t KL CLK t t S KH ADSP# t H ADSC# t S A1 ADDRESS t BW1#, BW2#, BW3#, BW4#, BWE#, GW# A2 H CE# (See Note) t S ADV# t H OE# tKQ t KQLZ DQ t t OEQ KQ t OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) Q(A2+2) BURST READ Note: 26. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active. Document #: 38-05123 Rev. *A Page 10 of 16 CY7C1345A/GVT71128E36 Timing Diagrams (continued) Write Timing[26] CLK tS ADSP# tH ADSC# tS A1 ADDRESS A2 A3 tH BW1#, BW2#, BW3#, BW4#, BWE# GW# CE# (See Note) tS ADV# tH OE# tOEHZ tKQX DQ Q D(A1) SINGLE WRITE Document #: 38-05123 Rev. *A D(A2) D(A2+2) D(A2+2) D(A2+2) BURST WRITE D(A2+3) D(A3) D(A3+1) D(A3+2) BURST WRITE Page 11 of 16 CY7C1345A/GVT71128E36 Timing Diagrams (continued) Read/Write Timing[26] CLK tS ADSP# tH ADSC# tS ADDRESS A1 A2 A3 A4 A5 tH BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# (See Note) ADV# OE# DQ Q(A1) Q(A2) Single Reads Document #: 38-05123 Rev. *A D(A3) Single Write Q(A4) Q(A4+1) Q(A4+2) Burst Read Q(A4+3) D(A5) D(A5+1) Burst Write Page 12 of 16 CY7C1345A/GVT71128E36 Ordering Information Speed (MHz) 117 Ordering Code CY7C1345A-117AC Package Name A101 Package Type Operating Range 100-Lead Thin Quad Flat Pack Commercial GVT71128E36T-7 CY7C1345A-117BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm) GVT71128E36B-7 100 CY7C1345A-100AC A101 100-Lead Thin Quad Flat Pack Commercial GVT71128E36T-8 CY7C1345A-100BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm) GVT71128E36B-8 100 CY7C1345A-100AC A101 100-Lead Thin Quad Flat Pack Commercial GVT71128E36T-9 CY7C1345A-100BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm) GVT71128E36B-9 100 CY7C1345A-100AC A101 100-Lead Thin Quad Flat Pack Commercial GVT71128E36T-10 CY7C1345A-100BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm) GVT71128E36B-10 Document #: 38-05123 Rev. *A Page 13 of 16 CY7C1345A/GVT71128E36 Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05123 Rev. *A Page 14 of 16 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1345A/GVT71128E36 Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05123 Rev. *A Page 15 of 16 CY7C1345A/GVT71128E36 Document History Page Document Title: CY7C1345A/GVT71128E36 128K x 36 Synchronous Flow-Through Burst SRAM Document Number: 38-05123 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 108314 09/25/01 BRI New Cypress spec—converted from Galvantech format *A 121069 11/13 /02 DSG Updated package drawing 51-85115 (BG119) to rev. *B *B 123136 01/19/03 RBI Added power up requirements to operating conditions information. Document #: 38-05123 Rev. *A Page 16 of 16