CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.7, 3.0 and 3.5 ns Optimal for depth expansion Single 3.3V –5% and +5% power supply VDD Separate VDDQ for 3.3V or 2.5V Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High-density, high-speed packages JTAG boundary scan for BGA packaging version Available in 119-ball bump BG,165-ball FBGA package, and 100-pin TQFP packages (CY7C1440V33 and CY7C1442V33). 209 FBGA package for CY7C1446V33. Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors. The CY7C1440V33, CY7C1442V33, and CY7C1446V33 SRAMs integrate 1,048,576 x 36/2,097,152 x 18 and 524,288 x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). The data (DQa,b,c,d) and the data parity (DPa,b,c,d) outputs, enabled by OE, are also asynchronous. DQa,b,c,d and DPa,b,c,d apply to CY7C1440V33, DQa,b and DPa,b apply to CY7C1442V33, and DQa,b,c,d,e,f,g,h and DPa,b,c,d,e,f,g,h apply to CY7C1446V33. a,b,c,d,e,f,g,h each are eight bits wide in the case of DQ and one bit wide in the case of DP. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to eight bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPd. BWd controls DQ and DPd. BWe controls DQe and DPe. BWf controls DQf and DPf. BWg controls DQg and DPg. BWh controls DQh and DPh. BWa, BWb, BWc, BWd, BWe, BWf, BWg, and BWh can be active only with BWE LOW. GW LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the immediately next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. All inputs and outputs of the CY7C1440V33, CY7C1442V33, and the CY7C1446V33 are JEDEC-standard JESD8-5 -compatible. Selection Guide[1] Maximum Access Time Maximum Operating Current Com’l Maximum CMOS Standby Current CY7C1440V33 CY7C1446V33 CY7C1446V33 -300 CY7C1440V33 CY7C1446V33 CY7C1446V33 -250 CY7C1440V33 CY7C1446V33 CY7C1446V33 -200 CY7C1440V33 CY7C1446V33 CY7C1446V33 -167 Unit 2.3 2.7 3.0 3.5 ns TBD TBD TBD TBD mA TBD TBD TBD TBD mA Note: 1. Shaded areas contain advance information. Cypress Semiconductor Corporation Document #: 38-05184 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 13, 2002 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Logic Block Diagram CY7C1440V33–1M x 36 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP Q A[19:0] 20 GW 18 DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS Q D DQb, DPb BYTEWRITE REGISTERS Q D DQa, DPa BYTEWRITE REGISTERS Q D BWE BW d D BWc BWb BWa CE1 CE2 CE3 D ENABLE CE REGISTER 20 18 ADDRESS CE REGISTER D 1M X36 MEMORY ARRAY Q 36 36 Q D ENABLE DELAY Q REGISTER OUTPUT REGISTERS CLK INPUT REGISTERS CLK OE SLEEP CONTROL ZZ DQa,b,c,d DPa,b,c,d CY7C1446V33–2M × 18 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[20:0] GW Q 21 BWE BW b 19 DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS Q D ENABLE CE CE REGISTER Q D D BWa CE1 CE2 CE3 ADDRESS CE REGISTER D 19 21 2M X 18 MEMORY ARRAY Q 18 D ENABLE DELAY Q REGISTER OUTPUT REGISTERS CLK 18 INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQa,b DPa,b Document #: 38-05184 Rev. *B Page 2 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY CY7C1446V33 – 512K x 72 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[18:0] GW Q 19 BWE BW h 17 DQh, DPh BYTEWRITE REGISTERS DQg, DPg BYTEWRITE REGISTERS Q D DQf, DPf BYTEWRITE REGISTERS Q D DQe, DPe BYTEWRITE REGISTERS Q D DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS Q D DQb, DPb BYTEWRITE REGISTERS Q D DQa, DPa BYTEWRITE REGISTERS Q D D BWg BWf BWe BW d D BWc BWb BWa CE1 CE2 CE3 ADDRESS CE REGISTER D 17 19 512KX72 MEMORY ARRAY Q Q 72 D ENABLE CE REGISTER 72 Q D ENABLE DELAY Q REGISTER OUTPUT REGISTERS CLK INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQa,b,c,d,e,f,g,h DPa,b,c,d,e,f,g,h Document #: 38-05184 Rev. *B Page 3 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1442 (2M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05184 Rev. *B A NC NC VDDQ VSSQ NC DPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC A A A A A A A A A VSS VDD 72M A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPb NC NC DQb NC DQb VDDQ VDDQ VSSQ VSSQ NC DQb NC DQb DQb DQb DQb DQb VSSQ VSSQ VDDQ VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSSQ VSSQ DQa DQb DQa DQb DQa DPb NC DQa VSSQ VSSQ VDDQ VDDQ NC DQa NC DQa DQPa NC MODE A A A A A1 A0 CY7C1440 (1M X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 72M A VSS VDD A A A A A A A A A DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd Page 4 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Pin Configurations (continued) CY7C1440V33 (1M x 36) 1 3 2 A VDDQ B C NC NC D E DQc DQc A DQPc DQc VSS VSS F VDDQ DQc VSS A A A A A 6 7 ADSP ADSC A A A A VDDQ VDD A VSS A DQPb CE1 VSS VSS BWb VSS DQb DQb NC DQc DQc VDD DQd DQd BWc VSS NC VSS BWd CLK NC DQd DQd VSS VSS VSS VDDQ K DQd L M VDDQ N DQd P DQd R NC T NC A 72M MODE A U VDDQ TMS TDI DQd 5 OE ADV GW VDD G H J DQc DQc 4 DQPd NC NC DQb DQb DQb VDD VDDQ DQb DQb VDDQ DQa DQa BWa DQa DQa BWE VSS DQa A1 VSS DQa VDDQ DQa A0 VSS DQPa DQa VDD A NC A A A NC ZZ TCK TDO NC VDDQ 5 6 7 A A VDDQ NC VSS DQb CY7C1442V33 (2M x 18) 1 A VDDQ B NC NC C D DQb 2 3 A A A 4 A ADSP ADSC A A A NC DQb A VDD VSS VSS NC A VSS CE1 VSS VSS VSS VSS E NC F VDDQ NC VSS G H J NC DQb VDDQ BWb VSS NC K NC L M DQb DQb NC VDD DQb NC OE ADV GW VDD VSS VSS CLK NC VDDQ N DQb DQb NC VSS VSS P NC DQPb R NC T 72M U VDDQ Document #: 38-05184 Rev. *B A DQPa NC DQa NC NC NC DQa DQa VDD VDDQ DQa NC VDDQ NC DQa BWa DQa NC BWE VSS NC A1 VSS DQa VDDQ NC VSS A0 VSS NC DQa A A MODE A Vdd A NC A A NC ZZ TMS TDI TCK TDO NC VDDQ NC VSS NC A Page 5 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Pin Configuration (continued) 165-ball Bump FBGA CY7C1440V33 (1M x 36) – 11 x 15 FBGA 1 2 3 4 5 6 7 8 9 10 11 A NC A CE1 BWc BWb CE3 BWE ADSC ADV A NC B C D E F G H J K L M N P NC DPc A NC CE2 VDDQ BWd VSS BWa VSS CLK VSS GW VSS OE VSS ADSP VDDQ A NC NC DPb DQb R DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb NC DQd VSS DQd NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ DQa DQd DQd DQd DQd VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DPd NC VDDQ VSS NC A VSS VSS VDDQ NC DPa NC 72M A A TDI A1 TDO A A A A MODE A A A TMS A0 TCK A A A A 11 CY7C1442V33 (2M x 18) – 11 x 15 FBGA 1 2 3 4 5 6 7 8 9 10 A NC A CE1 BWb NC CE3 BWE ADSC ADV A A B C D E F G H J K L M N P NC NC A NC CE2 VDDQ NC VSS BWa VSS CLK VSS GW VSS OE VSS ADSP VDDQ A NC NC DPa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VSS NC NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ NC DQb DQb NC NC VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa NC NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DPb NC VDDQ VSS NC A VSS VSS VDDQ NC NC NC 72M A A TDI A1 TDO A A A A MODE A A A TMS A0 TCK A A A A R Document #: 38-05184 Rev. *B Page 6 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY CY7C1446 (512K x72) 1 2 3 4 5 6 A DQg DQg B DQg DQg BWSc C DQg DQg BWSh D DQg DQg VSS NC NC OE E DPg DPc VDDQ VDDQ VDD DQc VSS VSS VDDQ VDDQ VSS A CE2 7 8 9 10 11 CE3 A DQb DQb ADSP ADSC ADV BWSg NC BW A BWSb BWSf DQb DQb BWSd NC CE1 NC BWSe BWSa DQb DQb NC GW VSS DQb DQb VDD VDD VDDQ VDDQ DPf DPb VSS NC VSS VSS VSS DQf VDD NC VDD VDDQ VDDQ DQf DQf NC VSS VSS VSSQ DQf DQf F DQc G DQc H DQc DQc VSS VSS J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS VSS VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa DPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ NC NC MODE NC NC VSS DQe DQe R DPd DQc DPa DQf DPe T DQd DQd VSS U DQd DQd NC A A A A A A DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe Pin Definitions Pin Name I/O Pin Description A0 A1 A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. BWa BWb BWc BWd BWe BWf BWg BWh InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d,e,f,g,h and BWE). BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Document #: 38-05184 Rev. *B Page 7 of 31 PRELIMINARY CY7C1440V33 CY7C1442V33 CY7C1446V33 Pin Definitions I/O Pin Description CE1 Pin Name InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.(TQFP Only) CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.(TQFP Only) OE InputAsynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. MODE InputStatic Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. ZZ InputAsynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved.This pin can also be left as a NC DQa, DPa DQb, DPb DQc, DPc DQd, DPd DQe, DPe DQf, DPf DQg, DPg DQh, DPh I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition.DQ a,b,c,d,e,f,g and h are eight bits wide. DP a,b,c,d,e,f,g and h are one bit wide. TDO JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only) Synchronous This pin can be left as a floating pin if JTAG is not used. TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.(BGA Only) This pin Synchronous can be left as a floating pin if JTAG is not used. TMS Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous (BGA Only) This pin can be left as a floating pin if JTAG is not used. TCK JTAG serial clock VDD Power Supply VSS Ground VDDQ VSSQ Power supply inputs to the core of the device. Should be connected to 3.3V –5% +5% power supply. Ground for the core of the device. Should be connected to ground of the system. I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.375(min) to Vdd(max) I/O Ground 72M NC Serial clock to the JTAG circuit. (BGA Only) This pin can be left as a floating pin if JTAG is not used. Ground for the I/O circuitry. Should be connected to ground of the system. No connects. Reserved for address expansion. – Document #: 38-05184 Rev. *B No connects. Page 8 of 31 PRELIMINARY Introduction Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.2 ns (300-MHz device). The CY7C1440V33/CY7C1446V33/CY7C1446V33 support secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWa,b,c,d for CY7C1440V33, BWa,b for CY7C1442V33, and BWa,b,c,d,e,f,g,h for CY7C1446V33) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects (CE1, CE2, CE3 for TQFP/CE1 for BGA) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.2 ns (300-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address Document #: 38-05184 Rev. *B CY7C1440V33 CY7C1442V33 CY7C1446V33 advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BWx) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BWx signals. The CY7C1440V33/CY7C1442V33/CY7C1446V33 provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWa,b,c,d for CY7C1440V33, BWa,b,c,d,e,f,g,h for CY7C1446V33, and BWa,b for CY7C1446V33) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1440V33/CY7C1442V33/CY7C1446V33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWx) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented to A[x:0] (x = 20 for CY7C1440V33, x = 21 for CY7C1442V33, and x = 19 for CY7C1446V33) is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQ[x:0] is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1440V33/CY7C1442V33/CY7C1446V33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ[x:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[x:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1440V33/CY7C1442V33/CY7C1446V33 provides a two-bit wrap around counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Page 9 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Linear Burst Sequence Interleaved Burst Sequence First Address A[1:0]] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00 First Address Second Address Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Snooze mode standby current ZZ > VDD – 0.2V tZZS Device operation to ZZ ZZ > VDD – 0.2V tZZREC ZZ recovery time ZZ < 0.2V Cycle Min. Max. Unit 15 mA 2tCYC ns 2tCYC ns Descriptions[2, 3, 4, 5] Next Cycle Add. Used ZZ CE3 CE2 CE1 ADSP ADSC ADV OE DQ Write Unselected None L X X 1 X 0 X X Hi-Z X Unselected None L 1 X 0 0 X X X Hi-Z X Unselected None L X 0 0 0 X X X Hi-Z X Unselected None L 1 X 0 1 0 X X Hi-Z X Unselected None L X 0 0 1 0 X X Hi-Z X Begin Read External L 0 1 0 0 X X X Hi-Z X Begin Read External L 0 1 0 1 0 X X Hi-Z Read Continue Read Next L X X X 1 1 0 1 Hi-Z Read Continue Read Next L X X X 1 1 0 0 DQ Read Continue Read Next L X X 1 X 1 0 1 Hi-Z Read Continue Read Next L X X 1 X 1 0 0 DQ Read Suspend Read Current L X X X 1 1 1 1 Hi-Z Read Suspend Read Current L X X X 1 1 1 0 DQ Read Suspend Read Current L X X 1 X 1 1 1 Hi-Z Read Suspend Read Current L X X 1 X 1 1 0 DQ Read Notes: 2. X = “Don’t Care.” 1 = HIGH, 0 = LOW. 3. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has a single chip select CE1. Document #: 38-05184 Rev. *B Page 10 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Cycle Descriptions[2, 3, 4, 5] Next Cycle Add. Used ZZ CE3 CE2 CE1 ADSP ADSC ADV OE DQ Write Begin Write Current L X X X 1 1 1 X Hi-Z Write Begin Write Current L X X 1 X 1 1 X Hi-Z Write Begin Write External L 0 1 0 1 0 X X Hi-Z Write Continue Write Next L X X X 1 1 0 X Hi-Z Write Continue Write Next L X X 1 X 1 0 X Hi-Z Write Suspend Write Current L X X X 1 1 1 X Hi-Z Write Suspend Write Current L X X 1 X 1 1 X Hi-Z Write ZZ “sleep” None H X X X X X X X Hi-Z X Write Cycle Descriptions[2, 3] Function (CY7C1440V33) GW BWE BWd BWc BWb BWa Read 1 1 X X X X Read 1 0 1 1 1 1 Write Byte 0–DQa 1 0 1 1 1 0 Write Byte 1–DQb 1 0 1 1 0 1 Write Bytes 1, 0 1 0 1 1 0 0 Write Byte 2–DQc 1 0 1 0 1 1 Write Bytes 2, 0 1 0 1 0 1 0 Write Bytes 2, 1 1 0 1 0 0 1 Write Bytes 2, 1, 0 1 0 1 0 0 0 Write Byte 3–DQd 1 0 0 1 1 1 Write Bytes 3, 0 1 0 0 1 1 0 Write Bytes 3, 1 1 0 0 1 0 1 Write Bytes 3, 1, 0 1 0 0 1 0 0 Write Bytes 3, 2 1 0 0 0 1 1 Write Bytes 3, 2, 0 1 0 0 0 1 0 Write Bytes 3, 2, 1 1 0 0 0 0 1 Write All Bytes 1 0 0 0 0 0 Write All Bytes 0 X X X X X Function (CY7C1446V33) Read GW BWE BWb BWa 1 1 X X Read 1 0 1 1 Write Byte 0–DQ[7:0] and DP0 1 0 1 0 Write Byte 1–DQ[15:8] and DP1 1 0 0 1 Write All Bytes 1 0 0 0 Write All Bytes 0 X X X IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1440V33/CY7C1442V33 incorporates a serial boundary scan Test Access Port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 Document #: 38-05184 Rev. *B compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V I/O logic levels. Page 11 of 31 PRELIMINARY Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port–Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. Test Data Out (TDO) CY7C1440V33 CY7C1442V33 CY7C1446V33 When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 70-bit-long register, and the x18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The TDO output pin is used to serially clock data-out from the registers. The e output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. Performing a TAP Reset TAP Instruction Set A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. TAP Registers The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Document #: 38-05184 Rev. *B Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. Page 12 of 31 PRELIMINARY EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock Document #: 38-05184 Rev. *B CY7C1440V33 CY7C1442V33 CY7C1446V33 operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (TCS and TCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 13 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY TAP Controller State Diagram[76] 1 TEST-LOGIC RESET 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05184 Rev. *B Page 14 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register . . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[7, 10] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = −4.0 mA 2.4 V VOH2 Output HIGH Voltage IOH = −100 µA 3.0 V VOL1 Output LOW Voltage IOL = 8.0 mA 0.4 V VOL2 Output LOW Voltage IOL = 100 µA 0.2 V VIH Input HIGH Voltage 1.8 VDD + 0.3 V VIL Input LOW Voltage –0.5 0.8 V IX Input Load Current –5 5 µA GND ≤ VI ≤ VDDQ TAP AC Switching Characteristics Over the Operating Range[8, 9] Parameters Description Min. Max. Unit 10 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency 100 ns tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns Set-up Times Notes: 7. All voltage referenced to ground. 8. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 9. Test conditions are specified using the load in TAP AC test conditions. TR/TF = 1 ns. 10. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. Document #: 38-05184 Rev. *B Page 15 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY TAP AC Switching Characteristics Over the Operating Range[8, 9] Parameters tCS Description Min. Max. Unit Capture Set-up to TCK Rise 10 ns tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns Hold Times Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 0 ns ns TAP Timing and Test Conditions 1.25V ALL INPUT PULSES Vih 50Ω 0V TDO Z0 =50Ω CL =20 pF GND tTH tTL (a) Test Clock TCK tTC YC tTMSS tTMSH Test Mode Select TMS t TDIS t TDIH Test Data-In TDI Test Data-Out TDO tTD OV Document #: 38-05184 Rev. *B tTDOX Page 16 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Identification Register Definitions Instruction Field x18 x36 Description Revision Number (31:29) 000 000 Reserved for version number. Department Number (27:25) 101 101 Department Number Voltage (28&24) 00 00 Architecture (23:21) 000 000 Architecture Type Memory type (20:18) 000 000 Defines type of memory Device Width (17:15) 010 100 Defines width of the SRAM. x36 or x18 111 Defines the density of the SRAM Device Density (14:12) 111 Cypress JEDEC ID (11:1) 00000110100 ID Register Presence (0) 1 00000110100 Allows unique identification of SRAM vendor. 1 Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size (x18) Bit Size (x36) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 51 70 Identification Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use. This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. RESERVED 101 Do Not Use. This instruction is reserved for future use. RESERVED 110 Do Not Use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Boundary Scan Order (1M × 36) Boundary Scan Order (1M × 36) Bit # Signal Name Bump ID Document #: 38-05184 Rev. *B Bit # Signal Name Bump ID Bit # Signal Name Bump ID Bit # Signal Name Bump ID Page 17 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Boundary Scan Order (1M × 36) Bit # Signal Name Bump ID Bit # Signal Name Boundary Scan Order (2M × 18) Bump ID Bit # Signal Name Bump ID Bit # Signal Name Bump ID Boundary Scan Order (2M × 18) Bit # Signal Name Bump ID Document #: 38-05184 Rev. *B Bit # Signal Name Bump ID Page 18 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–55°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V DC Voltage Applied to Outputs in High-Z State[11] ................................ –0.5V to VDDQ + 0.5V DC Input Voltage[11] ............................ –0.5V to VDDQ + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Ambient Temp.[12] VDD VDDQ Com’l 0−70°C 3.3V +5% /–5% 2.375V(Min) VDD(Max) Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.135 3.465 V VDDQ I/O Supply Voltage 2.375 VDD V VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA Vddq=3.3V 2.4 V VDD = Min., IOH = –1.0 mA Vddq=2.5V 2.0 V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA Vddq=3.3V 0.4 V VDD = Min., IOL = 1.0 mA Vddq=2.5V 0.4 V VIH Input HIGH Voltage Vddq=3.3 V 2.0 V Vddq=2.5V 1.7 V VIL Input LOW Voltage[11] Vddq=3.3V –0.3 0.8 V Vddq=2.5V –0.3 0.7 V IX Input Load Current GND ≤ VI ≤ VDDQ 5 µA 30 µA 5 µA 300 MHz TBD mA 250MHz TBD mA 200MHz TBD mA 166Mhz TBD mA 300 MHz TBD mA 250MHz TBD mA 200MHz TBD mA 166Mhz TBD mA Input Current of MODE IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB1 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC ISB2 Automatic CE Power-down Current—CMOS Inputs Max. VDD, Device Deselected, VIN ≤ 0.3V or VIN > VDDQ − 0.3V, f=0 All speed grades TBD mA ISB3 Automatic CE Power-down Current—CMOS Inputs Max. VDD, Device Deselected, or VIN £ 0.3V or VIN > VDDQ - 0.3V f = fMAX = 1/tCYC 300 MHz TBD mA 250MHz TBD mA 200MHz TBD mA 166Mhz TBD mA All speed grades TBD mA ISB4 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 Notes: 11. Minimum voltage equals –2.0V for pulse durations of less than 20 ns. 12. TA is the ambient temperature. Document #: 38-05184 Rev. *B Page 19 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Capacitance[13] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V, VDDQ = 2.5V Max. Unit TBD pF TBD pF TBD pF AC Test Loads and Waveforms R = 317Ω Vddq OUTPUT ALL INPUT PULSES OUTPUT Z0 = 50Ω Vdd 5 pF R = 351Ω VTH = 1.5V INCLUDING JIG AND SCOPE (a) 90% 10% 90% 10% RL = 50Ω [14] GND ≤ 2.5V/ns ≤2.5V/ns (c) (b) Switching Characteristics Over the Operating Range[15, 16, 17] -300 Parameter Description Min. Max. -250 Min. Max. -200 Min. Max. -167 Min. Max. Unit tCYC Clock Cycle Time 3.3 4.0 5.0 6.0 ns tCH Clock HIGH 1.5 1.5 2.0 2.4 ns tCL Clock LOW 1.5 1.5 2.0 2.4 ns tAS Address Set-up Before CLK Rise 1.5 1.5 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.5 1.5 1.5 1.5 ns tADS ADSP, ADSC Set-up Before CLK Rise 1.5 1.5 1.5 1.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tWES BWE, GW, BWx Set-up Before CLK Rise 1.5 1.5 1.5 1.5 ns tWEH BWE, GW, BWx Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tADVS ADV Set-up Before CLK Rise 1.5 1.5 1.5 1.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tDS Data Input Set-up Before CLK Rise 1.5 1.5 1.5 1.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCES Chip Enable Set-up 1.5 1.5 1.5 1.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 tCHZ Clock to High-Z[16] tCLZ Clock to Low-Z[16] tEOHZ OE HIGH to Output High-Z[16, 17] 0.5 2.3 0.5 2.3 1.5 Low-Z[16, 17] tEOLZ OE LOW to Output tEOV OE LOW to Output Valid[16] 0.5 2.7 0.5 2.3 1.5 2.3 0 0.5 1.5 1.5 ns ns 3.0 0 3.0 ns ns 3.0 3.0 0 2.7 ns 3.5 3.0 2.3 0 2.3 0.5 3.0 ns ns 3.5 ns Notes: 13. Tested initially and after any design or process changes that may affect these parameters. 14. Input waveform should have a slew rate of 1 V/ns. 15.Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b), and (c) of AC Test Loads. 16.tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 17.At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ. Document #: 38-05184 Rev. *B Page 20 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Switching Waveforms Write Cycle Timing[5, 18, 19] Single Write Burst Write Pipelined Write tCH Unselected tCYC CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADH tADS ADSC initiated write ADSC tADVH tADVS ADV tAS ADD ADV Must Be Inactive for ADSP Write WD1 WD3 WD2 tAH GW tWS tWH WE tCES tWH tWS tCEH CE1 masks ADSP CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDH tDS Data In High-Z 1a 1a 2a = UNDEFINED 2b 2c 2d 3a High-Z = DON’T CARE Notes: 18. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table). 19. WDx stands for Write Data to Address X. Document #: 38-05184 Rev. *B Page 21 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Switching Waveforms (continued) Read Cycle Timing[5, 18, 20] Burst Read Single Read tCYC Unselected tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH Suspend Burst ADV tADVH tAS ADD RD1 RD3 RD2 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES OE tEOV tCEH tOEHZ tDOH Data Out tCO 1a 1a 2a 2b 2c 2c 2d 3a tCLZ = DON’T CARE tCHZ = UNDEFINED Note: 20. RDx stands for Read Data from Address X. Document #: 38-05184 Rev. *B Page 22 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Switching Waveforms (continued) Read/Write Cycle Timing[5, 18, 19, 20] Single Read tCYC Single Write Single Write Single cycle deselect Burst Read tCH Pipelined Read CLK tADS tADH tCL ADSP ADSC tADVS ADV tAS ADD tADVH RD1 WD2 WD3 RD4 RD5 tAH GW tWS tWS tWH WE tCES tWH tCEH CE1 Unselected CE1 CE2 tCES tCEH CE3 tCES tCEH tEOV OE tEOHZ Data In/Out tEOLZ tCO 1a 1a Out 2a In tDS = DON’T CARE Document #: 38-05184 Rev. *B 4a Out 3a In = UNDEFINED tDH tDOH 4b Out 4c Out 4d Out tCHZ I/O Disabled within one clock cycle after deselect Page 23 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Switching Waveforms (continued) Pipelined Read/Write Timing[5, 18, 19, 20] Selected ADSP read ADSC read Unselected ADSC write ADSP write CLK ADSP ADSC ADV ADD RD1 RD2 RD3 RD4 WD5 WD6 5a In 6a In WD8 WD7 GW WE CE1 CE2 CE3 OE Data In/Out 1a 1a Out 2a Out 3a Out = DON’T CARE Document #: 38-05184 Rev. *B 4a Out 7a In = UNDEFINED Page 24 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Switching Waveforms (continued) OE Switching Waveforms OE tEOV tEOHZ Three-State I/Os tEOLZ ZZ Mode Timing [5, 21, 22] CLK ADSP HIGH ADSC CE1 CE2 LOW HIGH CE3 ZZ IDD tZZS IDD(active) IDDZZ I/Os tZZREC Three-state Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 22. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05184 Rev. *B Page 25 of 31 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY Ordering Information Speed (MHz) 300 Ordering Code CY7C1440V33-300AC CY7C1446V33-300AC A101 100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial 119-ball BGA (14 x 22 x 2.4 mm) CY7C1446V33-300BX BG209 209-ball FBGA (14 x 22 x 2.2mm) CY7C1440V33-250AC CY7C1446V33-250AC CY7C1446V33-250BX CY7C1440V33-250BZC CY7C1446V33-250BZC CY7C1440V33-200AC CY7C1446V33-200AC BB165C A101 BG119 BG209 BB165C A101 165-ball FBGA (15 x 17 mm) 100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-ball BGA (14 x 22 x 2.4 mm) 209-ball FBGA (14 x 22 x 2.2mm) 165-ball FBGA (15 x 17 mm) 100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack CY7C1440V33-200BGC CY7C1446V33-200BGC BG119 119-ball BGA (14 x 22 x 2.4 mm) CY7C1446V33-200BX BG209 209-ball FBGA (14 x 22 x 2.2mm) CY7C1440V33-200BZC CY7C1446V33-200BZC 167 Operating Range BG119 CY7C1440V33-250BGC CY7C1446V33-250BGC 200 Package Type CY7C1440V33-300BGC CY7C1446V33-300BGC CY7C1440V33-300BZC CY7C1446V33-300BZC 250 Package Name CY7C1440V33-167AC CY7C1446V33-167AC CY7C1440V33-167BGC CY7C1446V33-167BGC CY7C1446V33-167BX CY7C1440V33-167BZC CY7C1446V33-167BZC Document #: 38-05184 Rev. *B BB165C A101 BG119 BG209 BB165C 165-ball FBGA (15 x 17 mm) 100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-ball BGA (14 x 22 x 2.4 mm) 209-ball FBGA (14 x 22 x 2.2mm) 165-ball FBGA (15 x 17 mm) Page 26 of 31 PRELIMINARY CY7C1440V33 CY7C1442V33 CY7C1446V33 Package Diagrams 100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05184 Rev. *B Page 27 of 31 PRELIMINARY CY7C1440V33 CY7C1442V33 CY7C1446V33 Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Document #: 38-05184 Rev. *B Page 28 of 31 PRELIMINARY CY7C1440V33 CY7C1442V33 CY7C1446V33 Package Diagrams (continued) 165-ball FBGA (15 x 17 x 1.20 mm) BB165C 51-85165-** Document #: 38-05184 Rev. *B Page 29 of 31 PRELIMINARY CY7C1440V33 CY7C1442V33 CY7C1446V33 Package Diagrams (continued) 209-Lead PBGA (14 x 22 x 2.20 mm) BG209 51-85143-*B Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05184 Rev. *B Page 30 of 31 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1440V33 CY7C1442V33 CY7C1446V33 Document History Page Document Title: CY7C1440V33/CY7C1442V33/CY7C1446V33 1M x 36/2M x 18/512K x 72 Pipelined SRAM Document Number: 38-05184 REV. ECN No. Issue Date Orig. of Change Description of Change ** 113761 04/11/02 PKS New Data Sheet *A 116916 08/07/02 FLX Correct B11 pin of 165 FBGA package Shaded 300-MHz device information *B 121474 11/14/02 DSG Updated package diagrams 51-85115 (BG119) to rev. *B, 51-85143 (BG209) to rev. *B Document #: 38-05184 Rev. *B Page 31 of 31