CY7C373i UltraLogic™ 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable™ (ISR™) Flash technology — JTAG interface • Bus Hold capabilities on all I/Os and dedicated inputs • No hidden delays • High speed — fMAX = 125 MHz The CY7C373i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C373i is designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. Like all of the UltraLogic™ FLASH370i devices, the CY7C373i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins.The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments. — tPD = 10 ns — tS = 5.5 ns • • • • — tCO = 6.5 ns Fully PCI compliant 3.3V or 5.0V I/O operation Available in 84-pin PLCC and 100-pin TQFP packages Pin compatible with the CY7C374i Logic Block Diagram CLOCK INPUTS INPUT 1 4 INPUT/CLOCK MACROCELLS INPUT MACROCELL 2 2 16 I/Os LOGIC BLOCK A I/O0-I/O15 16 I/Os 36 LOGIC BLOCK B I/O16-I/O31 PIM 36 16 16 36 36 16 16 LOGIC BLOCK D 16 I/Os LOGIC BLOCK C 16 I/Os I/O48−I/O63 I/O32−I/O47 32 32 7C373i–1 Selection Guide 7C373i–83 7C373iL-83 7C373i–66 7C373iL–66 Maximum Propagation Delay, tPD (ns) 7C373i–125 7C373i–100 10 12 15 15 20 20 Minimum Set-up, tS (ns) 5.5 6.0 8 8 10 10 Maximum Clock to Output , tCO (ns) 6.5 6.5 8 8 10 10 Typical Supply Current, ICC (mA) 75 75 75 45 75 45  Note: 1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 10, 2000 CY7C373i Pin Configurations I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 63 I/O 2 I/O 1 I/O 0 VCCINT GND VCCIO ISREN GND I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 PLCC Top View 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 GND I/O55 I/O54 /SDI I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I 4 GND VCCIO CLK2/I 3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 7C373i–3 I/O38/SDO I/O39 GND I/O26 /SMODE I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCCINT GND VCCIO I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 7C373 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O24 I/O25 I/O8 I/O9 I/O10 /SCLK I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I 0 VCCIO GND CLK1/I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 GND NC I/O 63 VCCIO NC GND ISREN I/O 0 VCCINT I/O 4 I/O 3 I/O 2 I/O 1 I/O 7 I/O 6 I/O 5 NC VCCIO TQFP Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 SDO I/O35 I/O36 I/O37 I/O38 I/O39 VCCIO NC GND VCCIO I/O32 I/O33 I/O34 I/O30 I/O31 I2 VCCINT 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SMODE SCLK GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0 /I0 VCCIO N/C GND CLK1 /I1 I/O15 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCCIO NC SDI VCCIO I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3 /I4 GND NC VCCIO CLK2 /I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 GND NC 7C373i–2 CY7C373i Functional Description (continued) Programmable Interconnect Matrix The 64 macrocells in the CY7C373i are divided between four logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The Programmable Interconnect Matrix (PIM) connects the four logic blocks on the CY7C373i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. The logic blocks in the FLASH370i architecture are connected with an extremely fast and predictable routing resource—the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. Programming For an overview of ISR programming, refer to the FLASH370i Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of ISR capabilities, refer to the Cypress application note, “An Introduction to In System Reprogramming with FLASH370i.” Like all members of the FLASH370i family, the CY7C373i is rich in I/O resources. Every macrocell in the device features an associated I/O pin, resulting in 64 I/O pins on the CY7C373i. In addition, there is one dedicated input and four input/clock pins. PCI Compliance The FLASH370i family of CMOS CPLDs are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The simple and predictable timing model of FLASH370i ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without simple and predictable timing, PCI compliance is dependent upon routing and product term distribution. Finally, the CY7C373i features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used or the type of application, the timing parameters on the CY7C373i remain the same. Logic Block 3.3V or 5.0V I/O operation The number of logic blocks distinguishes the members of the FLASH370i family. The CY7C373i includes four logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. The FLASH370i family can be configured to operate in both 3.3V and 5.0V systems. All devices have two sets of VCC pins: one set, V CCINT, for internal operation and input buffers, and another set, VCCIO, for I/O output drivers. VCCINT pins must always be connected to a 5.0V power supply. However, the VCCIO pins may be connected to either a 3.3V or 5.0V power supply, depending on the output requirements. When VCCIO pins are connected to a 5.0V source, the I/O voltage levels are compatible with 5.0V systems. When VCCIO pins are connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay on all output buffers when operating in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is available in commercial and industrial temperature ranges. Product Term Array The product term array in the FLASH370i logic block includes 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex functions to be implemented in single passes through the device. Product Term Allocator The product term allocator is a dynamic, configurable resource that shifts product term resources to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370i CPLDs. Note that the product term allocator is handled by software and is invisible to the user. Bus Hold Capabilities on all I/Os and Dedicated Inputs In addition to ISR capability, a new feature called bus-hold has been added to all FLASH370i I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device’s performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to V CC or GND. I/O Macrocell Each of the macrocells on the CY7C373i has a separate I/O pin associated with it. In other words, each I/O pin is shared by two macrocells. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed, polarity control over the input sum-term, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input. Design Tools Development software for the CY7C371i is available from Cypress’s Warp™, Warp Professional™, and Warp Enterprise™ software packages. Please refer to the data sheets on these products for more details. Cypress also actively supports almost all third-party design tools. Please refer to third-party tool support for further information. 3 CY7C373i Maximum Ratings Static Discharge Voltage ........................................... >2001V (per MIL–STD–883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current ..................................................... >200 mA Storage Temperature ...................................–65°C to +150°C Operating Range Ambient Temperature with Power Applied ...............................................–55°C to +125°C Range Ambient Temperature VCC VCCINT Supply Voltage to Ground Potential ............... –0.5V to +7.0V Commercial 0°C to +70°C 5V ± 0.25V 5V ± 0.25V OR 3.3V ± 0.3V −40°C to +85°C 5V ± 0.5V 5V ± 0.5V OR 3.3V ± 0.3V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Industrial DC Input Voltage............................................ –0.5V to +7.0V DC Program Voltage .....................................................12.5V VCCIO Output Current into Outputs......................................... 16 mA Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min.  Typ. Max. Unit VOH Output HIGH Voltage VCC = Min. IOH = –3.2 mA (Com’l/Ind) VOHZ Output HIGH Voltage with Output Disabled VCC = Max. IOH = 0 µA (Com’l/Ind)[3, 4] 4.0 V IOH = –50 µA (Com’l/Ind) 3.6 V 0.5 V 2.0 7.0 V –0.5 0.8 V –10 +10 µA –50 +50 µA –125 µA –160 mA VOL Output LOW Voltage VIH Input HIGH Voltage 2.4 V [3, 4] VCC = Min.  IOL = 16 mA (Com’l/Ind) Guaranteed Input Logical HIGH Voltage for all Inputs   VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs IIX Input Load Current VI = Internal GND, VI = VCC IOZ Output Leakage Current VCC = Max., VO = GND or VO = VCC, Output Disabled  VCC = Max., VO = 3.3V, Output Disabled IOS Output Short Circuit Current[6, 7] ICC Power Supply Current VCC = Max., IOUT = 0 mA, f = 1 MHz, VIN = GND, VCC 0 VCC = Max., VOUT = 0.5V –70 –30 Com’l/Ind. 75 125 mA Com’l “L”, –66 45 75 mA IBHL Input Bus Hold LOW Sustaining Current VCC = Min., VIL = 0.8V +75 µA IBHH Input Bus Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V –75 µA IBHLO Input Bus Hold LOW Overdrive Current VCC = Max. +500 µA IBHHO Input Bus Hold HIGH Overdrive Current VCC = Max. –500 µA Capacitance Parameter Description Test Conditions CIN Input Capacitance VIN = 5.0V at f = 1 MHz CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz Min. 5 Max. Unit 8 pF 12 pF Notes: 2. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT. 3. IOH = –2 mA, IOL = 2 mA for SDO. 4. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional information. 5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 6. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters. 8. Measured with 16-bit counter programmed into each logic block. 9. CI/O for dedicated Inputs, and I/Os with JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max. 4 CY7C373i Inductance Parameter Description L Test Conditions Maximum Pin Inductance 100-Pin TQFP 84-Lead PLCC Unit 8 8 nH VIN = 5.0V at f = 1 MHz Endurance Characteristics Parameter Description N Maximum Reprogramming Cycles Test Conditions Max. Unit Normal Programming Conditions 100 Cycles AC Test Loads and Waveforms 238Ω (COM'L) 319Ω (MIL) 238Ω (COM'L) 5V OUTPUT 90% OUTPUT 170Ω (COM'L) 5 pF 236Ω (MIL) INCLUDING JIG AND SCOPE 35 pF INCLUDING JIG AND SCOPE (a) Equivalent to: ALL INPUT PULSES 3.0V 5V GND 90% 10% 10% < 2 ns < 2 ns 170Ω (COM'L) (b) (c) 7C373i–4 THÉVENIN EQUIVALENT 99Ω (COM'L) 2.08V(COM'L) OUTPUT Parameter Vx tER(–) 1.5V Output Waveform–Measurement Level V OH tER(+) 2.6V 0.5V V OL tEA(+) VX 0.5V 1.5V 0.5V VX tEA(–) VX V OH Vthe VX V OL 0.5V (d) Test Waveforms Note: 10. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load. 5 7C373i–5 CY7C373i Switching Characteristics Over the Operating Range Parameter Description 7C373i–125 7C373i–100 7C373i–83 7C373iL-83 7C373i–66 7C373iL–66 Min. Min. Min. Min. Max. Max. Max. Max. Unit Combinatorial Mode Parameters tPD Input to Combinatorial Output 10 12 15 20 ns tPDL Input to Output Through Transparent Input or Output Latch 13 15 18 22 ns tPDLL Input to Output Through Transparent Input and Output Latches 15 16 19 24 ns tEA Input to Output Enable 14 16 19 24 ns tER Input to Output Disable 14 16 19 24 ns Input Registered/Latched Mode Parameters tWL Clock or Latch Enable Input LOW Time 3 3 4 5 ns tWH Clock or Latch Enable Input HIGH Time  3 3 4 5 ns tIS Input Register or Latch Set-Up Time 2 2 3 4 ns tIH Input Register or Latch Hold Time 2 2 3 4 ns tICO Input Register Clock or Latch Enable to Combinatorial Output 14 16 19 24 ns tICOL Input Register Clock or Latch Enable to Output Through Transparent Output Latch 16 18 21 26 ns 6.5 6.5 8 10 ns Output Registered/Latched Mode Parameters tCO Clock or Latch Enable to Output tS Set-Up Time from Input to Clock or Latch Enable tH Register or Latch Data Hold Time tCO2 Output Clock or Latch Enable to Output Delay (Through Memory Array) tSCS Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) 8 10 12 15 ns tSL Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable 10 12 15 20 ns tHL Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable 0 0 0 0 ns fMAX1 Maximum Frequency with Internal Feedback (Least of 1/tSCS, 1/(tS + tH), or 1/tCO) 125 100 83 66 MHz fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) 153.8 153.8 125 100 MHz fMAX3 Maximum Frequency of (2) CY7C373is with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH) 83.3 80 62.5 50 MHz tOH–tIH 37x Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[7, 12] 0 0 0 0 ns 5.5 6 8 10 ns 0 0 0 0 ns 14 16 19 24 ns Notes: 11. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 12. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C373i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. 6 CY7C373i Switching Characteristics Over the Operating Range FRQWLQXHG 7C373i–125 7C373i–100 7C373i–83 7C373iL-83 7C373i–66 7C373iL–66 Description Min. Min. Min. Min. tICS Input Register Clock to Output Register Clock 8 10 12 15 ns fMAX4 Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) 125 83.3 66.6 50.0 MHz 10 12 15 20 ns 12 14 17 22 ns Parameter Max. Max. Max. Max. Unit Pipelined Mode Parameters Reset/Preset Parameters tRW tRR tRO tPW tPR tPO Asynchronous Reset Width Asynchronous Reset Recovery Time   Asynchronous Reset to Output Asynchronous Preset Width 16  Asynchronous Preset Recovery Time Asynchronous Preset to Output  18 21 26 ns 10 12 15 20 ns 12 14 17 22 ns  16 18 21 26 ns Tap Controller Parameter fTAP Tap Controller Frequency 500 500 500 500 kHz 3.3V I/O Mode Parameters t3.3IO 3.3V I/O mode timing adder 1 1 1 1 ns Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT 7C373i–6 Registered Output INPUT tH tS CLOCK tCO REGISTERED OUTPUT tWL tWH CLOCK 7C373i–7 7 CY7C373i Switching Waveforms (continued) Latched Output INPUT tS tH LATCH ENABLE tPDL tCO LATCHED OUTPUT 7C373i–8 Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK tICS tSCS OUTPUT REGISTER CLOCK 7C373i–10 Latched Input LATCHED INPUT tIS tIH LATCH ENABLE tPDL tICO COMBINATORIAL OUTPUT tWH tWL LATCH ENABLE 7C373i–11 8 CY7C373i Switching Waveforms (continued) Latched Input and Output LATCHED INPUT tPDLL LATCHED OUTPUT tICOL tSL tHL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tWH tWL LATCH ENABLE 7C373i–12 Asynchronous Reset tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK 7C373i–13 Asynchronous Preset tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK 7C373i–14 9 CY7C373i Switching Waveforms (continued) Output Enable/Disable INPUT tEA tER OUTPUTS 7C373i–16 Ordering Information Speed (MHz) 125 100 83 66 Ordering Code Package Type Package Type 100-Pin Thin Quad Flatpack Operating Range CY7C373i–125AC A100 CY7C373i–125JC J83 Commercial CY7C373i–100AC A100 CY7C373i–100JC J83 CY7C373i–100AI A100 CY7C373i–100JI J83 CY7C373i–83AC A100 CY7C373i–83JC J83 CY7C373i–83AI A100 CY7C373i–83JI J83 84-Lead Plastic Leaded Chip Carrier CY7C373iL–83JC J83 84-Lead Plastic Leaded Chip Carrier Commercial CY7C373i–66AC A100 100-Pin Thin Quad Flatpack Commercial 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack Commercial 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack Industrial 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack Commercial 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack CY7C373i–66JC J83 CY7C373i–66AI A100 CY7C373i–66JI J83 84-Lead Plastic Leaded Chip Carrier CY7C373iL–66JC J83 84-Lead Plastic Leaded Chip Carrier Industrial 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack Industrial Commercial Document #: 38-00495-F FLASH370, FLASH370i, ISR, UltraLogic, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor Corporation. 10 CY7C373i Package Diagrams 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-B 11 CY7C373i Package Diagrams 84-Lead Plastic Leaded Chip Carrier J83 51-85006-A © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.