DS1073 Special EconOscillator/Divider www.maxim-ic.com FEATURES § § § § § § § Dual Fixed frequency outputs (29.2 kHz to 100 MHz) No external components 0.5% Initial tolerance 1% variation over temperature and voltage Single 2.7Vto 3.6V supply Power-down mode Synchronous output gating OUT1 1 8 DNC OUT0 2 7 DNC VCC 3 6 OE GND 4 5 PDN DS1073Z 150-MIL SOIC DS1073M 300-MIL DIP DESCRIPTION The DS1073 Special is a fixed frequency oscillator requiring no external components for operation. Numerous set operating frequencies are possible in the range 29.2 kHz to 100 MHz. The DS1073 Special is shipped from the factory pre-programmed to a specific output frequency and mode of operation. The part is branded according to the device’s master frequency (see DS1073 data sheet). The customer fills out a “1073 Special Order Form” with the required information and submits it to the factory for approval. Contact the factory for availability of specific frequencies. In general, any frequency possible on a standard DS1073 can be made available. The DS1073 special is available in 8-pin DIP or SOIC packages, allowing the generation of a clock signal easily, economically and using minimal board area. 1 of 12 111802 DS1073 BLOCK DIAGRAM Figure 1 Master Oscillator 60-100MHz Prescaler Divide by M 1, 2, 4 Power Down Control Divider Divide by N 1-513 OUT0 (Optional) (Reference) OUT1 PDN OE 2 of 12 DS1073 1073 SPECIAL Order Form Use this form for DS1073 Special programmed EconOscillators . All sections must be completed. Refer to the datasheet or contact the factory at (972) 371-6822 for assistance. Parent Part Number: DS1073 Customer Name: _______________________________________________________________ Customer Contact: _____________________________________________________________ Customer Address: _____________________________________________________________ _____________________________________________________________________________ Customer Phone: (Area) _____ _____ ________ Salesman: ____________________________________________________________________ Sales Representative: ___________________________________________________________ Distributor (if any): ____________________________________________________________ Package: 300mil 8-pin DIP Parent Device: 150mil 8-pin SOIC (circle one) DS ________________ ( part will be branded with this speed) Master Frequency: _________ MHz Reference Output: Disabled Output Frequency: _________ Prescaler (M) : Standard or Special (circle one) (60,66,80 or 100MHz) Enabled - Frequency _________ (Equals master frequency/M) (Equals master frequency/MN) _________ Divider (N): _________ Special Instructions (Tape & Reel, etc.): _____________________________________________________________________________ _____________________________________________________________________________ _____________________________________________________________________________ _____________________________________________________________________________ _____________________________________________________________________________ Customer Signature: _____________________________________ (acknowledges acceptance of special settings) Fax the completed form to Louis Grantham at (972) 371-4799 (FAX). 3 of 12 DS1073 PIN DESCRIPTIONS Output Pin (OUT1 pin): This pin is the main oscillator output. Output Enable Function (OE pin): The DS1073 Special features a “synchronous” output enable. When OE is at a high logic level the oscillator free runs. When this pin is taken low OUT1 is held low, immediately if OUT1 is already low, or at the next high-to-low transition if OUT1 is high. This prevents any possible truncation of the output pulse width when the enable is used. While the output is disabled the master oscillator continues to run (producing an output at OUT0, if the EN0 bit = 0) but the internal counters (/N) are reset. This results in a constant phase relationship between OE’s return to a high level and the resulting OUT1 signal. When the enable is released OUT1 will make its first transition within one to two clock periods of the master clock. Power-Down ( PDN pin): A low logic level on this pin can be used to make the device stop oscillating (active low) and go into a reduced power consumption state. Internal “Enabling Sequencer” circuitry will first disable OUT in the same way as when OE is used. Next OUT0 will be disabled in a similar fashion. Finally the oscillator circuitry will be disabled. In this mode both outputs will go into a high impedance state. The power consumption in the power-down state is much less than if OE is used because the internal oscillator is completely powered down. Consequently the device will take considerably longer to recover (i.e., achieve stable oscillation) from a power-down condition than if the OE is used. Reference Output (OUT0 pin): A reference output, OUT0, is also available from the output of the prescaler. OUT0 is unaffected by the OE pin, but is disabled in a glitchless fashion if the device is powered down. If this output is not required it can be permanently disabled and there will be a corresponding reduction in overall power consumption. The availability of this output and its frequency are specified on the special order form. DNC: Do not connect. OPERATION OF OUTPUT ENABLE Since the output enable and internal master oscillator are asynchronous there is the possibility of timing difficulties in the application. To minimize these difficulties the DS1073 features an “enabling sequencer” to produce predictable results when the device is enabled and disabled. In particular the output gating is configured so that truncated output pulses can never be produced. ENABLE TIMING The output enable function is produced by sampling the OE input with the output from the pre-scaler mux (MCLK) and gating this with the output from the programmable divider. The exact behavior of the device is therefore dependent on the setup time (tSU) from a transition on the OE input to the rising edge of MCLK. If the actual setup time is less than TSUEM then one more complete cycle of MCLK will be required to complete the enable or disable operation (see diagrams). This is unlikely to be of any consequence in most applications, and then only if the value for N is small. In general, the output will make its first positive transition between approximately one and two clock periods of MCLK after the rising edge of OE. (Figure 2) 4 of 12 DS1073 Figure 2 Disable Timing If OE goes low while OUT1 is high, the output will be disabled on the completion of the output pulse. If OUT1 is low, the disabling behavior will be dependent on the setup time between the falling edge of OE and the rising edge of MCLK. If tSU < TSUEM the result will be one additional pulse appearing on the output before disabling occurs. If the device is in divide-by-one mode, the disabling occurs slightly differently. In this case if tSU > TSUEM one additional output pulse will appear, if tSU < TSUEM then two additional output pulses will appear. The following diagrams illustrate the timing in each of these cases. (Figure 3 and 4) Figure 3 Figure 4 5 of 12 DS1073 POWER-DOWN CONTROL POWER-DOWN If PDN is taken low a power-down sequence is initiated. The “Enabling Sequencer” is used to execute events in the following sequence: 1. Disable OUT1 (same sequence as when OE is used) and reset N counters. 2. When OUT1 is low, switch OUT1 to high-impedance state. 3. Disable MCLK, switch OUT0 to high impedance state. 4. Disable master oscillator. POWER-UP When PDN is taken to a high level the following power-up sequence occurs: 1. Enable internal oscillator. 2. Set M and N to maximum values. 3. Wait approximately 256 cycles of MCLK for it to stabilize. 4. Reset M and N to programmed values. 5. Enable OUT0 ( if enabled) 6. Enable OUT1. Steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs. Figure 5 6 of 12 DS1073 POWER-ON RESET When power is initially applied to the device supply pin, a power-on reset sequence is executed, similar to that which occurs when the device is restored from a power-down condition. This sequence comprises two stages, first a conventional POR to initialize all on-chip circuitry, followed by a stabilization period to allow the oscillator to reach a stable frequency before enabling the outputs: 1. Initialize internal circuitry. 2. Enable internal oscillator. 3. Set M and N to maximum values. 4. Wait approximately 256 cycles of MCLK for the oscillator to stabilize. 5. Load M and N programmed values from EEPROM. 6. Enable OUT0 (if enabled). 7. Enable OUT1. Figure 6 7 of 12 DS1073 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -1.0V to +7.0V 0°C to 70°C -55°C to +125°C See J-STD-020A Specification * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C) (VCC =2.7V to 3.6V) PARAMETER Supply Voltage High-level Output Voltage (OUT1, OUT0) Low-level Output Voltage (OUT1, OUT0) High-level Input Voltage Low-level Input Voltage High-level Input Current ( PDN , OE) Low-level Input Current ( PDN , OE) Supply Current (Active) DS1073-100 DS1073-80 DS1073-66 DS1073-60 Standby Current (power-down) SYMBOL VCC VOH VOL CONDITION IOH = -2 mA, VCC = MIN IOL = 2 mA VIH VIL MIN 2.7 2.4 TYP MAX UNITS 3.6 V V 0.4 V 0.8 V V 1 uA 2 IIH VIH =2.4V,VCC = 3.6V IIL VIL=0,VCC=3.6V ICC CL = 15 pF (both outputs) 25 ICCQ Power-Down Mode 0.8 8 of 12 -1 uA 40 uA uA NOTE DS1073 AC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C) (VCC =2.7V to 3.6V) PARAMETER Output Frequency Accuracy SYMBOL fO CONDITION VCC = 3.15V, TA =25°C Over temp and voltage MIN TYP -0.5 0 +0.5 % -1 +1 % +0.5 % Combined Freq. Variation DfO Long Term Stability Minimum Output Frequency Power-Up Time Enable OUT1 from PDN ↑ Enable OUT0 from PDN ↑ OUT1 Hi-Z from PDN ↓ OUT0 Hi-Z from PDN ↓ Load Capacitance (OUT1, OUT0) Output Duty Cycle OUT1 OUT0 DfO -0.5 fOUT 29.3 T Setup Enable MCLK Jitter MAX UNITS tPOR+tSTAB tSTAB tSTAB tPDN tPDNd 0.1 0.1 0.1 CL 15 1 1 1 1 1 40 40 TSUEM J kHz 1 ms ms ms ms ms 2,3 3 3,4 pF 5 60 60 % % 20 ns 100 pS MCLK=100 MHz NOTES 6 NOTES: 1. The values of M and N must be chosen so that this specification is met. 2. This is the time from when VCC is applied until the output starts oscillating. 3. When the device is initially powered up, or restored from the power-down mode, OE should be asserted (high). Otherwise the start of the tstab interval will be delayed until OE goes high. OE can subsequently be returned to a low level during the tstab interval to force out low after the tstab, interval. If the external mode is selected tstab will be a function of the OSCIN period, i.e., external clock frequency. See “Calculated Parameters” to determine the value of tstab in this case. 4. Although OE does not normally affect OUT0 operation, if OE is held low during power-up the start of the tstab period will be delayed until OE is asserted. If OE remains low, OUT0 will not start. 5. Operation with higher capacitive loads is possible but may impair output voltage swing and maximum operation frequency. 6. Parameter given is a typical at 3 sigma. 9 of 12 DS1073 AC ELECTRICAL CHARACTERISTICS – CALCULATED PARAMETERS The following characteristics are derived from various device operating parameters (frequency, mode etc.). They are not specifically tested or guaranteed and may differ from the min and max limits shown by a small amount due to internal device setup times and propagation delays. However, the equations in the max column can be used to estimate a more accurate idea of typical device performance than the guaranteed values. PARAMETER OUT1 ↑ from OE ↑ OUT1 ↓ from OE ↓ N=1 N≥2 PDN ↓ to OUT1 Hi-Z N=1 N≥2 PDN ↓ to OUT0 Hi-Z N=1 N≥2 PDN ↑ to OUT1 ↑ PDN ↑ to OUT0 ↑ OUT1 ↑ after Power-up OUT0 ↑ after Power-up SYMBOL tEN tDIS tDIS CONDITION MIN tM tOUTH 0 MAX 2tM tOUTH + tM tOUTH tPDN tPDN tOUTH 0 tOUTH + tM tOUTH tPDN tPDN tOUTH 0 tOUTH + tM tOUTH tSTAB tSTAB 256tM 256tM 256tM 256tM 10 of 12 DS1073 DC ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C) (Vcc =2.7V to 3.6V) PARAMETER Supply Voltage High-level Output Voltage (OUT1, OUT0) Low-level Output Voltage (OUT1, OUT0) High-level Input Voltage Low-level Input Voltage High-level Input Current ( PDN , OE) Low-level Input Current( PDN ,OE) Supply Current (Active) DS1073-100 DS1073-80 DS1073-66 DS1073-60 Standby Current (power-down) SYMBOL VCC VOH VOL CONDITION IOH = -2 mA, VCC = MIN IOL = 2 mA VIH VIL MIN 2.7 2.4 TYP MAX UNITS 3.6 V V 0.4 V 0.8 V V 1 uA 2 IIH VIH =2.4V,VCC = 3.6V IIL VIL=0,VCC=3.6V ICC CL = 15 pF (both outputs) 25 ICCQ Power-Down Mode 0.8 11 of 12 -1 uA 50 mA uA NOTE DS1073 AC ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C) (VCC =3.15V ± 10%) PARAMETER Output Frequency Accuracy SYMBOL fO CONDITION VCC = 3.15V, TA =25°C Over temp and voltage MIN TYP -0.5 0 +0.5 % -2.5% 2.5% % +0.5 % Combined Freq. Variation DfO Long Term Stability Minimum Output Frequency Power-Up Time Enable OUT from PDN ↑ Enable OUT0 from PDN ↑ OUT Hi-Z from PDN ↓ OUT0 Hi-Z from PDN ↓ Load Capacitance (IN/OUT, OUT0) Output Duty Cycle IN/OUT OUT0 DfO -0.5 fOUT 29.3 T Setup Enable Master Jitter tPOR+tSTAB tSTAB tSTAB tPDN tPDN 0.1 0.1 0.1 CL 15 40 40 TSUEM MAX UNIT S MCLK=100 MHz J 1 1 1 1 1 NOTE S kHz 1 ms ms ms ms ms 2.3 3 3,4 pF 5 60 60 % % 20 ns 100 pS 6 NOTES: 1. The values of M and N must be chosen so that this specification is met. 2. This is the time from when VCC is applied until the output starts oscillating. 3. When the device is initially powered up or restored from the power-down mode, OE should be asserted (high). Otherwise the start of the tSTAB interval will be delayed until OE goes high. OE can subsequently be returned to a low level during the tSTAB interval to force out low after the tSTAB interval. If the external mode is selected, tSTAB will be a function of the OSCIN period, i.e. external clock frequency. See “Calculated Parameters” to determine the value of tSTAB in this case. 4. Although OE does not normally affect OUT0 operation, if OE is held low during power-up, the start of the tSTAB period will be delayed until OE is asserted. If OE remains low, OUT0 will not start. 5. Operation with higher capacitive loads is possible but may impair output voltage swing and maximum operation frequency. 6. Parameter given is typical at 3 sigma. 12 of 12