ETC HY57V28820ALT

HY57V28820A
Revision History
Revision 1.1 (Dec. 2000)
•
•
Eleminated -10 Bining product.
Changed DC Characteristics-ll.
- tCK
to 15ns from min in Test condition
- -K IDD1
to 120mA from 110mA
- -K IDD4 CL2 to 120mA from 100mA.
- -K IDD5
to 240mA from 220mA.
- -S IDD4 CL2 to 90mA from 100mA
• Added Burst-Read-Single-Write commend in Commend Truth Table
1.2 : Hynix Change
1.3 : Burst read single write mode correction
Rev. 1.3/Aug. 01
1
HY57V28820A
4Banks x 4M x 8bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V28820A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V28820A is organized as 4banks of 4,194,304x8.
HY57V28820A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.3±0.3V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4, 8 or Full Page for Sequential Burst
•
Data mask function by DQM
•
Internal four banks operation
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V28820AT-6
166MHz
HY57V28820AT-K
133MHz
HY57V28820AT-H
133MHz
HY57V28820AT-8
125MHz
HY57V28820AT-P
100MHz
HY57V28820AT-S
100MHz
HY57V28820ALT-6
166MHz
HY57V28820ALT-K
133MHz
HY57V28820ALT-H
133MHz
HY57V28820ALT-8
125MHz
HY57V28820ALT-P
100MHz
HY57V28820ALT-S
100MHz
Power
Organization
Interface
Package
4Banks x 4Mbits
x8
LVTTL
400mil 54pin TSOP II
Normal
Low power
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.3/Aug. 01
HY57V28820A
PIN CONFIGURATION
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe, Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ7
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
Rev. 1.3/Aug. 01
HY57V28820A
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 8 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
4Mx8 Bank3
CLK
Row active
Column
Pre
Decoders
DQM
Y decoders
Bank Select
A0
A1
Column Add
Counter
Address
Registers
Address buffers
A11
BA0
BA1
Rev. 1.3/Aug. 01
Burst
Counter
Mode Registers
CAS Latency
Data Out Control
Pipe Line Control
DQ0
I/O Buffer & Logic
Column
Active
Memory
Cell
Array
Sense AMP & I/O Gate
WE
X decoders
refresh
4Mx8 Bank 0
X decoders
CAS
4Mx8 Bank 1
X decoders
RAS
State Machine
CS
4Mx8 Bank 2
X decoders
CKE
Row
Pre
Decoders
DQ1
DQ6
DQ7
HY57V28820A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
1
Input High voltage
VIH
2.0
3.0
VDDQ + 0.3
V
1,2
Input Low voltage
VIL
-0.3
0
0.8
V
1,3
Note
Note :
1.All voltages are referenced to VSS = 0V
2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
AC Input High / Low Level Voltage
VIH / VIL
2.4/0.4
V
Vtrip
1.4
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Voutref
1.4
V
CL
50
pF
Input Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
1
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 1.3/Aug. 01
HY57V28820A
CAPACITANCE (TA=25°C, f=1MHz)
-6/K/H
Parameter
Pin
Input Capacitance
Data Input / Output Capacitance
-8/P/S
Symbol
Unit
Min.
Max.
Min.
Max.
CLK
CI1
2.5
3.5
2.5
4
pF
A0 ~ A11, BA0, BA1, CKE,
CS, RAS, CAS, WE, DQM
CI2
2.5
3.8
2.5
5
pF
DQ0 ~ DQ7
CI/O
4
6.5
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC O utput Load Circuit
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-1
1
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -4mA
Output Low Voltage
VOL
-
0.4
V
IOL =+4mA
Note :
1.VIN = 0 to 3.6V, All other pins are not under test = 0V
2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 1.3/Aug. 01
HY57V28820A
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Speed
Parameter
Symbol
Test Condition
-6
-K
-H
-8
-P
-S
120
120
110
100
100
100
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
IDD2P
CKE ≤ VIL(max), tCK = 15ns
2
IDD2PS
CKE ≤ VIL(max), tCK = ∞
2
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
20
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
10
IDD3P
CKE ≤ VIL(max), tCK = 15ns
7
IDD3PS
CKE ≤ VIL(max), tCK = ∞
7
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
40
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
40
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
Operating Current
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
Note
mA
1
mA
mA
mA
mA
CL=3
140
120
120
110
100
100
CL=2
100
120
100
100
100
90
240
240
220
200
200
200
mA
1
mA
2
2
mA
3
800
uA
4
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2.Min. of tRRC (Refresh RAS cycle time) is applied to HY57V28820AT-6/K/H/8/P/S which are listed on AC characteristic II.
3.HY57V28820AT-6/K/H/8/P/S
4.HY57V28820ALT-6/K/H/8/P/S
Rev. 1.3/Aug. 01
Unit
HY57V28820A
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-6
Parameter
CAS Latency = 3
tCK3
Max
6
Min
Max
7.5
1000
-8
-P
-S
Min
Max
Min
7.5
1000
8
1000
10
Min
Max
10
1000
10
Min
10
1000
ns
1000
Clock High Pulse Width
tCHW
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Clock Low Pulse Width
tCLW
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
CAS Latency = 3
tAC3
-
5.4
-
5.4
-
5.4
-
6
-
6
-
6
ns
CAS Latency = 2
tAC2
-
6
-
5.4
-
6
-
6
-
6
-
6
ns
Data-Out Hold Time
tOH
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CKE Setup Time
tCKS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
CKE Hold Time
tCKH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Command Setup Time
tCS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1
-
1
-
1
-
1
-
1
-
1
-
ns
12
ns
2
CAS Latency = 3
tOHZ3
2.7
5.4
2.7
5.4
2.7
5.4
3
6
3
6
3
6
ns
CAS Latency = 2
tOHZ2
2.7
5.4
2.7
5.4
3
6
3
6
3
6
3
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 1.3/Aug. 01
10
Note
Max
10
CLK to Data
Output in High-Z
Time
7.5
Max
tCK2
Access Time
From Clock
CAS Latency = 2
-H
Unit
Min
System Clock
Cycle Time
-K
Symbol
HY57V28820A
AC CHARACTERISTICS II
-6
Parameter
-K
-H
-8
-P
-S
-10
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Operation
tRC
60
-
60
-
65
-
68
-
70
-
70
-
80
-
ns
Auto Refresh
tRRC
60
-
60
-
65
-
68
-
70
-
70
-
96
-
ns
RAS to CAS Delay
tRCD
18
-
15
-
20
-
20
-
20
-
20
-
30
-
ns
RAS Active Time
tRAS
42
100K
45
100K
45
100K
48
100K
50
100K
50
100K
50
100K
ns
RAS Precharge Time
tRP
18
-
15
-
20
-
20
-
20
-
20
-
30
-
ns
RAS to RAS Bank Active Delay
tRRD
12
-
15
-
15
-
16
-
20
-
20
-
20
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-In to Precharge Command
tDPL
2
-
2
-
2
-
1
-
1
-
1
-
1
-
CLK
Data-In to Active Command
tDAL
5
-
4
-
5
-
4
-
3
-
3
-
4
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
CAS Latency = 3
tPROZ3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
CAS Latency = 2
tPROZ2
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
tPDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
Note
RAS Cycle Time
Precharge to Data
Output Hi-Z
Note :
1. A new command can be given tRRC after self refresh exit.
Rev. 1.3/Aug. 01
1
HY57V28820A
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
(V)
100MHz
Min
100MHz
Max
66MHz
Min
I (mA)
I (mA)
I (mA)
3.45
-2.4
3.3
-27.3
0
0.5
1
1.5
2
2.5
3
3.5
3
3.5
0
-100
-200
3.0
0.0
-74.1
-0.7
2.6
-21.1
-129.2
-7.5
2.4
-34.1
-153.3
-13.3
2.0
-58.7
-197.0
-27.5
1.8
-67.3
-226.2
-35.5
1.65
-73.0
-248.0
-41.1
1.5
-77.9
-269.7
-47.9
1.4
-80.8
-284.3
-52.4
1.0
-88.6
-344.5
-72.5
0.0
-93.0
-502.4
-93.0
I (mA)
Voltage
66MHz and 100MHz Pull-up
-300
-400
-500
-600
Voltage (V)
Ioh Min (100MHz)
Ioh Min (66MHz)
Ioh Min (66 and 100MHz)
IOL Characteristics (Pull-down)
66MHz and 100MHz Pull-down
100MHz
Min
100MHz
Max
66MHz
Min
250
(V)
I (mA)
I (mA)
I (mA)
200
0.0
0.0
0.0
0.0
0.4
27.5
70.2
17.7
0.65
41.8
107.5
26.9
0.85
51.6
133.8
33.3
1.0
58.0
151.2
37.6
1.4
70.7
187.7
46.6
1.5
72.9
194.4
48.0
1.65
75.4
202.5
49.5
1.8
77.0
208.6
50.7
1.95
77.6
212.0
51.5
3.0
80.3
219.6
54.2
3.45
81.4
222.6
54.9
Rev. 1.3/Aug. 01
I (mA)
Voltage
150
100
50
0
0
0.5
1
1.5
2
Voltage (V)
2.5
I (mA) 100 min
I (mA) 66 min
I (mA) 100 max
HY57V28820A
Minimum VDD clamp current
VDD Clamp @ CLK, CKE, CS, DQM & DQ
I(mA)
0.0
0.0
0.2
0.0
0.4
0.0
0.6
0.0
0.7
0.0
0.8
0.0
0.9
0.0
1.0
0.23
1.2
1.34
1.4
3.02
1.6
5.06
1.8
7.35
2.0
9.83
2.2
12.48
2.4
15.30
2.6
18.31
(Referenced to VDD)
20
15
mA
VDD (V)
10
5
0
0
1
Minimum VSS clamp current
-57.23
-2.4
-45.77
-2.2
-38.26
-2.0
-31.22
-1.8
-24.58
-1.6
-18.37
-1.4
-12.56
-1.2
-7.57
-1.0
-3.37
-0.9
-1.75
-0.8
-0.58
-0.7
-0.05
-0.6
0.0
-0.4
0.0
-0.2
0.0
0.0
0.0
Rev. 1.3/Aug. 01
-3
-2.5
-2
-1.5
0
-10
-20
mA
I (mA)
-2.6
3
I (mA)
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V)
2
Voltage
-30
-40
-50
-60
Voltage
I (mA)
-1
-0.5
0
HY57V28820A
DEVICE OPERATING OPTION TABLE
HY57V28820A(L)T-6
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
3CLKs
7CLKs
6CLKs
6CLKs
10CLKs
9CLKs
9CLKs
3CLKs
3CLKs
3CLKs
5.4ns
5.4ns
5.4ns
2.7ns
2.7ns
2.7ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
125MHz(8ns)
2CLKs
3CLKs
2CLKs
3CLKs
6CLKs
6CLKs
8CLKs
9CLKs
2CLKs
3CLKs
5.4ns
6ns
2.7ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
166MHz(6ns)
143MHz(7ns)
133MHz(7.5ns)
HY57V28820A(L)T-K
133MHz(7.5ns)
HY57V28820A(L)T-H
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
6ns
6ns
2.7ns
3ns
3ns
HY57V28820A(L)T-8
125MHz(8ns)
100MHz(10ns)
83MHz(12ns)
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
2CLKs
2CLKs
3CLKs
2CLKs
2CLKs
6CLKs
5CLKs
4CLKs
9CLKs
7CLKs
6CLKs
3CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HY57V28820A(L)T-P
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
HY57V28820A(L)T-S
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
Rev. 1.3/Aug. 01
HY57V28820A
COMMAND TRUTH TABLE
Command
A10/
AP
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
ADDR
RA
Read
1
L
V
H
Write
L
H
X
L
H
L
L
X
CA
Write with Autoprecharge
H
X
L
L
H
L
X
Precharge selected Bank
Burst Stop
H
DQM
H
Auto Refresh
H
H
L
L
L
Burst-Read-SingleWRITE
H
X
L
L
Entry
H
L
L
X
H
Exit
L
H
H
L
H
H
L
X
L
V
X
V
X
H
X
X
L
L
X
A9 Pin High
(Other Pins OP code)
L
L
H
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge
power down
H
X
X
X
Self Refresh
Entry
V
H
Precharge All Banks
X
X
Exit
Entry
Exit
L
H
L
H
X
L
H
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Dont care, H = Logic High, L= Logic Low, BA=Bank Address, RA = Row Address, CA = Column Address,
Opcode=Operand Code, NOP=No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Rev. 1.3/Aug. 01
Note
V
CA
Read with Autoprecharge
Clock
Suspend
BA
3
HY57V28820A
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
Unit : mm(inch)
Rev. 1.3/Aug. 01