HY57V561620T 4Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V561620 is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16. HY57V561620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • Single 3.3V ± 0.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 8192 refresh cycles / 64ms • JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch • Programmable Burst Length and Burst Type • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4, 8 and Full Page for Sequential Burst • Data mask function by UDQM and LDQM • Internal four banks operation - 1, 2, 4 and 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency HY57V561620T-H 133MHz HY57V561620T-8 125MHz HY57V561620T-S 100MHz HY57V561620T-10 100MHz Power Organization Interface Package Normal 4Banks x 4Mbits x16 LVTTL 400mil 54pin TSOP II This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.5 / May.00 HY57V561620T PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54pin TSOP II 400mil x 875mil 0.8mm pin pitch VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 PIN DESCRIPTION PIN PIN NAME DESCRIPTION CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select Enables or disables all inputs except CLK, CKE, UDQM and LDQM BA0, BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A12 Address Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details UDQM, LDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers NC No Connection No connection Revision 1.5 / May.00 2 HY57V561620T FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x16 I/O Synchronous DRAM Self Refresh Logic & Timer Internal Row Counter 4Mx16 Bank 3 CLK Row Active Column Active Column Pre Decoders UDQM Y decoders LDQM Bank Select A0 A1 Revision 1.5 / May.00 DQ1 DQ14 DQ15 Column Add Counter Address Register Address buffers A12 BA0 BA1 Memory Cell Array DQ0 I/O Buffer & Logic WE 4Mx16 Bank 0 X decoders CAS 4Mx16 Bank 1 Sense AMP & I/O Gate RAS 4Mx16 Bank 2 State Machine CS Row Pre Decoders X decoders X decoders CKE Burst Counter Mode Registers CAS Latency Data Out Control Pipe Line Control 3 HY57V561620T ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70°C) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1 Input High Voltage VIH 2.0 3.0 VDDQ + 2.0 V 1,2 Input Low Voltage VIL VSSQ-2.0 0 0.8 V 1,3 Note : 1. All voltages are referenced to VSS = 0V 2. VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration 3. VIL (max) is acceptable -2.0V AC pulse width with ≤3ns of duration AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V) Parameter Symbol Value Unit AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V Vtrip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voutref 1.4 V CL 50 pF Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Note 1 Note : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit Revision 1.5 / May.00 4 HY57V561620T CAPACITANCE (TA=25°C, f=1MHz) -H Parameter Pin Input capacitance Data input / output capacitance -8/S/10 Symbol Unit Min Max Min Max CLK C I1 2.5 3.5 2.5 4.0 pF A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM CI2 2.5 3.8 2.5 5.0 pF DQ0 ~ DQ15 CI/O 4.0 6.5 4.0 6.5 pF OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output Output 50pF 50pF DC Output Load Circuit DC CHARACTERISTICS I Parameter AC Output Load Circuit (TA=0 to 70°C, VDD=3.3±0.3V) Symbol Min. Max Unit Note Input leakage current ILI -1 1 uA 1 Output leakage current ILO -1 1 uA 2 Output high voltage VOH 2.4 - V IOH = -4mA Output low voltage VOL - 0.4 V IOL =+4mA Note : 1. VIN = 0 to 3.6V, All other pins are not under test = 0V 2. DOUT is disabled, VOUT=0 to 3.6V Revision 1.5 / May.00 5 HY57V561620T DC CHARACTERISTICS II (TA=0°C to 70°C, VDD=3.3V ± 0.3V, VSS=0V) Speed Parameter Symbol Test Condition -H -8 -S -10 120 110 100 100 Unit Note mA 1 IDD1 Burst Length=1, One bank active tRAS ≥ tRAS(min),tRP ≥ tRP(min), IO=0mA IDD2P CKE ≤ VIL(max), tCK = min. 2 IDD2PS CKE ≤ VIL(max), tCK = ∞ 2 IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 20 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 10 IDD3P CKE ≤ VIL(max), tCK = min 3 IDD3PS CKE ≤ VIL(max), tCK = ∞ 3 IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 25 IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable 15 Burst Mode Operating Current IDD4 tCK ≥ tCK(min), tRAS ≥ tRAS(min), IO=0mA All banks active 150 140 120 120 mA 1 Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active 260 260 250 250 mA 2 mA 3 IDD6 CKE ≤ 0.2V 4 Self Refresh Current 2 mA 4 Operating Current Precharge Standby Current in power down mode Precharge Standby Current in non power down mode Active Standby Current in power down mode Active Standby Current in non power down mode mA mA mA mA Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY57V561620T-H/8/S/10 Revision 1.5 / May.00 6 HY57V561620T AC CHARACTERISTICS I -H Parameter CAS Latency = 3 tCK3 Max 7.5 Min Max 8 1000 CAS Latency = 2 -S -10 Unit Min System clock cycle time -8 Symbol Min Max 10 1000 10 1000 ns 1000 12 Clock high pulse width tCHW 2.5 - 3 - 3 - 3 - ns 1 Clock low pulse width tCLW 2.5 - 3 - 3 - 3 - ns 1 CAS Latency = 3 tAC3 - 5.4 - 6 6 - 8 ns CAS Latency = 2 tAC2 - 6 - 6 6 - 8 ns Data-out hold time tOH 2.7 - 3 - 3 - 3 - ns Data-Input setup time tDS 1.5 - 2 - 2 - 2.5 - ns 1 Data-Input hold time tDH 0.8 - 1 - 1 - 1.5 - ns 1 Address setup time tAS 1.5 - 2 - 2 - 2.5 - ns 1 Address hold time tAH 0.8 - 1 - 1 - 1.5 - ns 1 CKE setup time tCKS 1.5 - 2 - 2 - 2.5 - ns 1 CKE hold time tCKH 0.8 - 1 - 1 - 1.5 - ns 1 Command setup time tCS 1.5 - 2 - 2 - 2.5 - ns 1 Command hold time tCH 0.8 - 1 - 1 - 1.5 - ns 1 CLK to data output in low Z-time tOLZ 1 - 1 - 1 - 1 - ns CLK to data output in high Z-time 12 Note Max tCK2 Access time from clock 12 Min 12 ns 2 CAS Latency = 3 tOHZ3 2.7 5.4 3 6 3 6 3 8 ns CAS Latency = 2 tOHZ2 3 6 3 6 3 6 3 8 ns Note : 1. Assume tR / tF (input rise and fall time ) is 1ns. 2. Access times to be measured with input signals of 1v/ns slew rate, 0.8v to 2.0v Revision 1.5 / May.00 7 HY57V561620T -H -S -10 Symbol tRC Note Min Min Max Max Min 65 68 - - 80 ns RAS cycle time Auto Refresh RAS to CAS delay 65 - - 70 80 - tRCD - 20 20 - - ns active time tRAS 100K 48 50 100K 100K ns precharge time tRP - 20 20 - - ns to RAS tRRD CAS delay 1 Write command to data-in delay tWTL tDPL Data-in to active command MRS to new command - 2 tDQZ tDQM 16 - 5 DQM to data-out Hi-Z Precharge to data output Hi-Z 15 0 - 0 2 - 2 - - - 2 - 1 0 - 0 - - 4 - 1 - 2 20 2 - 2 - 5 - ns CLK - 0 2 CLK CLK CLK - Latency = 3 tPROZ3 - 3 3 - - CLK Latency = 2 tPROZ2 - - 2 - - CLK tPDE 1 1 - - 1 CLK Self refresh exit time 1 - - 1 1 - Refresh Time - 64 64 - - 64 1 Note : 1. A new command can be given tRRC after self refresh exit. Revision 1.5 / May.00 8 HY57V561620T IBIS SPECIFICATION IOH Characteristics (Pull-up) Voltage 100MHz Min 100MHz Max 66MHz and 100MHz Pull-up 66MHz Min 0 0.5 1 1.5 2 2.5 3 3.5 3 3.5 0 I (mA) 3.45 I (mA) I (mA) -100 -2.4 3.3 -27.3 -200 3.0 0.0 -74.1 -0.7 2.6 -21.1 -129.2 -7.5 2.4 -34.1 -153.3 -13.3 2.0 -58.7 -197.0 -27.5 1.8 -67.3 -226.2 -35.5 1.65 -73.0 -248.0 -41.1 1.5 -77.9 -269.7 -47.9 1.4 -80.8 -284.3 -52.4 1.0 -88.6 -344.5 -72.5 0.0 -93.0 -502.4 -93.0 I (mA) (V) -300 -400 -500 -600 Voltage (V) Ioh Min (100MHz) Ioh Min (66MHz) Ioh Min (66 and 100MHz) IOL Characteristics (Pull-down) 66MHz and 100MHz Pull-down 100MHz Min 100MHz Max 66MHz Min 250 (V) I (mA) I (mA) I (mA) 200 0.0 0.0 0.0 0.0 0.4 27.5 70.2 17.7 0.65 41.8 107.5 26.9 0.85 51.6 133.8 33.3 1.0 58.0 151.2 37.6 1.4 70.7 187.7 46.6 1.5 72.9 194.4 48.0 1.65 75.4 202.5 49.5 1.8 77.0 208.6 50.7 1.95 77.6 212.0 51.5 3.0 80.3 219.6 54.2 3.45 81.4 222.6 54.9 I (mA) Voltage 150 100 50 0 0 0.5 1 1.5 2 Voltage (V) 2.5 I (mA) 100 min I (mA) 66 min I (mA) 100 max ** IBIS spec. is also applied to 133MHz device. Revision 1.5 / May.00 9 HY57V561620T V Minimum VDD clamp current (Referenced to VDD) Clamp @ CLK, CKE, CS VDD I(mA) 20 0.0 0.2 0.0 0.0 15 0.7 0.0 0.0 mA 0.6 10 0.9 1.0 0.23 5 1.34 1.4 1.6 0 5.06 0 7.35 1 2 Voltage 2.0 2.2 3 12.48 I (mA) 15.30 2.6 CS, DQM & DQ VSS SS (V) -2.6 -3 Minimum V clamp current -2.5 -1.5 -2 -1 -0.5 0 0 -57.23 -45.77 -10 -2.2 -31.22 -24.58 -1.6 -1.4 -12.56 -20 mA -2.0 -30 -40 -7.57 -1.0 -0.9 -50 -1.75 -0.58 Voltage -0.7 -0.6 -60 0.0 0.0 I (mA) -0.2 0.0 Revision 1.5 / May.00 0.0 10 HY57V561620T DEVICE OPERATING OPTION TABLE HY57V561620T-H CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns CAS Latency tRCD tRAS tRC tRP tAC tOH HY57V561620T-8 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns HY57V561620T-S CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns HY57V561620T-10 CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10.0ns) 3CLKs 3CLKs 5CLKs 8CLKs 3CLKs 8ns 3ns 83MHz(12.0ns) 2CLKs 3CLKs 5CLKs 8CLKs 3CLKs 8ns 3ns 66MHz(15.0ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 8ns 3ns Revision 1.5 / May.00 11 HY57V561620T COMMAND TRUTH TABLE Command A10/ AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X ADDR RA Read Note 1 V L CA Read with Autoprecharge V H Write L H X L H L L X CA Write with Autoprecharge H X L L H L X Precharge selected Bank Burst Stop H UDQM, LDQM H Auto Refresh H H L L L Entry H L L L X H X Exit L H H L H H L X L V X V X H X X L H X X X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge power down H X X X Self Refresh Entry V H Precharge All Banks X X Exit Clock Suspend BA Entry Exit L H L H X L H X X X X Note : 1. OP Code : Operand Code 2. V = Valid, X = Don’t care, H = Logic High, L= Logic Low, RA = Row Address, CA = Column Address. Revision 1.5 / May.00 12 HY57V561620T PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package Unit : mm(Inch) Revision 1.5 / May.00 13