a FEATURES Operates from +1.7 V to ⴞ18 V Low Supply Current: 15 A/Amplifier Low Offset Voltage: 75 V Outputs Sink and Source: ⴞ8 mA No Phase Reversal Single- or Dual-Supply Operation High Open-Loop Gain: 600 V/mV Unity-Gain Stable Precision, Micropower Operational Amplifiers OP193/OP293/OP493* PIN CONFIGURATIONS 8-Lead SO (S Suffix) 8-Lead Epoxy DIP (P Suffix) NULL NC –IN A +IN A V+ OP193 OUT A NULL V– NULL 1 8 NC –IN A 2 7 V+ +IN A 3 6 OUT A 4 5 NULL V– APPLICATIONS Digital Scales Strain Gages Portable Medical Equipment Battery-Powered Instrumentation Temperature Transducer Amplifier GENERAL DESCRIPTION The OP193 family of single-supply operational amplifiers features a combination of high precision, low supply current and the ability to operate at low voltages. For high performance in single-supply systems the input and output ranges include ground, and the outputs swing from the negative rail to within 600 mV of the positive supply. For low voltage operation the OP193 family can operate down to 1.7 volts or ± 0.85 volts. The combination of high accuracy and low power operation make the OP193 family useful for battery-powered equipment. Its low current drain and low voltage operation allow it to continue performing long after other amplifiers have ceased functioning either because of battery drain or headroom. The OP193 family is specified for single +2 volt through dual ±15 volt operation over the HOT (–40°C to +125°C) temperature range. They are available in plastic DIPs, plus SOIC surfacemount packages. OP193 NC = NO CONNECT 8-Lead SO (S Suffix) OUT A –IN A +IN A 8-Lead Epoxy DIP (P Suffix) V+ OP293 V– OUT B OUT A 1 –IN A 2 7 OUT B +IN A 3 6 –IN B 5 +IN B 4 16-Lead Wide Body SOL (S Suffix) OUT A 1 14 OUT D –IN A 2 13 –IN D 12 +IN D OP493 V+ –IN B 14-Lead Epoxy DIP (P Suffix) V+ 4 8 +IN B V– +IN A 3 OP293 11 V– +IN B 5 10 +IN C –IN B 6 9 –IN C OUT B 7 8 OUT C OUT A –IN A +IN A V+ +IN B –IN B OUT B NC OP493 OUT D –IN D +IN D V– +IN C –IN C OUT C NC NC = NO CONNECT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 OP193/OP293/OP493–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V = ⴞ15.0 V, T = 25ⴗC unless otherwise noted) S A “E” Grade Min Typ Max Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage VOS OP193 OP193, –40°C ≤ TA ≤ +125°C OP293 OP293, –40°C ≤ TA ≤ +125°C OP493 OP493, –40°C ≤ TA ≤ +125°C VCM = 0 V, –40°C ≤ TA ≤ +125°C VCM = 0 V, –40°C ≤ TA ≤ +125°C Input Bias Current IB Input Offset Current IOS Input Voltage Range Common-Mode Rejection VCM CMRR Large Signal Voltage Gain AVO Large Signal Voltage Gain Large Signal Voltage Gain Long Term Offset Voltage Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Swing High Output Voltage Swing Low Short Circuit Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier NOISE PERFORMANCE Voltage Noise Density Current Noise Density Voltage Noise DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Channel Separation AVO AVO VOS ∆VOS/∆T VOH VOL –14.9 ≤ VCM ≤ +14 V –14.9 ≤ VCM ≤ +14 V, –40°C ≤ TA ≤ +125°C RL = 100 kΩ, –10 V ≤ VOUT ≤ +10 V –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +125°C RL = 10 kΩ, –10 V ≤ VOUT ≤ +10 V –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +125°C RL = 2 kΩ, –10 V ≤ VOUT ≤ +10 V –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +125°C Note 1 Note 2 IL = 1 mA IL = 1 mA, –40°C ≤ TA ≤ +125°C IL = 5 mA IL = –1 mA IL = –1 mA, –40°C ≤ TA ≤ +125°C IL = –5 mA –14.9 100 ISY VS = ± 1.5 V to ± 18 V VS = ± 1.5 V to ± 18 V, –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C, RL = ∞ VOUT = 0 V, VS = ± 18 V Unit 75 175 100 200 125 225 150 250 250 350 275 375 µV µV µV µV µV µV 15 20 nA 4 +13.5 nA V dB 2 +13.5 116 –14.9 97 116 97 94 dB 500 300 500 300 300 V/mV V/mV V/mV 150 V/mV V/mV V/mV 300 350 200 350 200 150 200 125 200 125 100 0.2 14.1 14.0 13.9 100 150 1.75 14.2 300 14.1 14.1 –14.7 –14.6 14.0 13.9 –14.4 +14.2 –14.1 ± 25 ISC PSRR “F” Grade Min Typ Max 100 120 97 97 V/mV V/mV V/mV µV µV/°C 14.2 V 14.1 –14.7 –14.6 V V V –14.4 +14.2 –14.1 ± 25 V V mA 120 dB 94 dB 30 30 µA en in en p-p f = 1 kHz f = 1 kHz 0.1 Hz to 10 Hz 65 0.05 3 65 0.05 3 nV/√Hz pA/√Hz µV p-p SR GBP RL = 2 kΩ 15 35 15 35 V/ms kHz 120 120 dB VOUT = 10 V p-p, RL = 2 kΩ, f = 1 kHz NOTES 1 Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125 °C, with an LTPD of 1.3. 2 Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta. Specifications subject to change without notice. –2– REV. B OP193/OP293/OP493 ELECTRICAL SPECIFICATIONS (@ V = 5.0 V, V S CM = 0.1 V, TA = 25ⴗC unless otherwise noted) “E” Grade Min Typ Max Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage VOS OP193 OP193, –40°C ≤ TA ≤ +125°C OP293 OP293, –40°C ≤ TA ≤ +125°C OP493 OP493, –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection IB IOS VCM CMRR Large Signal Voltage Gain AVO Large Signal Voltage Gain Long Term Offset Voltage Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Swing High Output Voltage Swing Low Short Circuit Current POWER SUPPLY Power Supply Rejection Ratio AVO VOS ∆VOS/∆T VOH VOL 0.1 ≤ VCM ≤ 4 V 0.1 ≤ VCM ≤ 4 V, –40°C ≤ TA ≤ +125°C RL = 100 kΩ, 0.03 ≤ VOUT ≤ 4.0 V –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +125°C RL = 10 kΩ, 0.03 ≤ VOUT ≤ 4.0 V –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +125°C Note 1 Note 2 IL = 100 µA IL = 1 mA IL = 1 mA, –40°C ≤ TA ≤ +125°C IL = 5 mA IL = –100 µA IL = –100 µA, –40°C ≤ TA ≤ +125°C No Load IL = –1 mA IL = –1 mA, –40°C ≤ TA ≤ +125°C IL = –5 mA 0 100 75 175 100 200 125 225 15 2 4 116 “F” Grade Min Typ Max 0 96 150 250 250 350 275 375 20 4 4 116 Unit µV µV µV µV µV µV nA nA V dB 92 92 dB 200 125 200 125 V/mV V/mV V/mV 130 130 75 50 75 50 70 0.2 4.1 4.0 4.0 70 150 1.25 4.4 4.4 4.4 140 300 4.1 4.0 4.0 160 4.4 4.4 V V 4.4 140 V V mV 220 5 280 700 ±8 ISC 160 220 5 280 400 500 900 V/mV V/mV V/mV µV µV/°C 700 ±8 400 500 900 mV mV mV mV mV mA ISY VS = ± 1.7 V to ± 6.0 V VS = ± 1.5 V to ± 18 V, –40°C ≤ TA ≤ +125°C VCM = 2.5 V, RL = ∞ NOISE PERFORMANCE Voltage Noise Density Current Noise Density Voltage Noise en in en p-p f = 1 kHz f = 1 kHz 0.1 Hz to 10 Hz 65 0.05 3 65 0.05 3 nV/√Hz pA/√Hz µV p-p DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product SR GBP RL = 2 kΩ 12 35 12 35 V/ms kHz Supply Current/Amplifier PSRR 100 120 120 dB 14.5 14.5 dB µA 94 97 90 NOTES 1 Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125 °C, with an LTPD of 1.3. 2 Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta. Specifications subject to change without notice. REV. B –3– OP193/OP293/OP493 ELECTRICAL SPECIFICATIONS (@ V = 3.0 V, V S CM = 0.1 V, TA = 25ⴗC unless otherwise noted) “E” Grade Min Typ Max Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage VOS OP193 OP193, –40°C ≤ TA ≤ +125°C OP293 OP293, –40°C ≤ TA ≤ +125°C OP493 OP493, –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Large Signal Voltage Gain Long Term Offset Voltage Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Swing High Output Voltage Swing Low Short Circuit Current POWER SUPPLY Power Supply Rejection Ratio IB IOS VCM CMRR 0.1 ≤ VCM ≤ 2 V 0.1 ≤ VCM ≤ 2 V, –40°C ≤ TA ≤ +125°C RL = 100 kΩ, 0.03 ≤ VOUT ≤ 2 V AVO –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +125°C VOS Note 1 ∆VOS/∆T Note 2 VOH VOL PSRR ISY Supply Voltage Range VS DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Channel Separation VS = +1.7 V to +6 V, –40°C ≤ TA ≤ +125°C VCM = 1.5 V, RL = ∞ –40°C ≤ TA ≤ +125°C 116 90 100 75 0 94 0.2 2.1 1.9 1.9 116 100 150 1.25 2.14 2.1 280 700 ±8 300 2.1 1.9 1.9 400 500 900 100 94 +2 150 250 250 350 275 375 20 4 2 87 100 75 100 ISC Supply Current/Amplifier NOISE PERFORMANCE Voltage Noise Density Current Noise Density Voltage Noise IL = 1 mA IL = 1 mA, –40°C ≤ TA ≤ +125°C IL = 5 mA IL = –1 mA IL = –1 mA –40°C ≤ TA ≤ +125°C IL = –5 mA 0 97 75 175 100 200 125 225 15 2 2 “F” Grade Min Typ Max dB V/mV V/mV V/mV µV µV/°C V 2.1 280 V V mV 700 ±8 +2 µV µV µV µV µV µV nA nA V dB 2.14 400 500 900 97 90 14.5 22 22 ± 18 Unit mV mV mA 14.5 22 22 ± 18 dB µA µA V en in en p-p f = 1 kHz f = 1 kHz 0.1 Hz to 10 Hz 65 0.05 3 65 0.05 3 nV/√Hz pA/√Hz µV p-p SR GBP RL = 2 kΩ 10 25 10 25 V/ms kHz 120 120 dB VOUT = 10 V p-p, RL = 2 kΩ, f = 1 kHz NOTES 1 Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125 °C, with an LTPD of 1.3. 2 Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta. Specifications subject to change without notice. –4– REV. B OP193/OP293/OP493 ELECTRICAL SPECIFICATIONS (@ V = 2.0 V, V S CM = 0.1 V, TA = 25ⴗC unless otherwise noted) “E” Grade Min Typ Max Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage VOS Input Bias Current Input Offset Current Input Voltage Range Large Signal Voltage Gain IB IOS VCM AVO OP193 OP193, –40°C ≤ TA ≤ +125°C OP293 OP293, –40°C ≤ TA ≤ +125°C OP493 OP493, –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C Long Term Offset Voltage VOS POWER SUPPLY Power Supply Rejection Ratio PSRR Supply Current/Amplifier ISY Supply Voltage Range VS RL = 100 kΩ, 0.03 ≤ VOUT ≤ 1 V –40°C ≤ TA ≤ +125°C Note 1 VS = 1.7 V to 6 V, –40°C ≤ TA ≤ +125°C VCM = 1.0 V, RL = ∞ –40°C ≤ TA ≤ +125°C 75 175 100 175 125 225 15 2 1 0 60 “F” Grade Min Typ Max 150 250 250 350 275 375 20 4 1 0 60 70 70 150 100 94 +2 300 97 90 13.2 20 25 ± 18 +2 Unit µV µV µV µV µV µV nA nA V V/mV V/mV µV 13.2 20 25 ± 18 dB µA µA V NOISE PERFORMANCE Voltage Noise Density Current Noise Density Voltage Noise en in en p-p f = 1 kHz f = 1 kHz 0.1 Hz to 10 Hz 65 0.05 3 65 0.05 3 nV/√Hz pA/√Hz µV p-p DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product SR GBP RL = 2 kΩ 10 25 10 25 V/ms kHz Specifications subject to change without notice. REV. B –5– OP193/OP293/OP493 ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Output Short-Circuit Duration to Gnd . . . . . . . . . . Indefinite Storage Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range OP193/OP293/OP493E, F . . . . . . . . . . . . –40°C to +125°C Junction Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C Package Type θJA3 θJC Unit 8-Pin Plastic DIP (P) 8-Pin SOIC (S) 14-Pin Plastic DIP (P) 16-Pin SOL (S) 103 158 83 92 43 43 39 27 °C/W °C/W °C/W °C/W Model Temperature Range Package Description Package Option OP193ES* OP193ES-REEL* OP193ES-REEL7* OP193FP* OP193FS OP193FS-REEL OP193FS-REEL7 OP293ES OP293ES-REEL OP293ES-REEL7 OP293FP* OP293FS OP293FS-REEL OP293FS-REEL7 OP493ES* OP493ES-REEL* OP493FP* OP493FS* OP493FS-REEL* –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin Plastic DIP 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin Plastic DIP 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 16-Pin SOL 16-Pin SOL 14-Pin Plastic DIP 16-Pin SOL 16-Pin SOL SO-8 SO-8 SO-8 N-8 SO-8 SO-8 SO-8 SO-8 SO-8 SO-8 N-8 SO-8 SO-8 SO-8 SOL-16 SOL-16 N-14 SOL-16 SOL-16 *Not for new design, obsolete April 2002. NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For supply voltages less than ± 18 V, the input voltage is limited to the supply voltage. 3 θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket for PDIP, and θJA is specified for device soldered in circuit board for SOIC package. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP193/OP293/OP493 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– WARNING! ESD SENSITIVE DEVICE REV. B Typical Performance Characteristics–OP193/OP293/OP493 NUMBER OF AMPLIFIERS 160 450 ⴛ PDIPS 120 80 40 0 –75 –60 –45 –30 –15 0 150 VS ⴝ 3V VCM ⴝ 0.1V TA ⴝ 25°C 160 450 ⴛ PDIPS 120 80 40 0 –75 –60 –45 –30 –15 0 15 30 45 60 75 OFFSET – V TPC 1. OP193 Offset Distribution, VS = ± 15 V TPC 2. OP193 Offset Distribution, VS = +3 V 120 450 ⴛ PDIPS 90 60 30 0.2 0.4 0.6 0.8 –1 +125°C –2 1 2 3 4 COMMON-MODE VOLTAGE – V 0 10 100 1k FREQUENCY – Hz TPC 7. CMRR vs. Frequency REV. B 10k +PSRR 60 100 1k FREQUENCY – Hz 10k TPC 6. PSRR vs. Frequency 40 +SR ⴝ –SR VS ⴝ ±15V 15 +SR ⴝ –SR VS ⴝ +5V 10 5 20 80 0 10 5 SHORT CIRCUIT CURRENT – mA SLEW RATE – V/ms CMRR – dB 20 VS ⴝ +5V 5V ⱕ VS ⱕ 30V TA ⴝ 25°C 20 25 40 1.0 40 TA ⴝ 25°C 60 0.8 0.6 +25°C –3 TPC 5. Input Bias Current vs. Common-Mode Voltage 100 0.4 –PSRR 100 0 120 80 0.2 –40°C TCVOS – VⲐ°C VS ⴝ ±15V 30 120 0 1.0 TPC 4. OP193 TCVOS Distribution, VS = ± 15 V 60 TPC 3. OP193 TCVOS Distribution, VS = +3 V –4 0 0 450 ⴛ PDIPS 90 VS ⫽ 5V INPUT BIAS CURRENT – nA NUMBER OF AMPLIFIERS VS ⴝ ⴞ15V –40°C ⱕ TA ⱕ +125°C 120 TCVOS – VⲐ°C 1 150 VS ⴝ 3V VCM ⴝ 0.1V –40°C ⱕ TA ⱕ +125°C 0 0 15 30 45 60 75 OFFSET – V PSRR – dB NUMBER OF AMPLIFIERS 200 VS ⴝ ±15V TA ⴝ 25°C NUMBER OF AMPLIFIERS 200 0 –50 –25 +ISC VS ⴝ ±15V 30 | –ISC | VS ⴝ ±15V 20 10 +ISC VS ⴝ +5V | –ISC | VS ⴝ +5V 0 25 50 75 100 125 TEMPERATURE – °C TPC 8. Slew Rate vs. Temperature –7– 0 –50 –25 0 25 50 75 100 125 TEMPERATURE – °C TPC 9. Short Circuit Current vs. Temperature OP193/OP293/OP493 –0.5 –0.10 VS ⴝ +2V VCM ⴝ 0.1V –0.15 –0.20 0 25 –1 20 SUPPLY CURRENT – µA INPUT BIAS CURRENT – nA VS ⴝ ±15V –2 –3 VS ⴝ +2V VCM ⴝ 0.1V –4 VS ⴝ ±18V 15 VS ⴝ +2V VCM ⴝ 1V 10 5 VS ⴝ ±15V –0.25 –50 –25 0 25 50 75 100 –5 –50 125 –25 TEMPERATURE – °C 25 50 75 100 CURRENT NOISE DENSITY – pAⲐ Hz 100 10 1 10 100 FREQUENCY – Hz TPC 13. Voltage Noise Density vs. Frequency 100 10 1 10 100 FREQUENCY – Hz 2000 800 100 125 5V ⱕ VS ⱕ 30V TA ⴝ 25°C 1000 DELTA FROM VCC 100 DELTA FROM VEE 10 1k TPC 14. Current Noise Density vs. Frequency 1000 75 1 0.1 2500 50 10000 5V ⱕ VS ⱕ 30V TA ⴝ 25°C 1 1k 25 TPC 12. Supply Current vs. Temperature 1000 5V ⱕ VS ⱕ 30V TA ⴝ 25°C 0 TEMPERATURE – °C TPC 11. Input Bias Current vs. Temperature 1000 1 0.1 0 –50 –25 125 TEMPERATURE – °C TPC 10. Input Offset Current vs. Temperature VOLTAGE NOISE DENSITY – nVⲐ Hz 0 DELTA FROM SUPPLY RAIL – mV INPUT OFFSET CURRENT – nA 0 0.1 1 10 100 1000 LOAD CURRENT – A 10000 TPC 15. Delta Output Swing from Either Rail vs. Current Load 60 1500 1000 VS ⴝ +5V 0.03V ⱕ VOUT ⱕ 4V 500 0 –50 –25 0 25 50 75 100 TEMPERATURE – °C TPC 16. Voltage Gain (RL = 100 kΩ) vs. Temperature 125 VS ⴝ 5V VS ⴝ ±15V –10V ⱕ VOUT ⱕ +10V 40 600 400 GAIN – dB VS ⴝ ±15V –10V ⱕ VOUT ⱕ +10V VOLTAGE GAIN – VⲐmV VOLTAGE GAIN – VⲐmV TA ⴝ 25°C VS ⴝ +5V 0.03V ⱕ VOUT ⱕ 4V 0 200 0 –50 –25 0 25 50 75 100 TEMPERATURE – °C TPC 17. Voltage Gain (RL = 10 kΩ) vs. Temperature –8– 20 125 –20 10 100 1k 10k FREQUENCY – Hz 100k TPC 18. Closed-Loop Gain vs. Frequency, VS = 5 V REV. B OP193/OP293/OP493 50 OVERSHOOT – % GAIN – dB 40 20 VS ⴝ 5V TA ⴝ 25°C AV ⴝ 1 50mV ⱕ VIN ⱕ 150mV LOADS TO GND 60 +OS ⴝ | –OS | RL ⴝ 50k⍀ VS ⴝ 5V PHASE 40 90 40 30 +OS RL ⴝ ⴥ 45 20 GAIN 0 0 20 PHASE – Degrees 60 TA ⴝ 25°C VS ⴝ ±15V GAIN – dB 60 0 +OS ⴝ | –OS | RL ⴝ 10k⍀ 10 –OS RL ⴝ ⴥ –20 10 100 1k 10k FREQUENCY – Hz 0 10 100k –90 –40 100 10000 TPC 20. Small Signal Overshoot vs. Capacitive Load TPC 19. Closed-Loop Gain vs. Frequency, VS = ± 15 V 1k 10k 100k FREQUENCY – Hz 1M TPC 21. Open-Loop, Gain and Phase vs. Frequency V+ 60 VS ⴝ ±15V I1 45 20 GAIN 0 0 –20 I2 +INPUT 2k⍀ 90 PHASE PHASE – Degrees 40 GAIN – dB 100 1000 CAPACITIVE LOAD – pF –45 –20 I3 I4 2k⍀ Q5 Q1 Q2 –INPUT OP293, OP493 ONLY –45 Q6 Q4 Q3 Q7 TO OUTPUT STAGE Q8 D1 –40 100 –90 1k 10k 100k FREQUENCY – Hz 1M R1A R2A R1B R2B I5 TPC 22. Open-Loop, Gain and Phase vs. Frequency I6 V– NULLING TERMINALS (OP193 ONLY) FUNCTIONAL DESCRIPTION Figure 1. OP193/OP293/OP493 Equivalent Input Circuit The OP193 family of operational amplifiers are single-supply, micropower, precision amplifiers whose input and output ranges both include ground. Input offset voltage (VOS) is only 75 µV maximum, while the output will deliver ± 5 mA to a load. Supply current is only 17 µA. V+ Q4 A simplified schematic of the input stage is shown in Figure 1. Input transistors Q1 and Q2 are PNP devices, which permit the inputs to operate down to ground potential. The input transistors have resistors in series with the base terminals to protect the junctions from over voltage conditions. The second stage is an NPN cascode which is buffered by an emitter follower before driving the final PNP gain stage. The OP193 includes connections to taps on the input load resistors, which can be used to null the input offset voltage, VOS. The OP293 and OP493 have two additional transistors, Q7 and Q8. The behavior of these transistors is discussed in the Output Phase Reversal section of this data sheet. The output stage, shown in Figure 2, is a noninverting NPN “totem-pole” configuration. Current is sourced to the load by emitter follower Q1, while Q2 provides current sink capability. When Q2 saturates, the output is pulled to within 5 mV of ground without an external pull-down resistor. The totem-pole output stage will supply a minimum of 5 mA to an external load, even when operating from a single 3.0 V power supply. REV. B FROM INPUT STAGE Q1 Q5 OUTPUT Q3 Q2 I3 I2 I1 V– Figure 2. OP193/OP293/OP493 Equivalent Output Circuit By operating as an emitter follower, Q1 offers a high impedance load to the final PNP collector of the input stage. Base drive to Q2 is derived by monitoring Q1’s collector current. Transistor Q5 tracks the collector current of Q1. When Q1 is on, Q5 keeps Q4 off, and current source I1 keeps Q2 turned off. When Q1 is driven to cutoff (i.e., the output must move toward V–), Q5 allows Q4 to turn on. Q4’s collector current then provides the base drive for Q3 and Q2, and the output low voltage swing is set by Q2’s VCE,SAT which is about 5 mV. –9– OP193/OP293/OP493 Driving Capacitive Loads OP193 family amplifiers are unconditionally stable with capacitive loads less than 200 pF. However, the small signal, unity-gain overshoot will improve if a resistive load is added. For example, transient overshoot is 20% when driving a 1000 pF/ 10 kΩ load. When driving large capacitive loads in unity-gain configurations, an in-the-loop compensation technique is recommended as illustrated in Figure 6. Input Overvoltage Protection weight, and high energy density relative to older primary cells. Most lithium cells have a nominal output voltage of 3 V and are noted for a flat discharge characteristic. The low supply voltage requirement of the OP193, combined with the flat discharge characteristic of the lithium cell, indicates that the OP193 can be operated over the entire useful life of the cell. Figure 3 shows the typical discharge characteristic of a 1 AH lithium cell powering the OP193, OP293, and OP493, with each amplifier, in turn, driving 2.1 Volts into a 100 kΩ load. As previously mentioned, the OP193 family of op amps use a PNP input stage with protection resistors in series with the inverting and noninverting inputs. The high breakdown of the PNP transistors, coupled with the protection resistors, provides a large amount of input protection from over voltage conditions. The inputs can therefore be taken 20 V beyond either supply without damaging the amplifier. LITHIUM SULPHUR DIOXIDE CELL VOLTAGE – V 4 Output Phase Reversal—OP193 The OP193’s input PNP collector-base junction can be forwardbiased if the inputs are brought more than one diode drop (0.7 V) below ground. When this happens to the noninverting input, Q4 of the cascode stage turns on and the output goes high. If the positive input signal can go below ground, phase reversal can be prevented by clamping the input to the negative supply (i.e., GND) with a diode. The reverse leakage of the diode will, of course, add to the input bias current of the amplifier. If input bias current is not critical, a 1N914 will add less than 10 nA of leakage. However, its leakage current will double for every 10°C increase in ambient temperature. For critical applications, the collector-base junction of a 2N3906 transistor will add only about 10 pA of additional bias current. To limit the current through the diode under fault conditions, a 1 kΩ resistor is recommended in series with the input. (The OP193’s internal current limiting resistors will not protect the external diode.) Output Phase Reversal—OP293 and OP493 The OP293 and OP493 include lateral PNP transistors Q7 and Q8 to protect against phase reversal. If an input is brought more than one diode drop (≈0.7 V) below ground, Q7 and Q8 combine to level shift the entire cascode stage, including the bias to Q3 and Q4, simultaneously. In this case Q4 will not saturate and the output remains low. 3 2 OP493 OP193 OP293 1 0 0 1000 2000 3000 4000 5000 6000 7000 HOURS Figure 3. Lithium Sulfur Dioxide Cell Discharge Characteristic with OP193 Family and 100 kΩ Loads Input Offset Voltage Nulling The OP193 provides two offset nulling terminals that can be used to adjust the OP193’s internal VOS. In general, operational amplifier terminals should never be used to adjust system offset voltages. The offset null circuit of Figure 4 provides about ± 7 mV of offset adjustment range. A 100 kΩ resistor placed in series with the wiper arm of the offset null potentiometer, as shown in Figure 5, reduces the offset adjustment range to 400 µV and is recommended for applications requiring high null resolution. Offset nulling does not adversely affect TCVOS performance, providing that the trimming potentiometer temperature coefficient does not exceed ± 100 ppm/°C. The OP293 and OP493 do not exhibit output phase reversal for inputs up to –5 V below V– at +25°C. The phase reversal limit at +125°C is about –3 V. If the inputs can be driven below these levels, an external clamp diode, as discussed in the previous section, should be added. V+ 7 2 OP193 Battery-Powered Applications OP193 series op amps can be operated on a minimum supply voltage of 1.7 V, and draw only 13 µA of supply current per amplifier from a 2.0 V supply. In many battery-powered circuits, OP193 devices can be continuously operated for thousands of hours before requiring battery replacement, thus reducing equipment downtime and operating cost. 6 4 3 5 1 100k⍀ V– Figure 4. Offset Nulling Circuit High performance portable equipment and instruments frequently use lithium cells because of their long shelf life, light –10– REV. B OP193/OP293/OP493 V+ R1 240k⍀ 7 2 OP193 V+ (2.5V TO 36V) R2 1.5M⍀ C1 1000pF 6 7 2 OP193 4 3 5 6 VOUT (1.23V @ 25°C) 5 3 1 4 100k⍀ 100k⍀ 1 V– Q2 Figure 5. High Resolution Offset Nulling Circuit 3 MAT-01AH Q1 7 2 6 VBE2 5 VBE1 A Micropower False-Ground Generator Some single-supply circuits work best when inputs are biased above ground, typically at 1/2 of the supply voltage. In these cases a false ground can be created by using a voltage divider buffered by an amplifier. One such circuit is shown in Figure 6. This circuit will generate a false-ground reference at 1/2 of the supply voltage, while drawing only about 27 µA from a 5 V supply. The circuit includes compensation to allow for a 1 µF bypass capacitor at the false-ground output. The benefit of a large capacitor is that not only does the false ground present a very low dc resistance to the load, but its ac impedance is low as well. The OP193 can both sink and source more than 5 mA, which improves recovery time from transients in the load current. 5V OR 12V 10k⍀ 0.022F 240k⍀ 2 7 100⍀ OP193 3 240k⍀ 2.5V OR 6V 6 4 1F 1F V1 R3 68k⍀ ⌬VBE R4 130k⍀ R5 20k⍀ OUTPUT ADJUST Figure 7. A Battery-Powered Voltage Reference A Single-Supply Current Monitor Current monitoring essentially consists of amplifying the voltage drop across a resistor placed in series with the current to be measured. The difficulty is that only small voltage drops can be tolerated, and with low precision op amps this greatly limits the overall resolution. The single-supply current monitor of Figure 8 has a resolution of 10 µA and is capable of monitoring 30 mA of current. This range can be adjusted by changing the current sense resistor R1. When measuring total system current, it may be necessary to include the supply current of the current monitor, which bypasses the current sense resistor, in the final result. This current can be measured and calibrated (together with the residual offset) by adjustment of the offset trim potentiometer, R2. This produces a deliberate temperature dependent offset. However, the supply current of the OP193 is also proportional to temperature, and the two effects tend to track. Current in R4 and R5, which also bypasses R1, can be adjusted via a gain trim. Figure 6. A Micropower False-Ground Generator V+ A Battery-Powered Voltage Reference The circuit of Figure 7 is a battery-powered voltage reference that draws only 17 µA of supply current. At this level, two AA alkaline cells can power this reference for more than 18 months. At an output voltage of 1.23 V @ 25°C, drift of the reference is only 5.5 µV/°C over the industrial temperature range. Load regulation is 85 µV/mA with line regulation at 120 µV/V. TO CIRCUIT UNDER TEST OP193 ITEST 6 4 2 Design of the reference is based on the Brokaw bandgap core technique. Scaling of resistors R1 and R2 produces unequal currents in Q1 and Q2. The resulting ∆VBE across R3 creates a temperature-proportional voltage (PTAT) which, in turn, produces a larger temperature-proportional voltage across R4 and R5, V1. The temperature coefficient of V1 cancels (first order) the complementary to absolute temperature (CTAT) coefficient of VBE1. When adjusted to 1.23 V @ 25°C, output voltage tempco is at a minimum. Bandgap references can have start-up problems. With no current in R1 and R2, the OP193 is beyond its positive input range limit and has an undefined output state. Shorting Pin 5 (an offset adjust pin) to ground forces the output high under these circumstances and ensures reliable startup without significantly degrading the OP193’s offset drift. REV. B 7 3 5 VOUT = 100mV/mA(ITEST) 1 R2 100k⍀ R1 1⍀ R5 100⍀ R2 9.9k⍀ R3 100k⍀ Figure 8. Single-Supply Current Monitor –11– OP193/OP293/OP493 A Single-Supply Instrumentation Amplifier R1 20k⍀ Designing a true single-supply instrumentation amplifier with zero-input and zero-output operation requires special care. The traditional configuration, shown in Figure 9, depends upon amplifier A1’s output being at 0 V when the applied commonmode input voltage is at 0 V. Any error at the output is multiplied by the gain of A2. In addition, current flows through resistor R3 as A2’s output voltage increases. A1’s output must remain at 0 V while sinking the current through R3, or a gain error will result. With a maximum output voltage of 4 V, the current through R3 is only 2 µA, but this will still produce an appreciable error. R1 20k⍀ R2 1.98M⍀ 5V R3 20k⍀ V+ A1 1/2 OP293 –IN V– R4 1.98M⍀ 5V 10k⍀ 5V Q2 Q1 V+ A2 1/2 OP293 VN2222 R2 1.98M⍀ +IN VOUT V– 5V R3 20k⍀ V+ A1 1/2 OP293 –IN V– Figure 10. An Improved Single-Supply, 0 VIN, 0 VOUT Instrumentation Amplifier R4 1.98M⍀ 5V ISINK A Low-Power, Temperature to 4–20 mA Transmitter V+ A2 1/2 OP293 +IN VOUT V– Figure 9. A Conventional Instrumentation Amplifier One solution to this problem is to use a pull-down resistor. For example, if R3 = 20 kΩ, then the pull-down resistor must be less than 400 Ω. However, the pull-down resistor appears as a fixed load when a common-mode voltage is applied. With a 4 V common-mode voltage, the additional load current will be 10 mA, which is unacceptable in a low power application. Figure 10 shows a better solution. A1’s sink current is provided by a pair of N-channel FET transistors, configured as a current mirror. With the values shown, sink current of Q2 is about 340 µA. Thus, with a common-mode voltage of 4 V, the additional load current is limited to 340 µA versus 10 mA with a 400 Ω resistor. A simple temperature to 4–20 mA transmitter is shown in Figure 11. After calibration, this transmitter is accurate to ± 0.5°C over the –50°C to +150°C temperature range. The transmitter operates from 8 V to 40 V with supply rejection better than 3 ppm/V. One half of the OP293 is used to buffer the VTEMP pin, while the other half regulates the output current to satisfy the current summation at its noninverting input: I OUT + ( VTEMP × R6 + R7 R2 × R10 ) −V SET R2 + R6 + R7 R2 × R10 The change in output current with temperature is the derivative of the transfer function: ∆VTEMP ∆I OUT ∆T = ( R6 + R7 ∆T R2 × R10 ) 1N4002 R4 20k⍀ REF-43BZ 2 VI N 2 VOUT 6 VTEMP 3 GND 4 8 1/2 OP293 3 R1 10k⍀ 4 1 VTEMP R3 100k⍀ R2 1k⍀ R5 5k⍀ R6 3k⍀ R7 5k⍀ 6 VSET ZERO TRIM V+ 8V TO 40V SPAN TRIM 1/2 OP293 5 R8 1k⍀ 7 2N1711 R9 100k⍀ ALL RESISTORS 1/4W, 5% UNLESS OTHERWISE NOTED R10 100⍀ 1%, 1/2 W IOUT RLOAD Figure 11. Temperature to 4–20 mA Transmitter –12– REV. B OP193/OP293/OP493 From the formulas, it can be seen that if the span trim is adjusted before the zero trim, the two trims are not interactive, which greatly simplifies the calibration procedure. Calibration of the transmitter is simple. First, the slope of the output current versus temperature is calibrated by adjusting the span trim, R7. A couple of iterations may be required to be sure the slope is correct. C1 75nF R1 200k⍀ 5V R5 200k⍀ 5V 2 VCONTROL 8 A1 1/2 OP293 3 1 6 A2 1/2 OP293 4 R2 200k⍀ Once the span trim has been completed, the zero trim can be made. Remember that adjusting the zero trim will not affect the gain. R3 100k⍀ 7 SQUARE OUT 5 R4 200k⍀ TRIANGLE OUT R7 200k⍀ R6 200k⍀ The zero trim can be set at any known temperature by adjusting R5 until the output current equals: R8 200k⍀ 5V I OUT = ∆I FS (TAMBIENT − TMIN ) + 4 mA ∆TOPERATING CD4066 1 IN/OUT Table I shows the values of R6 required for various temperature ranges. R6 0°C to 70°C –40°C to +85°C –55°C to +150°C 10 kΩ 6.2 kΩ 3 kΩ f OUT = VCONTROL V × 10 Hz / V 3 OUT/IN S2 4 IN/OUT 5 CONT CONT 12 IN/OUT 11 S3 6 CONT OUT/IN 10 OUT/IN 9 IN/OUT 8 5V S4 7 VSS Figure 12. Micropower Voltage Controlled Oscillator A Micropower, Single-Supply Quad Voltage Output 8-Bit DAC The circuit of Figure 13 uses the DAC8408 CMOS quad 8-bit DAC and the OP493 to form a single-supply quad voltage output DAC with a supply drain of only 140 µA. The DAC8408 is used in the voltage switching mode and each DAC has an output resistance (≈10 kΩ) independent of the digital input code. The output amplifiers act as buffers to avoid loading the DACs. The 100 kΩ resistors ensure that the OP493 outputs will swing to within 1/2 LSB of ground, i.e.: but this can easily be changed by varying C1. The circuit operates well up to 500 Hz. 1 2 REV. B 5V CONT 13 2 OUT/IN A Micropower Voltage Controlled Oscillator An OP293 in combination with an inexpensive quad CMOS analog switch forms the precision VCO of Figure 12. This circuit provides triangle and square wave outputs and draws only 50 µA from a single 5 V supply. A1 acts as an integrator; S1 switches the charging current symmetrically to yield positive and negative ramps. The integrator is bounded by A2 which acts as a Schmitt trigger with a precise hysteresis of 1.67 volts, set by resistors R5, R6, and R7, and associated CMOS switches. The resulting output of A1 is a triangle wave with upper and lower levels of 3.33 and 1.67 volts. The output of A2 is a square wave with almost rail-to-rail swing. With the components shown, frequency of operation is given by the equation: 14 S1 Table I. R6 Values vs. Temperature Temp Range VDD –13– × 1.23 V 256 = 3 mV OP193/OP293/OP493 A Single-Supply Micropower Quad Programmable-Gain Amplifier 5V 5V 3.6k⍀ 4 5V AD589 1.23V 1 2 VDD 4 IOUT1A DAC A VREFA 1/4 DAC8408 2 3 A 1/4 OP493 VOUTA 1 11 R1 100k⍀ = 256 n 6 DAC B VREFB 1/4 DAC8408 6 IOUT1B B 1/4 OP493 8 7 5 VOUTB where n equals the decimal equivalent of the 8-bit digital code present at the DAC. R2 100k⍀ If the digital code present at the DAC consists of all zeros, the feedback loop will be open causing the op amp to saturate. The 10 MΩ resistors placed in parallel with the DAC feedback loop eliminates this problem with a very small reduction in gain accuracy. The 2.5 V reference biases the amplifiers to the center of the linear region providing maximum output swing. 13 DAC C VREFC 1/4 DAC8408 C 1/4 OP493 27 24 IOUT2C/2D 23 IOUT1D VOUT VIN 5 IOUT2A/2B 25 IOUT1C The combination of the quad OP493 and the DAC8408 quad 8-bit CMOS DAC creates a quad programmable-gain amplifier with a quiescent supply drain of only 140 µA (Figure 14). The digital code present at the DAC, which is easily set by a microprocessor, determines the ratio between the fixed DAC feedback resistor and the resistance that the DAC feedback ladder presents to the op amp feedback loop. The gain of each amplifier is: 14 12 VOUTC R3 100k⍀ 9 DAC D V REFD 1/4 DAC8408 D 1/4 OP493 21 10 8 VOUTD R4 100k⍀ OP493 DAC DATA BUS PINS 9(LSB)–16(MSB) A/B 17 18 R/W DAC8408ET DS1 19 DIGITAL CONTROL SIGNALS 20 DS2 DGND 28 Figure 13. Micropower Single-Supply Quad VoltageOutput 8-Bit DAC –14– REV. B OP193/OP293/OP493 VDD C1 0.1F 3 VINA 1 5V RFBA 4 DAC A 1/4 DAC8408 VREFA 2 IOUT1A 4 R1 10M⍀ 2 A 1/4 OP493 1 VOUTA 3 C2 0.1F 7 VI N B IOUT2A/2B 5 VREFB 8 IOUT1B 6 11 RFBB DAC B 1/4 DAC8408 R2 10M⍀ 6 5 C3 0.1F 26 VI N C VI N D 22 7 C 1/4 OP493 8 D 1/4 OP493 14 VOUTB RFBC VREFC 27 IOUT1C 25 DAC C 1/4 DAC8408 C4 0.1F B 1/4 OP493 RFBD DAC D 1/4 DAC8408 R3 10M⍀ 9 VOUTC 10 IOUT2C/2D 24 VREFD 21 R4 10M⍀ IOUT1D 23 13 12 VOUTD DAC DATA BUS PINS 9(LSB)–16(MSB) OP493 17 DIGITAL CONTROL SIGNALS 18 19 20 A/B R/W 2.5V REFERENCE VOLTAGE DAC8408ET DS1 DS2 DGND 28 Figure 14. Single-Supply Micropower Quad Programmable-Gain Amplifier REV. B –15– OP193/OP293/OP493 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8 5 8 1 0.2440 (6.20) 0.2284 (5.80) 4 1 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.015 (0.381) 0.008 (0.204) SEATING PLANE 16-Lead Wide Body SOL (S Suffix) 14-Lead Epoxy DIP (P Suffix) 8 0.280 (7.11) 0.240 (6.10) PIN 1 1 9 16 0.2992 (7.60) 0.2914 (7.40) 7 0.325 (8.25) 0.300 (7.62) 0.795 (20.19) 0.725 (18.42) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.0500 (1.27) 0.0160 (0.41) 0.022 (0.558) 0.014 (0.356) 14 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 4 0.430 (10.92) 0.348 (8.84) 0.1968 (5.00) 0.1890 (4.80) 0.0098 (0.25) 0.0040 (0.10) 0.280 (7.11) 0.240 (6.10) PIN 1 0.1574 (4.00) 0.1497 (3.80) PIN 1 5 C00295–0–1/02(B) 8-Lead Epoxy DIP (P Suffix) 8-Lead SO (S Suffix) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) PIN 1 8 1 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.4133 (10.50) 0.3977 (10.00) 0.4193 (10.65) 0.3937 (10.00) 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45° 0.0098 (0.25) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0125 (0.32) 0.0091 (0.23) 8° 0° 0.0500 (1.27) 0.0157 (0.40) Revision History Page Data Sheet changed from REV. A to REV. B. Deletion of WAFER TEST LIMITS Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Deletion of DICE CHARACTERISTICS Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 –16– REV. B PRINTED IN U.S.A. Location