IRU3004, IRU3005
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK
CONTROLLER IC WITH DUAL LDO CONTROLLER
FEATURES
DESCRIPTION
The IRU3004/IRU3005 series of controller ICs are specifically designed to meet Intel specifications for Pentium
III microprocessor applications as well as the next
generation P6 family processors. The IC provides a single
chip controller IC for the Vcore, GTL+ and clock supplies required for the Pentium III applications. These
devices feature a patented topology, that in combination with a few external components as shown in the
typical application circuit, will provide in excess of 20A
of output current for an on-board DC-DC converter while
automatically providing the right output voltage via the
five-bit internal DAC meeting the latest VRM specification. These products also feature loss-lesscurrent sensing by using the RDS(on) of the high side power MOSFET
as the sensing resistor and a Power Good window comparator that switches its open collector output low when
the output is outside of a ±10% window. Other features
of the device are: Undervoltage lockout for both 5V and
12V supplies, an external programmable soft start function as well as programming the oscillator frequency by
using an external capacitor.
Meets latest VRM 8.4 specification for PIII
Provides single chip solution for Vcore, GTL+ and
clock supply
On-board DAC programs the output voltage from
1.3V to 3.5V. The IRU3004/IRU3005 remains on for
VID code of (11111).
Dual linear regulator controller on-board for 1.5V
GTL+ and 2.5V clock supplies
Loss-less short circuit protection
Synchronous operation allows maximum efficiency
Patented architecture allows fixed frequency operation as well as 100% duty cycle during dynamic
load
Minimum part count. No external compensation.
Soft start
High current totem pole driver for direct driving of the
external power MOSFET
Power Good function
APPLICATIONS
Pentium III & next generation processor DC to DC
converter application
Low cost Pentium with AGP
TYPICAL APPLICATION
L1
L2
Q1
5V
R16
C5
C7
C13
Vout 3
R17
R1
Q2
C3
R2
C16
R4
C10
R3
R12
R13
3.3V
C4
C6
Q3
Vout 1
12V
C11
R18
12
V12
5
V5
8
CS+
9
HDrv
7
CS-
11
LDrv
10
Gnd
1 Ct
14
Vfb3
R7
R11
Lin1 2
13 SS
C2
D4
15
VID4
VID3
VID2
VID1
VID0
Vfb1 3
D3
16
D2
17
D1
18
D0
19
R8
C15
IRU3004
C1
PGd
6
Vfb2
4
Lin2
20
Q4
Vout 2
C9
C12
R14
3004app2-2.0
3.3V
R9
C14
R15
R5
Power Good
C8
Notes: Pentium III is trademark of Intel Corp.
PACKAGE ORDER INFORMATION
Ta (°C)
0 TO 70
0 TO 70
Rev. 1.2
12/8/00
Device
IRU3004CW
IRU3005CW
Package
20-pin Plastic SOIC WB
20-pin Plastic SOIC WB
2.5V Output Voltage
Adjustable
Fixed
4-3
IRU3004, IRU3005
ABSOLUTE MAXIMUM RATINGS
V5 supply Voltage .................................................
V12 Supply Voltage .................................................
Storage Temperature Range ......................................
Operating Junction Temperature Range ......................
10V
20V
-65 TO 150° C
0 TO 125° C
PACKAGE INFORMATION
20-PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
Ct / En 1
20 Lin2
Lin1 2
19 D0
Vfb1 3
18 D1
Vfb2 4
17 D2
V5 5
16 D3
PGd 6
15 D4
CS- 7
14 Vfb3
CS+ 8
13 SS
HDrv 9
12 V12
Gnd 10
11 LDrv
θJA =85°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over,V12 = 12V, V5 = 5V and Ta=0 to 70° C. Typical values
refer to Ta =25° C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the
ambient temperature.
PARAMETER
VID Section
DAC output voltage
(note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID input internal pull-up
resistor to V5
Power Good Section
Under voltage lower trip point
Under voltage upper trip point
UV Hysterises
Over voltage upper trip point
Over voltage lower trip point
OV Hysterises
Power Good Output LO
Power Good Output HI
Soft Start Section
Soft Start Current
4-4
SYM
TEST CONDITION
MIN
0.99Vs
TYP
MAX
UNITS
Vs
1.01Vs
V
0.1
0.5
0.4
%
%
V
V
kΩ
0.91Vs
V
V
V
V
V
V
V
V
2
27
Vout ramping down
Vout ramping up
Vout ramping up
Vout ramping down
0.89Vs
.015Vs
1.09Vs
.015Vs
RL=3mA
RL=5K pull up to 5V
CS+ =0V, CS- =5V
0.90Vs
0.92Vs
.02Vs
1.10Vs
1.08Vs
.02Vs
4.8
10
.025Vs
1.11Vs
.025Vs
0.4
µA
Rev. 1.2
12/8/00
IRU3004, IRU3005
PARAMETER
UVLO Section
UVLO Threshold-12V
UVLO Hysterises-12V
UVLO Threshold-5V
UVLO Hysterises-5V
Error Comparator Section
Input bias current
Input Offset Voltage
Delay to Output
Current Limit Section
C.S Threshold Set Current
C.S Comp Offset Voltage
Hiccup Duty Cycle
Supply Current
Operating Supply Current
SYM
TEST CONDITION
MIN
Supply ramping up
9.2
0.3
4.1
0.2
Supply ramping up
TYP
MAX
UNITS
10
0.4
4.3
0.3
10.8
0.5
4.5
0.4
V
V
V
V
2
+2
100
µA
mV
nS
240
+5
2
µA
mV
%
-2
Vdiff=10mV
160
-5
200
Css=0.1µF
Output Drivers Section
Rise Time
Fall Time
Dead Band Time
Oscillator Section
Osc Frequency
Osc Valley
Osc Peak
LDO Controller Section
Vfb1 & Vfb2 (IRU3004)
Vfb2 (IRU3005)
Vfb1 (IRU3005)
Input bias current
Lin1 or Lin2 Drive Current
CL=3000pF
V5
V12
20
14
CL=3000pF
CL=3000pF
CL=3000pF
100
70
70
200
100
130
300
nS
nS
nS
Ct=150pF
190
220
250
0.2
Khz
V
V
1.522
V
2
V
µA
mA
mA
V5
1.477
1.500
2.500
50
Note 1: Vs refers to the set point voltage given in Table 1.
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
D2
D1
D0
Vs
D4
D3
D2
D1
D0
Vs
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Table 1 - Set point voltage vs. VID codes
Rev. 1.2
12/8/00
4-5
IRU3004, IRU3005
PIN DESCRIPTIONS
PIN# PIN SYMBOL
PIN DESCRIPTION
19
D0
LSB input to the DAC that programs the output voltage. This pin can be pulled up
externally by a 10k resistor to either 3.3V or 5V supply.
18
D1
Input to the DAC that programs the output voltage. This pin can be pulled up externally
by a 10kΩ resistor to either 3.3V or 5V supply.
17
D2
Input to the DAC that programs the output voltage. This pin can be pulled up externally
by a 10k resistor to either 3.3V or 5V supply.
16
D3
MSB input to the DAC that programs the output voltage. This pin can be pulled up
externally by a 10k resistor to either 3.3V or 5V supply.
15
D4
This pin selects a range of output voltages for the DAC. When in the LOW state the
range is 1.3V to 2.05V. For VID codes of all "1" the IRU3004 keeps all the outputs on.
6
PGd
This pin is an open collector output that switches LO when the output of the converter is not within ±10% (typ) of the nominal output voltage. When PWRGD pin switches
LO the sat voltage is less than 0.4V at 3mA.
14
Vfb3
This pin is connected directly to the output of the Core supply to provide feedback to the
Error comparator.
8
CS+
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis
tor programs the C.S threshold depending on the RDS of the power MOSFET. An
external capacitor is placed in parallel with the programming resistor to provide high
frequency noise filtering.
7
CS-
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
13
SS
This pin provides the soft start for the switching regulator. An internal current source
charges an external capacitor that is connected from this pin to the GND which ramps
up the outputs of the switching regulator, preventing the outputs from overshooting as
well as limiting the input current. The second function of the Soft Start cap is to provide
long off time (HICCUP) for the synchronous MOSFET during current limiting.
1
Ct
This pin programs the oscillator frequency in the range of 50kHZ to 500kHZ with an
external capacitor connected from this pin to the GND.
2
Lin1
This pin controls the gate of an external transistor for either the GTL+ linear regulator or
Clock supply.
3
Vfb1
This pin provides the feedback for the linear regulator that its output drive is Lin1 pin. For
IRU3005, this pin is connected to the 2.5V regulator, eliminating the external dividers.
20
Lin2
This pin controls the gate of an external transistor for either the GTL+ linear regulator or
Clock supply.
4
Vfb2
This pin provides the feedback for the linear regulator that its output drive is Lin2 pin.
10
Gnd
This pin serves as the ground pin and must be connected directly to the ground plane.
A high frequency capacitor (0.1 to 1µF) must be connected from V5 and V12 pins to
this pin for noise free operation.
11
LDrv
Output driver for the synchronous power MOSFET.
9
HDrv
Output driver for the high-side power MOSFET.
12
V12
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (0.1 to 1µF) must be connected directly from this pin
to GND pin in order to supply the peak current to the power MOSFET during the transi
tions.
5
V5
4-6
5V supply voltage.
Rev. 1.2
12/8/00
IRU3004, IRU3005
BLOCK DIAGRAM
Vfb3
Enable
V12
Vset
V12
HDrv
Enable
UVLO
PWM
Control
V5
+
Vset
D0
D1
D2
D3
D4
Enable
5Bit
DAC,
Ctrl
Logic
V12
Slope
Comp
LDrv
Osc
CS-
Soft
Start &
Fault
Logic
CS+
Over
Current
200uA
Enable
Ct / En
Vfb2
SS
Lin2
1.1Vset
PGd
1.5V
Lin1
Gnd
0.9Vset
Vfb1
3004blk2-1.3
Figure 1 - Simplified block diagram of the IRU3004
Rev. 1.2
12/8/00
4-7
IRU3004, IRU3005
TYPICAL APPLICATION
Pentium III
L1
L2
Q1
5V
R16
C5
C7
C13
Vout 3
R17
R1
Q2
C3
R2
C16
R4
C10
R3
R12
R13
3.3V
C4
C6
Q3
Vout 1
12V
C11
12
V12
R18
5
V5
8
CS+
9
HDrv
7
CS-
11
LDrv
10
Gnd
14
Vfb3
1 Ct
R7
R11
Lin1 2
13 SS
C2
D4
15
Vfb1 3
D3
16
D2
17
D1
18
D0
19
R8
C15
IRU3004
C1
PGd
6
Vfb2
4
Lin2
20
Q4
Vout 2
C9
C12
R14
VID4
3004app2-2.0
VID3
R9
3.3V
C14
R15
VID2
VID1
R5
VID0
Power Good
C8
Figure 2 - Typical application of IRU3004 or IRU3005 in an on-board DC-DC converter providing the
Core, GTL+, and Clock supplies for the Pentium II microprocessor
Part #
IRU3004
IRU3005
R7 Value
See Parts List
Short
R8 Value
See Parts List
Open
Table 2 - Describes the differences between IRU3004 and IRU3005 applications
4-8
Rev. 1.2
12/8/00
IRU3004, IRU3005
IRU3004/IRU3005 Application Parts List
Ref Design Description
Qty
Part #
Manuf
Q1
MOSFET
1
IRL3103S, TO-263 package
IR
Q2
MOSFET
1
IRL3103D1S, TO-263 package
IR
Q3
Bipolar Trans, GP
1
MPS2222A, SOT-23 package
Q4
MOSFET
1
IRLR024, TO-252 package
L1
Inductor
1
L=1µH, 5052 core with 4 turns of 1.0mm wire
MicroMetal
L2
Inductor
1
L=2.7µH, 5052B core with 7 turns of 1.2mm wire
Micro Metal
C1
Capacitor, Ceramic
1
150pF, 0603
C2, 6
Capacitor, Ceramic
2
1uF, 0603
C3
Capacitor, Electrolytic
2
10MV1200GX, 1200µF,10V
C4
Capacitor, Ceramic
1
1µF, 0805
C5
Capacitor, Ceramic
1
220pF, 0603
C7, 14, 15 Capacitor, Ceramic
3
1000pF, 0603
Motorola
IR
Sanyo
C8
Capacitor, Ceramic
1
0.1µF, 0603
C9
Capacitor, Electrolytic
1
6MV1000GX, 1000µF, 6.3V
Sanyo
C10
Capacitor, Electrolytic
6
6MV1500GX, 1500µF, 6.3V
Sanyo
C11
Capacitor, Electrolytic
1
6MV150GX, 150µF, 6.3V
Sanyo
C12
Capacitor, Electrolytic
1
6MV1000GX, 1000µF, 6.3V
Sanyo
C13
Capacitor, Electrolytic
1
10MV470GX, 470µF, 10V
Sanyo
C16
Capacitor, Ceramic
1
4.7µF, 1206
R1
Resistor
1
3.3kΩ, 5%, 0603
R2, 3, 4
Resistor
3
4.7Ω, 5%, 1206
R5, 15
Resistor
2
10kΩ, 5%, 0603
R7, 12
Resistor
2
100Ω, 1%, 0603
R8
Resistor
1
150Ω, 1%, 0603
R9, 11, 14 Resistor
3
100Ω, 5%, 0603
R13
Resistor
1
22kΩ, 1%, 0603
R16
Resistor
1
220Ω, 1%, 0603
R17
Resistor
1
330Ω, 1%, 0603
R18
Resistor
1
10Ω, 5%, 0603
Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU transient voltage
Note 2: R14 and R15 set the 1.5V approximately 1% higher to account for the trace resistance drop
Rev. 1.2
12/8/00
4-9
IRU3004, IRU3005
TYPICAL APPLICATION
Pentium with AGP
L1
L2
Q1
5V
R16
C5
R1
C7
C13
Vout 3
R17
Q2
C3
R2
C16
R4
C10
R3
R12
R13
3.3V
C4
Q3
C6
C9
12V
12
V12
R18
5
V5
8
CS+
9
HDrv
7
CS-
11
LDrv
10
Gnd
1 Ct
C11
14
Vfb3
R7
R11
Lin1 2
C15
IRU3004
C1
13 SS
C2
D4
15
R8
Vfb1 3
D3
16
D2
17
D1
18
D0
19
PGd
6
Vfb2
4
Lin2
20
Q4
3.3V
C12
R9
VID4
R14
VID3
C14
3.3V
3004app3-1.4
VID2
R15
VID1
R5
VID0
Power Good
C8
Figure 3 - Typical application of IRU3004 in a Pentium with AGP where the power dissipation of the 3.3V
linear regulator is equally distributed between Q3 and Q4 pass transistors. This equal distribution is
possible by accurately regulating the first regulator using the IRU3004 linear controller and its internal
1% reference voltage while the second controller regulates the output of the first regulator from 4.17V to
3.3V, thereby distributing the power dissipation equally.
4-10
Rev. 1.2
12/8/00
IRU3004, IRU3005
IRU3004 Application Parts List
Ref Desig Description
Q1
MOSFET
Qty
1
Part #
IRL3103s, TO-263 package
Manuf
IR
Q2
MOSFET
1
IRL3103D1S, TO-263 package
IR
Q3,4
MOSFET
2
IRL3303S, TO-263 package
IR
L1
Inductor
1
L=1µH, 5052 core with 4 turns of
L2
Inductor
1
Micro Metal
1.0mm wire
L=2.7µH, 5052B core with 7 turns of
Micro Metal
1.2mm wire
C1
Capacitor, Ceramic
1
150pF, 0603
C2,6
Capacitor, Ceramic
2
1µF, 0603
C3
Capacitor, Electrolytic
2
10MV1200GX, 1200µF,10V
C4
Capacitor, Ceramic
1
1µF, 0805
C5
Capacitor, Ceramic
1
220pF, 0603
C7,14,15
Capacitor, Ceramic
3
1000pF, 0603
C8
Capacitor, Ceramic
1
0.1µF, 0603
C9
Capacitor, Electrolytic
1
6MV1000GX, 1000µF, 6.3V
Sanyo
C10
Capacitor, Electrolytic
6
6MV1500GX, 1500µF, 6.3V
Sanyo
Sanyo
C11
Capacitor, Electrolytic
1
6MV150GX, 150µF, 6.3V
Sanyo
C12
Capacitor, Electrolytic
1
6MV1000GX, 1000µF, 6.3V
Sanyo
C13
Capacitor, Electrolytic
1
10MV470GX, 470µF, 10V
Sanyo
C16
Capacitor, Ceramic
1
4.7µF, 1206
R1
Resistor
1
3.3kΩ, 5%, 0603
R2,3,4
Resistor
3
4.7Ω, 5%, 1206
R5,15
Resistor
2
10kΩ, 5%, 0603
R7
Resistor
1
267Ω, 1%, 0603
R8
Resistor
2
150Ω, 1%, 0603
R9,11,14
Resistor
3
100Ω, 5%, 0603
R12
Resistor
1
100Ω, 1%, 0603
R13
Resistor
1
22kΩ, 1%, 0603
R16
Resistor
1
220Ω, 1%, 0603
R17
Resistor
1
330Ω, 1%, 0603
R18
Resistor
1
10Ω, 5%, 0603
Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU transient voltage
Rev. 1.2
12/8/00
4-11
IRU3004, IRU3005
APPLICATION INFORMATION
An example of how to calculate the components for the
application circuit is given below.
Assuming, two sets of output conditions that this regulator must meet,
a) Vo=2.8V, Io=14.2A, ∆Vo=185mV, ∆Io=14.2A
b) Vo=2V, Io=14.2A, ∆Vo=140mV, ∆Io=14.2A
The regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total ∆Vo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output voltage, then the maximum ESR of the output capacitor is
calculated as:
ESR ≤
100
= 7 mΩ
14.2
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX,
1500µF, 6.3V has an ESR of less than 36mΩ typical.
Selecting 6 of these capacitors in parallel has an ESR
of ≈6mΩ which achieves our low ESR goal.
Other type of Electrolytic capacitors from other manufacturers to consider are the Panasonic FA series or the
Nichicon PL series.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
when transitioning from light load to full load and vice
versa. To accomplish this, the output of the regulator is
typically set about half the DC drop that results from
light load to full load. For example, if the total resistance
from the output capacitors to the Slot 1 and back to the
GND pin of the device is 5mΩ and if the total ∆I, the
change from light load to full load is 14A, then the output
voltage measured at the top of the resistor divider which
is also connected to the output capacitors in this case,
must be set at half of the 70mV or 35mV higher than the
DAC voltage setting. This intentional voltage level
4-12
shifting during the load transient eases the requirement
for the output capacitor ESR at the cost of load regulation. One can show that the new ESR requirement eases
up by half the total trace resistance. For example, if the
ESR requirement of the output capacitors without voltage level shifting must be 7mΩ, then after level shifting
the new ESR will only need to be 9.5mΩ if the trace
resistance is 5mΩ (7+5/2=9.5). However, one must be
careful that the combined “voltage level shifting” and the
transient response is still within the maximum tolerance
of the Intel specification. To insure this, the maximum
trace resistance must be less than:
Rs≤ 2(Vspec - 0.02*Vo - ∆Vo)/∆I
Where :
Rs=Total maximum trace resistance allowed
Vspec=Intel total voltage spec
Vo=Output voltage
∆Vo=Output ripple voltage
∆I=load current step
For example, assuming:
Vspec=±140 mV=±0.1V for 2V output
Vo=2V
∆Vo=assume 10mV=0.01V
∆I=14.2A
Then the Rs is calculated to be:
Rs≤ 2(0.140 - 0.02*2 - 0.01)/14.2=12.6mΩ
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6mΩ,
the
power
dissipated
is
(Io^2)*Rs=(14.2^2)*12.6=2.54W. This is a lot of power to
be dissipated in a system. So, if the Rs=5mΩ, then the
power dissipated is about 1W which is much more acceptable. If level shifting is not implemented, then the
maximum output capacitor ESR was shown previously
to be 7mΩ which translated to ≈ 6 of the 1500µF,
6MV1500GX type Sanyo capacitors. With Rs=5mΩ, the
maximum ESR becomes 9.5mΩ which is equivalent to
≈ 4 caps. Another important consideration is that if a
trace is being used to implement the resistor, the power
dissipated by the trace increases the case temperature
of the output capacitors which could seriously effect the
life time of the output capacitors.
Output Inductor Selection
The output inductance must be selected such that under low line and the maximum output voltage condition,
the inductor current slope times the output capacitor
ESR is ramping up faster than the capacitor voltage is
Rev. 1.2
12/8/00
IRU3004, IRU3005
drooping during a load current step. However, if the inductor is too small, the output ripple current and ripple
voltage become too large. One solution to bring the ripple
current down is to increase the switching frequency,
however that will be at the cost of reduced efficiency and
higher system cost. The following set of formulas are
derived to achieve the optimum performance without
many design iterations.
The maximum output inductance is calculated using the
following equation:
L = ESR * C * ( Vinmin - Vomax ) / ( 2* ∆I )
Where:
Vinmin = Minimum input voltage
For Vo = 2.8 V , ∆I = 14.2 A
L =0.006 * 9000 * ( 4.75 - 2.8) / (2 * 14.2) = 3.7µH
Assuming that the programmed switching frequency is
set at 200KHZ, an inductor is designed using the
Micrometals’ powder iron core material. The summary
of the design is outlined below:
The selected core material is Powder Iron, the selected
core is T50-52D from Micro Metal wounded with 8 turns
of # 16 AWG wire, resulting in 3µH inductance with ≈ 3
mΩ of DC resistance.
Assuming L = 3µH and the switching frequency; Fsw =
200KHZ , the inductor ripple current and the output ripple
voltage is calculated using the following set of equations:
T = 1/Fsw
T ≡ Switching Period
D ≈ ( Vo + Vsync ) / ( Vin - Vsw + Vsync )
D ≡ Duty Cycle
Ton = D * T
Vsw ≡ High side Mosfet ON Voltage = Io * RDS
RDS ≡ Mosfet On Resistance
Toff = T - Ton
Vsync ≡ Synchronous MOSFET ON Voltage=Io * RDS
∆Ir = ( Vo + Vsync ) * Toff /L
∆Ir ≡ Inductor Ripple Current
∆Vo = ∆Ir * ESR
∆Vo ≡Output Ripple Voltage
In our example for Vo = 2.8V and 14.2 A load, assuming
IRL3103 MOSFET for both switches with maximum onresistance of 19mΩ, we have:
T = 1 / 200000 = 5µSec
Vsw =Vsync= 14.2*0.019=0.27 V
D ≈ ( 2.8 + 0.27 ) / ( 5 - 0.27 + 0.27 ) = 0.61
Ton = 0.61 * 5 = 3.1µSec
Toff = 5 - 3.1 = 1.9µSec
∆Ir = ( 2.8 + 0.27 ) * 1.9 / 3 = 1.94A
∆Vo = 1.94 * .006 = .011 V = 11mV
Rev. 1.2
12/8/00
Power Component Selection
Assuming IRL3103 MOSFETs as power components,
we will calculate the maximum power dissipation as follows:
For high-side switch the maximum power dissipation
happens at maximum Vo and maximum duty cycle.
Dmax ≈ ( 2.8 + 0.27 ) / ( 4.75 - 0.27 + 0.27 ) = 0.65
Pdh = Dmax * Io^2*RDS(max)
Pdh= 0.65*14.2^2*0.029=3.8 W
RDS(max)=Maximum RDS(on) of the MOSFET at 125°C
For synch MOSFET, maximum power dissipation happens at minimum Vo and minimum duty cycle.
Dmin ≈ ( 2 + 0.27 ) / ( 5.25 - 0.27 + 0.27 ) = 0.43
Pds = (1-Dmin)*Io^2*RDS(max)
Pds=(1 - 0.43) * 14.2^2 * 0.029 = 3.33 W
Heatsink Selection
Selection of the heat sink is based on the maximum
allowable junction temperature of the MOSFETS. Since
we previously selected the maximum RDS(on) at 125°C,
then we must keep the junction below this temperature.
Selecting TO-220 package gives θjc=1.8°C/W (from the
venders’ datasheet ) and assuming that the selected
heatsink is black anodized, the heat-sink-to-case thermal resistance is; θcs=0.05°C/W, the maximum heat
sink temperature is then calculated as:
Ts = Tj - Pd * (θjc + θcs)
Ts = 125 - 3.82 * (1.8 + 0.05) = 118 °C
With the maximum heat sink temperature calculated in
the previous step, the heat-sink-to-air thermal resistance
(θsa) is calculated as follows:
Assuming Ta=35 °C
∆T = Ts - Ta = 118 - 35 = 83 °C Temperature Rise
Above Ambient
θsa = ∆T/Pd
θsa = 83 / 3.82 = 22 °C/W
Next, a heat sink with lower θsa than the one calculated
in the previous step must be selected. One way to do
this is to simply look at the graphs of the “Heat Sink
Temp Rise Above the Ambient” vs. the “Power Dissipation” given in the heatsink manufacturers’ catalog and
select a heat sink that results in lower temperature rise
than the one calculated in previous step. The following
heat sinks from AAVID and Thermalloy meet this criteria.
Co.
Part #
Thermalloy
6078B
AAVID
577002
4-13
IRU3004, IRU3005
Following the same procedure for the Schottky diode
results in a heatsink with θsa = 25 °C/W. Although it is
possible to select a slightly smaller heatsink, for simplicity the same heatsink as the one for the high side
MOSFET is also selected for the synchronous MOSFET.
Note that since the MOSFETs RDS(on) increases with
temperature, this number must be divided by ≈ 1.5, in
order to find the RDS(on) max at room temperature. The
Motorola MTP3055VL has a maximum of 0.18Ω RDS(on)
at room temperature, which meets our requirement.
Switcher Current Limit Protection
To select the heatsink for the LDO MOSFET the first
step is to calculate the maximum power dissipation of
the device and then follow the same procedure as for the
switcher.
The PWM controller uses the MOSFET RDS(on) as the
sensing resistor to sense the MOSFET current and compares to a programmed voltage which is set externally
via a resistor (Rcs) placed between the drain of the
MOSFET and the “CS+” terminal of the IC as shown in
the application circuit. For example, if the desired current limit point is set to be 22A and from our previous
selection, the maximum MOSFET RDS(on)=19mΩ, then
the current sense resistor, Rcs is calculated as:
Pd = ( Vin - Vo ) * IL
Where :
Pd = Power Dissipation of the Linear Regulator
IL = Linear Regulator Load Current
For the 1.5V and 2A load:
Vcs=IcL*Rds=22*0.019=0.418V
Rcs=Vcs/Ib=(0.418V)/(200uA)=2.1kΩ
Where: Ib=200µA is the internal current setting of the
device
Pd = (3.3 - 1.5)*2=3.6 W
Assuming Tj-max=125°C
Ts = Tj - Pd * (θjc + θcs)
Ts = 125 - 3.6 * (1.8 + 0.05) = 118 °C
Switcher Timing Capacitor Selection
The switching frequency can be programmed using an
external timing capacitor. The value of Ct can be approximated using the equation below:
35
. × 10 −5
FSW ≈
CT
Where:
Where :
Cr = Timing Capacitor
FSW = Switching Frequency
If, FSW = 200kHz:
35
. × 10− 5
CT ≈
= 175 pF
200 × 10 3
With the maximum heat sink temperature calculated in
the previous step, the heat-sink-to-air thermal resistance
(θsa) is calculated as follows:
Assuming Ta=35 °C
∆T = Ts - Ta = 118 - 35 = 83 °C Temperature Rise
Above Ambient
θsa = ∆T/Pd
θsa = 83 / 3.6 = 23 °C/W
The same heat sink as the one selected for the switcher
MOSFETs is also suitable for the 1.5V regulator. It is
also possible to use TO-263 package or even the
MTD3055VL in D-Pak if the load current is less than
1.5A. For the 2.5V regulator since the dropout voltage is
only 0.8V and the load current is less than 0.5A, for
most applications the same MOSFET without heat sink
or for low cost applications, one can use PN2222A in
TO-92 or SOT-23 package.
LDO Power MOSFET Selection
LDO Regulator Component Selection
The first step in selecting the power MOSFET for the
linear regulators is to select its maximum RDS(on) based
on the input to output Dropout voltage and the maximum
load current.
RDS(max) = (V in - Vo) / IL
For Vo = 1.5V, and Vin = 3.3V , IL=2A
RDS(max) = (3.3 - 1.5)/2= 0.9Ω
4-14
Since the internal voltage reference for the linear regulators is set at 1.5V for all devices, there is no need to
divide the output voltage for the 1.5V, GTL+ regulator.
Rev. 1.2
12/8/00
IRU3004, IRU3005
For the 2.5V, Clock supply the resistor dividers are selected per following:
Vo=(1+Rt/Rb)*Vref
Where:
Rt=Top resistor divider
Rb=Bottom resistor divider
Vref=1.5V typical
Assuming Rt=100Ω, for Vo=2.5V
Rb=Rt / [(Vo/Vref) - 1]
Rb=100 / [(2.5/1.5) - 1]=150Ω
For 1.5V output, Rt can be shorted and Rb left open.
However, it is recommended to leave the resistor dividers as shown in the typical application circuit so that
the output voltage can be adjusted higher to account for
the trace resistance in the final board layout.
It is also recommended that an external filter be added
on the linear regulators to reduce the amount of the high
frequency ripple at the output of the regulators. This can
simply be done by the resistor capacitor combination
as shown in the application circuit.
For IRU3005 that includes the resistor dividers internally,
Vfb1 can be directly connected to the output voltage
without any external resistors for a preset voltage of 2.5V.
The disadvantage is that the output voltage is not adjustable anymore. The application circuit given for
Pentium II can use either the IRU3004 or IRU3005 family of parts for maximum flexibility.
Disabling the LDO Regulators
14A, then the output voltage measured at the top of the
resistor divider which is also connected to the output
capacitors in this case, must be set at half of the 70 mV
or 35mV higher than the DAC voltage setting. To do this,
the top resistor of the resistor divider (R12 in the application circuit) is set at 100Ω, and the R13 is calculated.
For example, if DAC voltage setting is for 2.8V and the
desired output under light load is 2.835V, then R13 is
calculated using the following formula:
R13= 100*{Vdac /(Vo - 1.004*Vdac)} [Ω]
R13= 100*{2.8 /(2.835 - 1.004*2.800)} = 11.76 kΩ
Select 11.8 kΩ , 1%
Note: The value of the top resistor must not exceed 100Ω.
The bottom resistor can then be adjusted to raise the
output voltage.
Soft Start Capacitor Selection
The soft start capacitor must be selected such that during the start up when the output capacitors are charging
up, the peak inductor current does not reach the current
limit threshold. A minimum of 1µF capacitor insures this
for most applications. An internal 10µA current source
charges the soft start capacitor which slowly ramps up
the inverting input of the PWM comparator Vfb3. This
insures the output voltage to ramp at the same rate as
the soft start cap thereby limiting the input current. For
example, with 1µF and the 10µA internal current source
the ramp up rate is (∆V/ ∆t)=I/C = 1V/100mS. Assuming that the output capacitance is 9000µF, the maximum start up current will be:
The LDO controllers can easily be disabled by connecting the feedback pins, Vfb1 and Vfb2 to a voltage higher
than 2.5V such as 5V for all devices.
I=9000µF*(1V/100mS)=0.09A
Switcher Output Voltage Adjust
It is highly recommended to place an inductor between
the system 5V supply and the input capacitors of the
switching regulator to isolate the 5V supply from the
switching noise that occurs during the turn on and off of
the switching components. Typically an inductor in the
range of 1 to 3µH will be sufficient in this type of application.
As it was discussed earlier, the trace resistance from
the output of the switching regulator to the Slot 1 can be
used to the circuit advantage and possibly reduce the
number of output capacitors, by level shifting the DC
regulation point when transitioning from light load to full
load and vice versa. To account for the DC drop, the
output of the regulator is typically set about half the DC
drop that results from light load to full load. For example,
if the total resistance from the output capacitors to the
Slot 1 and back to the GND pin of the part is 5mΩ and if
the total ∆I, the change from light load to full load is
Rev. 1.2
12/8/00
Input Filter
Switcher External Shutdown
The best way to shutdown the switcher is to pull down
on the soft start pin using an external small signal transistor such as 2N3904 or 2N7002 small signal MOSFET.
This allows slow ramp up of the output, the same as the
power up.
4-15
IRU3004, IRU3005
Layout Considerations
Switching regulators require careful attention to the layout of the components, specifically power components
since they switch large currents. These switching components can create large amount of voltage spikes and
high frequency harmonics if some of the critical components are far away from each other and are connected
with inductive traces. The following is a guideline of how
to place the critical components and the connections
between them in order to minimize the above issues.
8) Place R11, C15, Q3 and C11 close to each other and
do the same with R9, C14, Q4 and C12.
Note: It is better to place the linear regulator components close to the IC and then run a trace from the
output of each regulator to its respective load such
as 2.5V to the clock and 1.5V for GTL + termination.
However, if this is not possible then the trace from
the linear drive output pins, pins 2 and 20 must be
routed away from any high frequency data signals.
Start the layout by first placing the power components:
1) Place the input capacitors C3 and the high side
MOSFET, Q1 as close to each other as possible
It is critical, to place high frequency ceramic capacitors close to the clock chip and termination resistors
to provide local bypassing.
2) Place the synchronous MOSFET, Q2 and the Q1 as
close to each other as possible with the intention
that the source of Q1 and drain of the Q2 has the
shortest length.
9) Place timing capacitor C1 close to pin 1 and soft
start capacitor C2 close to pin 13.
3) Place the snubber R4 & C7 between Q1 & Q2.
Note: It is extremely important that no data bus should
be passing through the switching regulator section specifically close to the fast transition nodes such as PWM
drives or the inductor voltage.
4) Place the output inductor, L2 and the output capacitors, C10 between the MOSFET and the load with
output capacitors distributed along the slot 1 and
close to it.
5) Place the bypass capacitors, C4 and C6 right next to
12V and 5V pins. C4 next to the 12V, pin 12 and C6
next to the 5V, pin 5.
6) Place the controller IC such that the PWM output
drives, pins 9 and 11 are relatively short distance from
gates of Q1 and Q2.
7) Place resistor dividers, R7 & R8 close to pin 3, R12
& R13 (note 1) close to pin 14 and R14 and R15
(note 1) close to pin 20.
Note 1: Although, the PWM controller does not require R12-15 resistors, and the feedback pins 3 and
14 can be directly connected to their respective outputs, they can be used to set the outputs slightly
higher to account for any output drop at the load due
to the trace resistance.
Component connections:
Using the 4 layer board, dedicate on layer to GND, another layer as the power layer for the 5V, 3.3V, Vcore,
1.5V and if it is possible for the 2.5V.
Connect all grounds to the ground plane using direct
vias to the ground plane.
Use large low inductance/low impedance plane to connect the following connections either using component
side or the solder side.
a) C3 to Q1 Drain
b) Q1 Source to Q2 Drain
c) Q2 drain to L2
d) L2 to the output capacitors, C10
e) C10 to the slot 1
f) Input filter L1 to the C3
g) C9 to Q4 drain
h) C12 to the Q4 source
Connect the rest of the components using the shortest
connection possible.
4-16
Rev. 1.2
12/8/00