a FEATURES Stand-Alone Li-Ion Battery Chargers High End-of-Charge Voltage Accuracy ⴞ0.4% @ +25ⴗC ⴞ0.75% @ –10ⴗC to +70ⴗC Intelligent End-of-Charge Output Signal Pin Programmable Cell Number Select On Chip 3.3 V LDO Regulator Programmable Charge Current with High Side Sense Softstart Charge Current Undervoltage Lockout Drives External PMOS ⴞ10% Adjustable End-of-Charge Voltage Charges NiCad, NiMH (with External Controller) PWM Oscillator Frequency: ADP3801: 200 kHz ADP3802: 500 kHz APPLICATIONS Fast Chargers Universal Chargers Cellular Phones Portable Computers Portable Instrumentation Desktop Chargers Personal Digital Assistants High Frequency Switch Mode Dual Li-Ion Battery Chargers ADP3801/ADP3802 FUNCTIONAL BLOCK DIAGRAM VL SD VCC DRV EOC CS+ CS– LDO + REFERENCE GATE DRIVE CURRENT LOOP AMP + EOC COMPARATOR SHUTDOWN UVLO + RESET RESET PWM A/B A/B SELECT MUX BATA BATB ISET FINAL BATTERY VOLTAGE PROGRAM (4.2, 8.4, 12.6) PROG SD\UVLO ADP3801/ADP3802 GND BATTERY VOLTAGE ADJUST 610% VOLTAGE LOOP AMP ADJ COMP 68mH 40mV VIN BATA BATB GENERAL DESCRIPTION The ADP3801 and ADP3802 are complete battery charging ICs. The devices combine a high accuracy final battery voltage control with a constant charge current control and an on-board Low Drop-Out Regulator (LDO). The accuracy of the final battery voltage control is guaranteed to ± 0.75% to safely charge Li-Ion batteries. An internal multiplexer allows the alternate charging of two separate battery stacks. The final voltage is pin programmable to one of three Li-Ion options: 4.2 V (one Li-Ion cell), 8.4 V (two Li-Ion cells), or 12.6 V (three Li-Ion cells). Paired with an external microcontroller for charge termination, the ADP3801/ADP3802 works as a fast charger for NiCad/ NiMH batteries or as a universal charger for all three battery chemistries. In addition, a pin is provided for changing the final battery voltage by up to ± 10% to adjust for variations in battery chemistry from different Li-Ion manufacturers without loss of accuracy in the final battery voltage. VCC DRV EOC CS+ CS– A/B 3.3V BATA VL BATB ADP3801/ADP3802 SD ISET RESET PROG GND COMP ADJ Figure 1. 4 Amp Dual Battery Charger REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADP3801/ADP3802–SPECIFICATIONS(@ –40ⴗC ≤ T ≤ +85ⴗC, VCC = 10.0 V, unless otherwise noted) A Parameter FINAL BATTERY VOLTAGE One Li-Ion Cell Two Li-Ion Cells1 Three Li-Ion Cells1 BATTERY PROGRAMMING INPUT (PROG) One Li-Ion Cell (4.2 V) Two Li-Ion Cells (8.4 V) Three Li-Ion Cells (12.6 V) Fail Safe Voltage (4.2 V) PROG Input Current Conditions Symbol Min Typ Max Units PROG = VT1, ADJ = VL, TA = +25°C PROG = VT1, ADJ = VL, –10°C ≤ TA ≤ +70°C PROG = VT1, ADJ = VL, –40°C ≤ TA ≤ +85°C PROG = VT2, ADJ = VL, TA = +25°C PROG = VT2, ADJ = VL, –10°C ≤ TA ≤ +70°C PROG = VT2, ADJ = VL, –40°C ≤ TA ≤ +85°C PROG = VT3, ADJ = VL, TA = +25°C PROG = VT3, ADJ = VL, –10°C ≤ TA ≤ +70°C PROG = VT3, ADJ = VL, –40°C ≤ TA ≤ +85°C VBAT VBAT VBAT VBAT VBAT VBAT VBAT VBAT VBAT 4.180 4.168 4.150 8.366 8.337 8.300 12.550 12.505 12.450 4.200 4.220 4.232 4.250 8.434 8.463 8.500 12.650 12.695 12.750 V V V V V V V V V VT1 VT2 VT3 0.00 1.00 2.05 3.10 0.20 1.20 2.30 3.30 5 V V V V µA Defaults to 1 Li-Ion Cell IB A/B SELECT MUX Select Battery BATB Select Battery BATA A/B Input Current BATA or BATB Input Resistance Channel Selected BATA or BATB Input Current Channel Not Selected BATA or BATB Shutdown Current Part in Shutdown VIH VIL IIN RIN IBA, IBB IBA, IBB 8.400 12.600 1.5 2.0 185 0.02 265 0.2 0.2 BATTERY ADJUST INPUT 2 (ADJ) % of Final Battery Voltage % of Final Battery Voltage ADJ Disable Voltage Threshold ADJ Bias Current ADJ = 1.0 V, –10°C ≤ TA ≤ +70°C ADJ = 2.3 V, –10°C ≤ TA ≤ +70°C 0% Change 1.0 V ≤ ADJ ≤ 2.3 V IB 90 110 2.475 10 OVERVOLTAGE COMPARATOR Trip Point Response Time Percent Above VBAT DRV Goes High tr 8 2 OSCILLATOR 200 kHz Option 500 kHz Option 0% Duty Cycle Threshold 100% Duty Cycle Threshold (ADP3801) (ADP3802) @ COMP Pin @ COMP Pin fOSC fOSC 150 375 CL = 1 nF, VCC – 4 V to 90% CL = 1 nF, 90% to VCC – 4 V VCC – VDRV VCC = 8 V VCC > 8 V tr tf VOH VOL VOL 35 75 275 1.0 2.0 VCC – 7 VCC – 6 VCS+ and VCS– VCS3 0.0 V ≤ VCSCM ≤ VCC – 2 V 0.0 V ≤ VCSCM ≤ VCC – 2 V 0.0 V ≤ VCSCM ≤ VCC – 2 V VCS3 DRV Goes High VCSCM VCSDM VCSVOS VCSIB VCSIOS 0.0 0.0 0.0 V ≤ VISET ≤ 1.65 V VISET = 1.65 V, –10°C ≤ TA ≤ +70°C VISET = 0.10 V, –10°C ≤ TA ≤ +70°C 0.0 V ≤ VISET ≤ 1.65 V VCS /VISET3 GATE DRIVE Rise Time Fall Time Output High Saturation Voltage Output Low Voltage CURRENT SENSE AMPLIFIER Input Common-mode Range Input Differential Mode Range Input Offset Voltage4 Input Bias Current Input Offset Current Over Current Trip Point Response Time ISET INPUT Charge Current Programming Function Programming Function Accuracy ISET Bias Current –2– 89 109 –5 –25 91 111 2.6 100 % % V nA % µs 250 625 0.1 ± 1.0 ± 10 15 kHz kHz V V ns ns mV V V VCC – 2 185 1 0.3 0.01 185 2 tr IB 200 500 1.0 2.0 1 1 V V µA kΩ µA µA 0.8 1 1 0.15 +5 +25 100 V mV mV µA µA mV µs V/V % % nA REV. 0 ADP3801/ADP3802 Parameter Conditions Symbol EOC OUTPUT5 Trip Point Hysteresis 100 kΩ to VL 100 kΩ to VL VCS3 VCS3 SHUTDOWN (SD) ON OFF SD Input Current LOW DROPOUT REGULATOR Output Voltage6 Dropout Voltage (VCC – VL) Output Current Drive SDH SDL 0 mA ≤ ILOAD ≤ 10 mA, 4.1 V ≤ VCC ≤ 20 V, –10°C ≤ TA ≤ +70°C 0 mA ≤ ILOAD ≤ 10 mA, 4.1 V ≤ VCC ≤ 20 V, –40°C ≤ TA ≤ +85°C ILOAD = 10 mA RESET OUTPUT VL Rising Threshold VL Falling Threshold Output High Logic Level RESET High RESET Low 1 MΩ to Ground External POWER SUPPLY ON Supply Current OFF Supply Current No External Loads No External Loads UVLO6, 7 VCC Rising Threshold VCC Falling Threshold Turn On Turn Off, IVL = 1 mA Min VL 3.267 VL VDO IVL 3.250 Units mV mV 2.0 0.2 0.8 1 V V µA 3.3 3.333 V 3.350 0.8 V V mA 10 0.4 20 2.5 2.4 2.4 2.7 2.55 2.9 2.9 2.8 V V V 5.0 115 7.0 180 mA µA 3.9 3.4 4.0 V V ISYON ISYOFF 3.8 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. Specifications subject to change without notice. –3– Max 10 0.2 NOTES 1 VCC = VBAT + 2 V. 2 See Figure 5. 3 VCS = (VCS+) – (VCS–). 4 Accuracy guaranteed by ISET INPUT, Programming Function Accuracy specification. 5 EOC Output Comparator monitors charge current, and it is enabled when V BAT ≥ 95% of the final battery voltage. 6 LDO is active during SD and UVLO. 7 Turn-off threshold depends on LDO dropout. REV. 0 Typ ADP3801/ADP3802 ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS* Input Voltage (VCC to GND) . . . . . . . . . . . . . . –0.3 V to 20 V DRV, VCS+, VCS– to GND . . . . . . . . . . . . . . . . –0.3 V to VCC BATA, BATB to GND . . . . . . . . . . . . . . . . . –0.3 V to 14.0 V A/B, ISET, PROG, ADJ to GND . . . . . . . . . . . –0.3 V to VL SD, RESET, COMP, EOC to GND . . . . . . . . . . –0.3 V to VL Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W Ambient Temperature Range . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DRV RESET VCC VL SD CS– CS+ ISET COMP EOC ADJ PROG BATB BATA A/B1 GND External Transistor Drive Power on RESET Output Supply Voltage LDO Output Shutdown Control Input Negative Current Sense Input Positive Current Sense Input Charge Current Program Input External Compensation Node End-of-Charge Output Signal Adjust Battery Voltage ± 10% Program Final Battery Voltage Input Battery “B” Voltage Sense Battery “A” Voltage Sense “A” or “B” Battery Select Input Ground Oscillator Frequency ADP3801AR ADP3802AR R-16A R-16A 200 kHz 500 kHz DRV 1 RESET 2 VCC 3 ADP3801 ADP3802 16 GND 15 A/B 14 BATA VL 4 13 CS– 6 11 ADJ 7 10 EOC ISET 8 9 COMP BATB TOP VIEW SD 5 (Not to Scale) 12 PROG CS+ PIN FUNCTION DESCRIPTIONS Mnemonic Package Option PIN CONFIGURATION NOTES *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA is specified for worst case conditions with device soldered on a circuit board. Pin Number Model NOTE 1 “L” = Battery “A.” CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3801/ADP3802 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 Typical Performance Characteristics–ADP3801/ADP3802 100 VCC = 10V 0.3 40 20 0.2 VBAT ACCURACY – % 60 0.1 0 –0.1 –0.2 –0.4 –40 –0.1 –0.3 0.1 0.3 0.5 –0.4 –0.2 0 0.2 0.4 0.6 VBAT ACCURACY – % Figure 2. VBAT Accuracy Distribution 0 –0.1 0 20 40 60 TEMPERATURE – 8C 80 100 –0.3 6 10 8 10 12 14 16 18 SUPPLY VOLTAGE – Volts 20 Figure 4. VBAT Accuracy vs. Supply Voltage 10 VCC = 10V TA = +258C 200 VCC = 10V VCC = 10V 9 0 –5 THRESHOLD – mV 195 5 THRESHOLD – % VBAT PERCENT CHANGE – % –20 Figure 3. VBAT Accuracy vs. Temperature 15 0.1 –0.2 –0.3 0 –0.5 TA = +258C VBAT = 4.2V 0.2 80 VBAT ACCURACY – % TOTAL NUMBEROF PARTS 0.3 0.4 VCC = 10V TA = +258C 8 7 190 185 6 –10 –15 0 0.5 1.0 1.5 2.0 2.5 VADJ – Volts 3.0 5 –40 3.5 Figure 5. VBAT Percent Change vs. VADJ –20 0 20 40 60 TEMPERATURE – 8C 80 180 –40 100 Figure 6. Overvoltage Comparator Threshold vs. Temperature TA = +258C 0 20 40 60 TEMPERATURE – 8C 80 100 Figure 7. Overcurrent Comparator Threshold vs. Temperature 0.2 0.3 3.7 –20 TA = +258C VCC = 10V 3.5 3.4 LDO ACCURACY – % 3.6 LDO ACCURACY – % UVLO TRIP POINT – Votts 0.2 0.1 0 –0.1 0.1 0 –0.1 –0.2 3.3 0 1 2 3 4 5 6 7 8 LDO LOAD CURRENT – mA 9 10 Figure 8. UVLO Trip Point-Off vs. LDO Load Current REV. 0 –0.3 –40 –0.2 –20 0 20 40 60 TEMPERATURE – 8C 80 Figure 9. LDO Accuracy vs. Temperature –5– 100 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE – Volts 20 Figure 10. LDO Accuracy vs. Supply Voltage ADP3801/ADP3802 0.4 215 0 ADP3801 VCC = 10V TA = +258C CLDO = 1mF VCC = 10V FREQUENCY – kHz –20 0.3 PSRR – dB –40 –60 0.2 195 185 0.1 0 1 2 9 3 4 5 6 7 8 LOAD CURRENT – mA 10 Figure 11. LDO Dropout Voltage vs. Load Current Figure 12. LDO PSRR vs. Frequency 6 DRV – Volts 60 40 4 2 0 1 VCC = 10V CL = 1nF TA = +258C 250ns/DIV 20 1.0 2.0 2.5 VCOMP – Volts 1.5 3.0 CH1 2.00V 3.5 Figure 14. Duty Cycle vs. COMP Pin Voltage M 250ns CH1 TIME – ns 0.2 5.5 3.7 3.6 TA = +858C 5.0 TA = +258C 4.5 TA = –408C 4.0 NOT SWITCHING SD = ON 3.5 40 60 0 20 TEMPERATURE – 8C 80 100 Figure 17. DRV Output Low Voltage with VCC = 10 V vs. Temperature 40 60 0 20 TEMPERATURE – 8C 80 100 15 POWER SUPPLY CURRENT – mA POWER SUPPLY CURRENT – mA CLAMP VOLTAGE – Volts 3.8 –20 Figure 16. DRV High Saturation Voltage vs. Temperature VCC = 10V –20 100 0.3 0 –40 9.40V Figure 15. DRV Rise and Fall Times 3.9 3.5 –40 80 VCC = 10V 10 8 0.5 0 20 40 60 TEMPERATURE – 8C 0.4 80 0 –20 Figure 13. Oscillator Frequency vs. Temperature 12 VCC = 10V TA = +258C 0 175 –40 –100 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 FREQUENCY – Hz 100 DUTY CYCLE – % 205 –80 SATURATION VOLTAGE – Volts DROPOUT VOLTAGE – Volts TA = +258C 4 8 12 16 SUPPLY VOLTAGE – Volts 20 Figure 18. Power Supply Current vs. Supply Voltage @ Three Temperatures –6– VCC = 10V TA = +258C 50% DUTY CYCLE 13 11 ADP3802 9 ADP3801 7 5 0 0.5 1.0 1.5 2.0 CAPACITIVE LOAD – nF 2.5 Figure 19. Power Supply Current vs. Capacitive Load on DRV REV. 0 ADP3801/ADP3802 A 3.3 V LDO is used to generate a regulated supply for internal circuitry. Additionally, the LDO can deliver up to 10 mA of current to power external circuitry such as a microcontroller. An Undervoltage Lockout (UVLO) circuit is included to safely shut down the charging circuitry when the input voltage drops below its minimum rating. A shutdown pin is also provided to turn off the charger when, for example, the battery has been fully charged. The LDO remains active during shutdown or UVLO and has a quiescent current of 110 µA. APPLICATIONS SECTION PRODUCT DESCRIPTION The ADP3801 and ADP3802 are complete Li-Ion battery charging ICs. Combined with a microcontroller, they also function as voltage limited, µC programmable constant current source chargers for NiCad and NiMH chemistries. Utilizing an external PMOS pass transistor, the devices realize a buck type constant current, constant voltage (CCCV) charger controller that is capable of charging two separate battery packs for such applications as portable computer chargers and cellular phone chargers. The Functional Block Diagram shows the ICs’ functional blocks, which are detailed below: Battery Charging Overview Figure 20 shows a simplified Buck type battery charger application circuit for the ADP3801/ADP3802. When a discharged battery is first placed in the charger, the battery voltage is well below the final charge voltage, so the current sense amplifier controls the charge loop in constant current mode. The charge current creates a voltage drop across the sense resistor RCS. This voltage drop is buffered and amplified by amplifier GM1. Amplifier GM2 compares the output of GM1 to an external current control voltage provided at the ISET pin and servos the charger loop to make these voltages equal. Thus, the charge current is programmed using the ISET input voltage. • A/B SELECT MUX—Two-channel multiplexer for charging two battery stacks. • FINAL BATTERY VOLTAGE PROGRAM—Multiplexer to program 4.2 V, 8.4 V, or 12.6 V final battery voltage. • VOLTAGE LOOP AMP—GM-type amplifier to control the final battery voltage. It includes a built-in overvoltage comparator. • EOC COMPARATOR—End-of-charge detection output to signal when the battery is fully charged. The output of GM2 is analog “OR’ed” with the output of GM3, the voltage loop amplifier. Only one or the other amplifier controls the charge loop at any given time. As the battery voltage approaches its final voltage, GM3 comes into balance. As this occurs, the charge current decreases, unbalancing GM2, and control of the feedback loop naturally transfers to GM3. • BATTERY VOLTAGE ADJUST—Amplifier to adjust the final battery voltage up to ± 10%. • CURRENT LOOP AMP—High-side-current-sense amplifier to sense and control the charge current at a programmable level. It includes an overcurrent comparator. The ADP3801/ADP3802 can control the charging of two independent battery stacks or a single battery stack. The A/B SELECT MUX has a logic input to choose between the two batteries. See Figure 31 for more information on dual battery charging. The output of the multiplexer is applied to a precision thin-film resistor string to divide down the battery voltage. The final battery voltage is chosen by selecting the proper resistor divider tap with the PROG multiplexer. The output of this mux goes directly to the input of GM3, comparing the divided down battery voltage to the internal reference. To guarantee ± 0.75% accuracy, a high precision internal reference and high accuracy thin film resistors are used. Including these components onchip saves the significant cost and design effort of adding them externally. • PWM—Pulsewidth modulator and oscillator (ADP3801200 kHz, ADP3802-500 kHz). • GATE DRIVE—Gate drive to control an external pass transistor. It includes a clamp to limit the drive voltage to protect the external PMOS. • LDO + REFERENCE—3.3 V low dropout regulator to supply an external microcrontroller and for on-chip supply. Includes an internal precision reference ( VREF = VL/2). • SHUTDOWN—Logic input to shut down the charger. The LDO remains on. • UVLO—Undervoltage lockout circuit to shut down the charger for low supply voltages. • RESET—Active LOW output to reset external logic on powerup. During charging, the ADP3801/ADP3802 maintains a constant, programmable charge current. The high side current sense amplifier has low offset allowing the use of a low voltage drop for current sensing: 165 mV for the maximum charge current. The input common-mode range extends from ground to VCC – 2 V ensuring current control over the full charging voltage of the battery, including a short circuit condition. A high impedance dc voltage input (ISET) is provided for programming the charge current over a wide range. When the battery voltage approaches its final limit, the part automatically transfers to voltage control mode. Both the current control loop and the voltage control loop share the same compensation pin minimizing the number of external components. An internal comparator monitors the charge current to detect the end-of-charge (EOC). When the current decreases such that VCS ≤ 8 mV, the EOC output pulls low. REV. 0 –7– ADP3801/ADP3802 L RCS D2 VIN CIN DRV VCC EOC BATA RB D1 COUT Rf1 Rf2 A/B CS– CS+ BATA VL MUX 3.3V BATB GM1 LDO (TO mC) PROG VREF RESET (TO mC) SD POWERON RESET VREF VT UVLO GATE DRIVE FINAL VBAT PROG VREF Q FF S BIAS (FROM mC) ISET GM2 R 1mF (FROM mC) 100kV OSCILLATOR GM3 3R (FROM mC) ADJ ADP3801/ADP3802 R 1mF 100kV 2.475V VREF GND COMP Figure 20. Simplified Application Diagram Setting the Final Battery Voltage VL The final battery voltage is determined by the voltage on the Battery Programming (PROG) pin. This pin controls the state of the PROG multiplexer, which selects the appropriate tap from the internal battery voltage resistor divider. The specification table details the PROG voltages for each final battery voltage. A resistor divider from the LDO can be used to set the PROG voltage as shown in Figure 21. To provide fail safe operation, a PROG voltage equal to 0.0 V or 3.3 V results in the minimum final battery voltage of 4.2 V. The PROG input is high impedance, so the voltage can be set with a high impedance resistor divider from VL. Alternatively, a PWM output from a microcontroller can be used with an RC filter to generate the desired threshold voltage. VBAT SETTING 4.2 VT1 = 0.0V R1 (5%) R2 (5%) 8.4 VT2 = 1.1V 200kV 100kV 12.6 VT3 = 2.2V 100kV 200kV R1 PROG R2 0* * CONNECT PROG TO GND FOR VBAT = 4.2V Figure 21. Resistor Divider Sets the Final Battery Voltage –8– REV. 0 ADP3801/ADP3802 The same care must be given to the ground connection for the ADP3801/ADP3802. Any voltage difference between the battery ground and the GND pin will cause an error in the charge voltage. This error includes the voltage drop due to the ground current of the part. Thus, the GND pin should have a thick trace or ground plane connected as close as possible to the battery’s negative terminal. Any current from additional circuitry should be routed separately to the supply return and not share a trace with the GND pin. Adjusting the Final Battery Voltage In addition to the PROG input, the ADP3801/ADP3802 provides an input (ADJ) for fine adjustment of the final battery voltage. For example, the ADJ amplifier allows the nominal 4.2 V per cell setting for Li-Ion battery cells to be adjusted to 4.1 V for certain chemistries. An internal amplifier buffers the ADJ pin and adjusts the internal reference voltage on the input to GM3. Figure 5 shows a graph of the percent change in final battery voltage vs. the ADJ voltage. The linear portion between 0.6 VREF and 1.4 VREF follows the formula below: ( ) ∆VBAT % = VADJ − VREF Dual Battery Operation The ADP3801/ADP3802 is designed to charge two separate battery packs. These batteries can be of different chemistries and have a different number of cells. At any given time, only one of the two batteries is being charged. To select which battery is being monitored, and therefore which battery is being charged, the ADP3801/ADP3802 includes a battery selector mux. This two-channel mux is designed to be “break-beforemake” to ensure that the two batteries are not shorted together momentarily when switching from one to the other. The A/B input is a standard logic input, with a logic low selecting BATA and a logic high selecting BATB. See the application in Figure 31 for more information. × 100 4 VREF The factor of four in the denominator is due to internal scaling. When VADJ is above 2.5 V, an internal comparator switches off the ADJ amplifier, giving a 0% change in VBAT. Whenever the ADJ function is not used it should be connected to VL. The total range of adjustment is ± 10%. For example, the 4.2 V final battery voltage setting can be adjusted from 3.78 V to 4.62 V. Of course, care must be taken not to adjust the final battery voltage to an unsafe charging level for Li-Ion batteries. Follow the battery manufacturers specifications for the appropriate final battery voltage. Never charge a Li-Ion battery above the manufacturers rated maximum! Overvoltage Comparator GM3 includes an overvoltage comparator. Its output bypasses the COMP node to quickly reduce the duty cycle of the PWM to 0% when an overvoltage event occurs. A second output is connected to the COMP node and, with slower response, reduces the voltage on the COMP cap to provide a soft start recovery. The threshold of the comparator is typically 8% above the final battery voltage. This comparator protects external circuitry from any condition that causes the output voltage to quickly increase. The most likely reason is if the battery is suddenly removed while it is being charged with high current. Figure 27 shows the transient response when the battery is removed. Notice that the output voltage increases to the comparator trip point, but it is quickly brought under control and held at the final battery voltage. Voltage Loop Accuracy The ADP3801/ADP3802 guarantees that the battery voltage be within ± 0.75% of the setpoint over the specified temperature range and the specified charge current range. This inclusive specification saves the designer the time and expense of having to design-in additional high accuracy components such as a reference and precision resistors. To maintain the ± 0.75% specification, the layout and design of the external circuitry must be considered. The input impedance of BATA and BATB is typically 265 kΩ, so any additional impedance on these inputs will cause an error. As a result, do not add external resistors to the battery inputs. Furthermore, if the output voltage is being used for other purposes, such as to supply additional circuitry, the current to this circuitry should be routed separately from the sense lines to prevent voltage drops due to impedance of the PC-board traces. In general, route the sense lines as Kelvin connections as close to the positive terminals of the battery as possible. REV. 0 –9– ADP3801/ADP3802 Current Sense Amplifier Overcurrent Comparator A differential, high side current sense amplifier (GM1 in Figure 20) amplifies the voltage drop across a current sense resistor RCS. The input common-mode range of GM1 extends from ground to VCC – 2 V. Sensing to ground ensures current regulation even in short circuit conditions. To stay within the common-mode range of GM1, VCC must be at least 2 V greater than the final battery voltage or a circuit such as shown in Figure 32 must be used. RC filters are included to filter out high frequency transients, which could saturate the internal circuitry. The filter’s cutoff is typically set at half the switching frequency of the oscillator. Similar to the voltage loop, the current loop includes a comparator to protect the external circuitry from an overcurrent event. This comparator trips when GM1’s differential input voltage exceeds 185 mV. Like the overvoltage comparator, it has two outputs to quickly reduce the duty cycle to 0% and to provide a soft-start recovery. The response time of the internal comparator is approximately 1 µs; however, the filter on the input of GM1 may slow down the total response time of the loop. The charge current is controlled by the voltage on the ISET pin according to the following formula: I CHARGE = VISET 10 × RCS The factor of 10 is due the GM1’s gain of 10 V/V. To set a charge current of 1.5 A with RCS = 0.1 Ω, VISET must be 1.5 V. Figure 22 shows the linearity of the charge current control as the voltage is increased from 0 V to the programmed final battery voltage (12.6 V in this case). It is important to state that this curve is taken with an ideal, zero impedance load. An actual Li-Ion battery will exhibit a more gradual drop in charge current due to the internal impedance of the battery as shown in Figure 25. The ADP3801/ADP3802 provides an active low, end-of-charge (EOC) logic output to signal when the battery has completed charging. The typical Li-Ion charging characteristic in Figure 25 shows that when the battery reaches its final voltage the current decreases. To determine EOC, an internal comparator senses when the current falls below 6% of full scale, ensuring that the battery has been fully charged. The comparator has hysteresis to prevent oscillation around the trip point. To prevent false triggering (such as during soft-start), the comparator is only enabled when the battery voltage is within 5% of its final voltage. As the battery is charging up, the comparator will not go low even if the current falls below 6% as long as the battery voltage is below 95% of full scale. Once the battery has risen above 95%, the comparator is enabled. There are two important reasons for this functionality. First, when the circuit is initially powered on, the charge current is zero because of the soft start. If the comparator is not gated by the battery voltage, then EOC would go low erroneously. Second, a provision must be made for battery discharge. Assume that a battery has been fully charged. EOC goes low, and the charger is gated off. When the battery voltage falls to 95%, due to self-discharge for example, EOC will return high. Then the charger can start up and top off the battery, preventing the battery from “floating” at the end-of-charge voltage. 3.5 3.0 2.5 ICHARGE – Amps End-of-Charge Output 2.0 1.5 1.0 0.5 0 2 3 4 5 6 7 8 9 VOUT – Volts 10 11 12 13 Figure 22. CCCV Characteristic with Ideal Load The EOC output has many possible uses as shown in Figure 23. One simple function is to terminate the charging to prevent floating (Figure 23a). It can be used as a logic signal to a microcontroller to indicate that the battery has finished charging. The microcontroller can then switch to the next battery if appropriate or shutdown the ADP3801/ADP3802. It can also be used to turn on an LED to signal charge completion (Figure 23b). Using a flip-flop, EOC can control the switching from BATA to BATB (Figure 23d). The RC filter delays switching between the two batteries to ensure that the output capacitor is discharged. –10– REV. 0 ADP3801/ADP3802 COMP Node Both the current loop and the voltage loop share a common, high impedance compensation node, labeled COMP. A series capacitor and resistor on this node help to compensate both loops. The resistor is included to provide a zero in the loop response and boost phase margin. ADP3800 EOC COMP (a) EOC Output Terminates Charge ADP3800 VL EOC 270V 100kV 2N3906 0.1mF (b) EOC Turns on LED to Signal Charge Completion ADP3800 EOC VL 10kV 270V 2N3906 0.1mF 20kV 20kV The current available to charge and discharge the COMP capacitor during normal operation is 100 µA. Thus, the slew rate at this node is equal to 100 µA divided by the capacitor. For a typical capacitance of 1 µF, the slew rate is 0.1 V/ms. Thus, it takes about 10 ms before the ADP3801/ADP3802 starts to operate from a soft-start state. This is regardless of the internal oscillator frequency. One important note is that the COMP node is a high impedance point. Any external resistance or leakage current on this node will cause an error in both the charge current control and the final battery voltage. Gate Drive COMP 100kV The voltage at the COMP node determines the duty cycle of the PWM. The threshold levels are typically 1.0 V for 0% duty cycle and 2.0 V for 100% duty cycle, resulting in a total range of 1.0 V. When the ADP3801/ADP3802 first turns on, the COMP capacitor is at 0.0 V. It has to charge up to at least 1.0 V before the duty cycle rises above 0% and the pass transistor turns on. This “soft-start” behavior is desirable to avoid undue stress on the external components. In addition, whenever the part is placed in Shutdown or in UVLO, the COMP capacitor is discharged to ensure soft start upon recovery. 2N3904 3 2 100kV (c) EOC Terminates Charge and Turns on LED The ADP3801/ADP3802 gate drive is designed to provide high transient currents to drive the pass transistor. The rise and fall times are typically 20 ns and 200 ns respectively when driving a 1 nF load, which is typical for a PMOSFET with RDS(ON) = 60 mΩ. Figure 15 shows the typical transient response of the output stage driving this load from a 10 V supply. A voltage clamp is added to limit the pull-down voltage to 7 V below VCC. For example, if VCC is 10 V then the output will pull down to 3 V minimum, limiting the VGS voltage applied to the external FET. Low Dropout Regulator and Reference ADP3800 EOC VL COMP RESET 74H73A 100kV 0.1mF 10kV J Q BATSELB* 2N3906 20kV K Q A/B + BATSELA* 100kV 2N3904 3 2 100kV 100kV 1mF Shutdown *LEVEL SHIFTED TO TO DRIVE PMOS (d) Flip-Flop Switches Between Batteries on EOC Signal Figure 23. EOC Output Circuits REV. 0 A 3.3 V LDO is used to generate a regulated supply for internal circuitry. Additionally, the LDO can deliver up to 10 mA of current to power external circuitry such as a microcontroller. A 1.0 µF capacitor must be placed close to the VL pin to ensure stability of the regulator. Due to the design of the regulator, stability is not contingent on the ESR for the output capacitor. Many different types of capacitors can be used providing flexibility and ease of design. The LDO also includes a high accuracy, low drift internal reference equal to half of VL to set levels within the part. During shutdown and UVLO, both the reference and the LDO remain active. The IC may be placed in shutdown at any time to stop charging of the batteries and to conserve power. For example, to safely switch from one battery to the next, the part should be shut down to momentarily interrupt charging. Also, if the batteries have completed charging or no batteries are present, then the part may be placed in shutdown to save power. A logic low on –11– ADP3801/ADP3802 SD results in shutdown. All internal circuitry is shut off except for the LDO and the reference, and the supply current is typically 110 µA. When SD returns high, the part resumes full operation. The compensation capacitor at the COMP node is discharged during shutdown, so the part will resume operation in soft-start mode. on the current sense amplifier. In applications where the input supply does not offer enough headroom, the circuits in Figures 32 and 33 can be used as explained in the section on low overhead charging. Overtemperature Shutdown Undervoltage Lockout—UVLO The internal Undervoltage Lockout (UVLO) circuit monitors the input voltage and keeps the part in shut-down mode until VCC rises above 3.9 V. During UVLO, the LDO and reference are still active, but the analog front end, the oscillator, and the gate drive are off. UVLO helps to prevent the circuitry from entering an unknown state that could incorrectly charge a battery. To prevent oscillation around VCC = 3.9 V, the UVLO circuitry has built-in hysteresis. Once the part is on, the UVLO circuitry does not shut it off until the LDO enters dropout. Because the dropout voltage depends on the LDO’s load, the UVLO trip point-off also depends on the load. Refer to Figure 8 for a graph of the UVLO trip point-off versus LDO load. RESET The ADP3801/ADP3802 has an on-chip temperature detector to shut the part down when the die temperature reaches typically +160°C. Such a condition could occur with a short-circuit on the LDO or a short on the DRV pin. In either case, the operation of the charger will stop and the DRV pin will be pulled high. With approximately +10°C hysteresis, the overtemperature shutdown releases at typically +150°C. These temperatures are higher than the absolute maximum ratings for the die, and are included as a safety feature only. Li-Ion Battery Charger The ADP3801 and ADP3802 are ideally suited for a single or dual Li-Ion batterypack charger. They combine 200 kHz or 500 kHz switching with a PMOS pass transistor drive to realize a Buck topology CCCV charger. The following discussion goes through the complete design of a charger using the ADP3801. This information also applies to the ADP3802. When the power is first applied to the ADP3801/ADP3802, the RESET pin is held at ground by an external 1 MΩ resistor. It remains low until the LDO output voltage rises to above 80% of its final value. When this threshold is reached, the RESET pin is pulled high. The internal RESET comparator includes about 150 mV of hysteresis to avoid oscillation around the threshold. Battery: 3 Series Cell Li-Ion Pack. Input Voltage: VIN = 15 V dc to 20 V dc. Final Battery Voltage: VBAT = 12.6 V. Charge Current: ICHARGE = 4.0 A (for VO = 0 V to 12.6 V) Supply Considerations Circuit Topology The guaranteed operating supply voltage range of the ADP3801/ ADP3802 is from 4 V to 20 V, and it typically consumes 5.0 mA of quiescent current when not switching. However, the part needs at least 2 V of headroom between VCC and the voltage on the CS+ and CS– pins. This is for the common-mode range The complete Buck charger circuit is shown in Figure 24. The dc-source voltage can be supplied from an ac/dc adaptor or an external dc/dc supply. (+15V TO +20V) VIN 210mF 25V RCS 40mV 33mH Si4463 0.1mF Charger Specifications MBRD835 1kV MBRD835 BATA 12.6VMAX 140mF 25V 4.3kV C7 2.2nF 4.3kV C9 2.2nF RESET 1MV GND DRV RESET VCC ADP3801/ ADP3802 VL 100kV SD SD A/B BATA BATB TOP VIEW (Not to Scale) PROG CS– ADJ CS+ EOC COMP ISET 100kV 56V VL = +3.3V 200kV 24kV 4.7mF 1.0mF 100kV 20kV EOC Figure 24. Li-Ion Battery Charger –12– REV. 0 ADP3801/ADP3802 Current Sense The maximum charging current is specified by the battery manufacturer as 4.0 A. To avoid losing excessive power on the current-sense resistor, it is advisable to keep the voltage drop across the resistor at maximum current to 160 mV or below. Thus, RCS = 0.16 V/4 A = 40 mΩ. The resistor’s maximum power rating can be calculated using the data sheet specification for the Overcurrent Comparator. The overcurrent protection is specified at 4.9 A when using a 40 mΩ resistor; therefore, the resistor has to be rated at PR = (4.9)2 × 0.04 = 0.96 W. Thus a 1.0 W or higher power rated resistor should be used. Two 2.2 nF capacitors are connected from the CS+ and CS– inputs to ground to filter out high frequency switching noise. ISET Programming Voltage This voltage programs the charge current based on the above calculated RCS. Using the data sheet specification for the current programming at the ISET input of 0.1 V/V, we need: VISET = RCS × I CHARGE = 0.04 Ω × 4.0 A = 1.6 V The maximum off-time of the Buck switch (TOFFMAX) occurs at the maximum input voltage of 20 V: TOFFMAX = 100 − DMAX = fOSC × 100 100 − 63 200 kHz × 100 = 1.9 µs This gives an inductor value of: L> VOMAX × TOFFMAX = I RPP 12.6 V × 1.9 µs = 24 µH 1.0 A The max inductor peak current is calculated as follows: ILPEAK = IDC + IRPP /2 = 4.0 + 1.0/2 = 4.5 APEAK The max inductor rms current is calculated (where 0.577 is the conversion factor for a peak to RMS value): I LRMS = 0.577 × 0.5 × VO × TOFF = 0.577 × 0.5 × 12.6 × 1.9 µs L 24 µH = 0.3 A The 1.6 V can be obtained from the 3.3 V LDO by a resistor divider of 20 kΩ and 22 kΩ. An appropriate inductor is the Coiltronix UP4B330, which is specified at 33 µH and can carry the 4.5 A current with about a 20°C temperature rise. For the ADP3802, the above formulas give: TOFFMAX = 0.74 µs and L = 10 µH. PROG Voltage PFET Selection and Thermal Design 0.1V/V 0.1V/V Next, the PROG voltage has to be determined to set the proper final battery voltage. From the data sheet, VPROG for two Li-Ion batteries in series (12.6 V) is between 2.05 V and 2.3 V. A 2.2 V input can be obtained from the 3.3 V LDO by a resistor divider of 66.5 kΩ and 33.2 kΩ. ADJ Voltage Since no further adjustment of the final battery voltage is required, this pin is tied to the VL pin, which disables the internal amplifier. Output Voltage and Duty Cycle A Buck type of converter’s output voltage VO can be calculated as follows: VO = VIN × D 100 = VIN × TON 100 × T In the above equation, D is the maximum duty cycle of the converter in percentage, and TON and T are the ON time and total period respectively. Setting VINMIN = 15 V provides margin for external voltage drops and the common-mode input range of the current sense amplifier. We have to consult the available P-channel MOSFET (PFET) transistor selection charts for switch-mode power supply applications to find a PFET in the desired package whose Safe Operation Area (SOA) would meet the maximum VIN and IO requirements with acceptable margin. For this application, the Temic Si4463 was selected in an SO-8 package. This transistor is specified at VDSS = –20 V, VGSMAX = 12 V, RDS(ON) = 0.013 Ω (for VGS = 4.5 V), and IDMAX = 10 A. Its SOA covers the 20 V, 4.0 ADC, and 4.5 APEAK application requirements with adequate margin. Since the switching losses are negligible for properly driven PFETs compared to conduction losses, the worst-case conduction losses can be estimated from the worst case ON resistance (RDS(ON)) of the selected PFET when subjected to short circuit current at the minimum input voltage and close to 100% duty cycle. RDS(ON) increases about 50% at TJ = 150°C. Thus the worst case value we can use is 0.023 Ω. The maximum PFET dissipation is calculated as follows: PDMAX = IPEAK2 × RDS(ON) = 4.5 A2 × 0.023 Ω = 0.47W Next the maximum junction temperature TJMAX of the transistor can be calculated: For VIN = 11 V: DMAX = VO × 100 / VIN = 12.6 × 100 / 15 = 84% TJMAX = TA + (RθJA) × PDMAX = 50 + (50) × 0.47 = 74°C For VIN = 20 V: DMAX = VO × 100 / VIN = 12.6 × 100 / 20 = 63% Buck Inductor The inductor value can be calculated after determining the allowable amount of inductor ripple current. For continuous buck operation, and considering low cost inductor core materials and acceptable core losses at 200 kHz, the usual peak-topeak inductor ripple current (IRPP) used is 20%-40% of the maximum dc current. Using 25% of 4.0 ADC gives IRPP = 1.0 APP. REV. 0 where TA = 50°C and R θJA = 50°C/W, as specified on the transistor’s data sheet for a 1 inch square PCB-pad. The calculated TJMAX should be below the maximum allowed junction temperature of the transistor with adequate margin. The Si4463 specifies a TJMAX of 150°C, which we meet with more than adequate margin. –13– ADP3801/ADP3802 Gate Drive to CIN, a 0.1 µF decoupling capacitor is required as close as possible to the VCC pin. The ADP3801 and ADP3802 are designed to directly drive the gate of a PFET with no additional circuitry as shown on the circuit diagram. The DRV pin pulls the gate up to within 250 mV of VCC, which is more than enough to ensure that the transistor turns off. To turn the PFET on, the DRV pin pulls down to a clamped voltage that is at most 7 V below VCC. Check the specified PFET’s maximum Gate-Source rating to see if this voltage does not exceed its breakdown. The Si4463 is rated at VGSMAX = 12 V, which is well above the maximum gate drive for the ADP3801/ADP3802. This is low enough for most applications. For cost reduction, one of the 68 µF capacitors could be removed, or a cheaper electrolytic could be used instead. Schottky Rectifier Selection and Thermal Design Output Capacitor Selection The diode power dissipation (PD) is calculated by multiplying the forward voltage drop (VF) times the Schottky diode duty cycle multiplied by the short circuit current. The worst-case forward voltage drop of MBRD835 diode is 0.41 V at IPK = 4.5 A, thus: DON / 100 84 / 100 VOUTRIPPLE = I LPP × ESR + = 130 mVPP = 1.0 A × 0.1 Ω + fOSC × COUT 200 kHz × 140 µF This ripple is low enough for most applications. Again, one of the capacitors could be removed or lower cost electrolytic capacitors could be used to reduce cost. PD = IPK × DD × VF = 4.5 × 0.95 × 0.41 = 1.8W From the diode’s worst-case dissipation, the maximum junction temperature TJMAX of the diode can be calculated: Charger Performance Summary The circuit properly executes the charging algorithm, exhibiting stable operation regardless of battery conditions, including an open circuit load in which the battery is removed. TJMAX = TA + RθJA × PD = 25 + (40) × 1.8 = 97°C RθJA is the junction to ambient thermal impedance of the diode. The calculated TJMAX should be below the maximum allowed junction temperature of the diode with adequate margin. TJMAX of the MBRD835 is 125°C, which is met with adequate margin. Input Capacitor Selection VIN ( × VOUT VIN − VOUT Li-Ion charging characteristics are given in Figure 25. The charge current is maintained at its programmed level until the battery reaches its final voltage. Then the current begins to decrease. The shape of the current decrease is dependent on the internal impedance of the battery. When the current drops below 240 mA, the EOC comparator signals the end-of-charge of the battery. 4.5 VBAT – Volts In continuous mode, the source current of the PMOS is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by: I RMS ≈ D / 100 84 / 100 VI NRIPPLE = IO × ESR + ON = 360 mVPP = 4.0 A × 0.07 Ω + fOSC × CIN 200 kHz × 210 µF As a first choice, we’ll use two of the same type of 68 µF Sprague capacitors for the output. The inductor rms ripple current was calculated as 0.3 A, which is far below the specification for these capacitors. The other consideration is the allowable output ripple voltage. Assuming high battery internal resistance, all of the worst case inductor ripple current may flow through the output capacitor. This results in a ripple voltage of: The Schottky diode’s peak current and average power dissipation must not exceed the diode ratings. The most stressful condition for the output diode is under short circuit (VO = 0 V), where the diode duty cycle DD is at least 95%. Under this condition, the diode must safely handle IPK at close to 100% duty cycle. IOUT Once the capacitor is chosen, the input ripple voltage should be checked: ) This formula has a maximum at VIN = 2 VOUT, where IRMS = IOUT /2 = 2.0 A. 4.0 VBAT 3.5 3.0 This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. As a first choice, three 68 µF/20 V Sprague type 593D tantalum capacitors are used in parallel. Each is specified as follows: ESR = 0.2 Ω, maximum ripple current of 0.91ARMS. In addition –14– ICHARGE – Amps 2.5 ICHARGE 4.0 2.7 1.3 0 EOC 0 0.5 1.0 1.5 TIME – Hours 2.0 2.5 3.0 Figure 25. Li-Ion Charging Characteristic REV. 0 ADP3801/ADP3802 The efficiency of this circuit is shown in Figure 26 for a charge current of 4 Amps. As expected, the efficiency increases with the output voltage, up to a maximum of 92% at 12.6 V. VCC – Volts VCC 100 15V 5V VCC = 15V ICHARGE = 4 AMP EFFICIENCY – % 80 ICHARGE (AVERAGE) ICHARGE – Amps FREQ = 200kHz 90 FREQ = 500kHz VCC = 15V TA = +258C ICHARGE = 4 Amps 20ms/DIV 10V 0A 4A Figure 28. Source Current Due to Input Turn-On 70 Feedback Loop Compensation Design 60 6 7 8 9 10 11 OUTPUT – Volts 12 13 14 Figure 26. Efficiency for ICHARGE = 4.0 Amp Figure 27 shows the output voltage transient when a battery load is snapped off. The output is charging a battery (which is currently discharged to 5 V) at 4.0 A when the battery is removed. The high charge current causes the output voltage to quickly increase and exceed the final battery voltage. However, the overvoltage comparator quickly controls the output and only a small overshoot results. When the battery is returned to the circuit, VBAT is pulled back down to the battery’s voltage. OUTPUT VOLTAGE – Volts 14V 12V 10V 8V The ADP3801 and ADP3802 have two separate feedback loops, the current control loop and the voltage control loop. Each loop must be compensated properly so that the circuit is stable during the entire charging cycle of a battery including the case where no battery is present. A series RC from the COMP pin to ground provides pole/zero compensation for both loops. The circuit in Figure 24 is properly compensated for the ADP3801 and ADP3802 and can be used as is. Figure 29 shows a typical ac model of the ADP3801/ADP3802. The current loop and voltage loop are comprised of voltage controlled current sources (GM stages). The gains given in the schematic and the impedance at the COMP node are typical values for both the ADP3801 and ADP3802. This model can be used to simulate the small signal ac behavior of the part using a SPICE-based simulator when paired with an ac model of a buck regulator. However, transient and dc behavior is not modeled with this model. The GM stages are actually modeled using the “Table” component in PSpice, which limits the dc levels to ease dc convergence. The coefficients on the schematic give the table coefficients. The input resistors (R1 and R2) are currently set for a 4.2 V final battery voltage. Use the accompanying table to adjust R1 and R2 for the other voltage options. Doing so is important to properly set the voltage loop gain. 6V VBAT = 12.6V ICHARGE = 4 AMP VCC = 15V 50ms/DIV CH1 2.00V M50.0ms CH 1 TIME – ms 10.0V Figure 27. Output Voltage Transient Due to Battery Snap Off CS+ VBAT GM1 R1 R2 4.2V 173kV 112kV 8.4V 229kV 56kV 12.6V 247.7kV 37.3kV CS– gm = 1E – 4 (0,0) (0.2, 20E – 6) GM2 ISET The behavior of the circuit when it is powered on with a dead battery inserted is important to check to make sure that the charger does not exhibit irregular behavior during power-up. In this case, the ADP3801 needs to regulate the output current to 4.0 A. Figure 28 shows the average Si4463 source current under such a condition. When the input power is applied to the charger, the source current ramps up in a controlled manner due to the ADP3801’s soft start. R3 100kV I1 100mA gm = 8E – 3 (–12.5m, –200E – 6) (12.5m,0) GM3 VBAT R1 173kV E4 V1 1.65V OUT R4 4MV R2 112kV GAIN = 1V/V gm = 1.6E – 3 (–62.5m, –200E – 6) (62.5m,0) Figure 29. AC Behavioral SPICE Model for the ADP3801 and ADP3802 REV. 0 –15– ADP3801/ADP3802 NiCad/NiMH Charging Dual Li-Ion Battery Charger When paired with a low cost, 8-bit microcontroller, the ADP3801/ADP3802 charges NiCad and NiMH batteries. The ADP3801/ADP3802 is used to provide a programmable charge current limit with a fail-safe voltage limit, and the microcontroller monitors the battery and determines the charge termination. Common methods for termination are “negative delta V” and “delta T.” Both methods require that the present value of either the voltage or temperature be compared to a previous value. Such functionality is performed by an µC with an on-board ADC. Some applications such as certain desktop chargers for cellular phones or laptops with two batteries require that two separate battery stacks be charged independently. The ADP3801/ADP3802 is designed to handle these applications with two battery sense inputs and a multiplexer to select between the two. The application circuit is essentially the same as Figure 24 except that external FETs must be added to direct the charge current to the proper battery stack. Figure 31 shows the additional circuitry needed. The µC and the ADP3801/ADP3802 are configured as shown in Figure 30 for the universal charger. The voltage setting on the ADP3801/ADP3802 should not interfere with normal charging, but still provide a fail safe voltage if the battery is removed. For example, if a 6-cell NiCad battery is being charged, the output voltage of the ADP3801/ADP3802 should be programmed to 12.6 V. The 6-cell battery has a peak voltage of approximately 1.7 V–1.8 V per cell, giving a total voltage of 9.6 V–10.8 V. Thus, the 12.6 V setting provides enough headroom for normal charging. Si4463 100kV RCS 40mV 4.3kV VIN VDD R1 AN0 AN1 R4 PA0 MICROCONTROLLER ISET R2 PA1 PA3 PA2 VCC BATA R3 C1 R5 C2 ADP3801/ ADP3802 CHARGER CIRCUIT SD C3 T EOC 4.3kV MBRD835 RB BATB 100kV CS+ CS– * * A/B SELECTOR A/B BATA BATB ADP3801/ ADP3802 * OPEN-COLLECTOR OUTPUTS Figure 31. Dual Li-Ion Battery Charger To provide alternate or sequential charging, the two separate batteries are alternately connected to the output of the charger by two Si4463 PFETs. The control of these FETs is accomplished by open-collector logic outputs and 100 kΩ pull-up resistors. The programming of the A/B terminal should come from a 0 V to 3.3 V logic output. Most likely a dedicated logic circuit or a microcontroller would control the system. The BATB sense input is enabled by connecting a >2 V potential to the A/B input (or <0.8 V to select BATA). The A and B battery voltages are directly sensed by the BATA and BATB inputs. Two Schottky diodes are also included to prevent one battery stack from shorting to the other through the body diodes of the FETs. When the charger has finished charging one battery (signaled by the EOC output), the MUX and external FETs can be switched to charge the second battery. When switching from one battery to the next the following procedure is recommended to minimize transient currents: VL PROG BATA Si4463 CO Universal Battery Charger The combination of a µC and the ADP3801/ADP3802 can be extended to a low cost universal charger for Li-Ion and NiCad/ NiMH as shown in Figure 30. The µC with on-board A/D converter monitors the battery’s voltage and temperature to determine the end-of-charge for either NiCad or NiMH batteries. The ADP3801/ADP3802 also monitors the battery voltage to determine the end-of-charge for Li-Ion. The EOC output is connected to a digital input on the µC for signaling. The µC can shutdown the charger circuitry when it is not required. The µC shown operates from 3.3 V, so it can be powered directly from the LDO of the ADP3801/ADP3802. The LDO voltage also serves as a 1% reference for the µC’s ADC. MBRD835 GND T = BATTERY THERMISTOR 1. Turn off the ADP3801/ADP3802 PWM by bringing the SD pin low. Figure 30. Universal Battery Charger Block Diagram Both the charge current and the final battery voltage can be dynamically set by using a PWM output from the µC. The PWM inputs to ISET and PROG are filtered by an RC combination to generate a dc voltage on the pins. This functionality allows multiple battery types and chemistries to be accommodated in a single charger circuit. 2. Turn off the FET to the battery being charged. 3. Wait approximately 60 seconds for CO to discharge through RB. 4. Turn on the FET to the second battery. 5. Change the A/B SELECT MUX to the second battery. 6. Turn on the ADP3801/ADP3802 by bringing the SD pin high. –16– REV. 0 ADP3801/ADP3802 The 60 second wait period allows the output capacitor to discharge before switching from one battery to the next. Without this wait period, the capacitor would be fully charged when switched to an uncharged battery. The current under this condition is only limited by the ESR of the capacitor, the ON resistance of the FET and diode, and the series resistance of the battery. These values are typically very small, so current in excess of 5 amps can flow for a short time period. In most practical circuits the wait period is not required, but it is good practice to have it in µC controlled systems. The duration of the wait period is determined by the RC time constant of CO and RB and can be adjusted by changing these components. The two Si4463 switches are turned on by connecting their gates to ground. In a short circuit or overdischarged battery condition, the switches could be operated in their linear region. This may result in high power dissipation and excessive die temperature rise. In µC controlled chargers a simple monitor routine can reduce the charge current if the battery voltage is lower than about 2 V. This should not happen under normal circumstances as the Li-Ion cells are not discharged below 2.5 V/cell. Because the current sense voltage is divided down by these input resistors, the current sense programming function also changes. Remember to adjust the programming function by the same ratio. In this example, the programming function would become 0.125 V/V. Also, the EOC current detection point changes by the same factor. An alternative to adding the resistor divider is to use a low side current sense. The CS+ and CS– inputs have a common-mode range that extends approximately 300 mV below ground. The circuit in Figure 33 shows how a low side current sense would be configured. The current programming function, EOC detection point, and ac performance do not change from the normal configuration. Si4463 VIN 210mF RCS 40mV 4.3kV 4.3kV 2.2nF 0.1mF GND 2.2nF Low Overhead Charging VCC DRV EOC CS– For applications where the input supply is less than 2 V higher than the final battery voltage, the circuit of Figure 32 can be used. This circuit adds a resistor divider to the input of the current sense amplifier to increase its common-mode input voltage range. The value of this resistor divider should divide down the battery voltage such that the common-mode voltage at CS+ and CS– is at least 2 V less than the chip’s VCC. The formula for the ratio is: R2 R1 + R2 ≤ VL 0.1mF For example, if VCCMIN = 9 V and VBATMAX = 8.4 V, then the ratio would be 0.833. To provide some headroom for resistor tolerances and line drops, the actual ratio should be lowered to 0.8. The resistors should be reasonably large to keep the current drain low. Values of R1 = 20 kΩ (0.1%) and R2 = 80 kΩ (0.1%) work well. A diode is added between the current sense resistor and the battery to prevent discharging the battery through these resistors. GND 430pF CS+ R2 80kV CS– ADP3801/ ADP3802 Figure 32. Low Overhead Charging REV. 0 BATB A/B COMP ADJ PROG VL VBATPROG Figure 33. Low Side Current Sensing For Low Overhead Charging R1 20kV 430pF R2 80kV VISET BATA SD RCS 0.1V R1 20kV ISET ADP3801/ADP3802 RESET VCC MIN − 2 V VBATMAX CS+ –17– ADP3801/ADP3802 VCC Greater Than 20 V Operation Some ac/dc adapters have a poorly regulated output voltage that can rise above the 20 V maximum operating voltage of the ADP3801/ADP3802. The circuit in Figure 34 uses a Zener diode and an NPN transistor to extend the ADP3801/ADP3802’s maximum input voltage. The Zener should be at least 3 V higher than the final battery voltage to meet the minimum headroom requirements. 3 V is used to account for the VBE drop of the 2N3904 transistor and additional losses in the circuit. If VIN drops below the value of the Zener diode, VCC is no longer regulated and it tracks VIN. If the 2 V of headroom on the current sense pins is not maintained, then the circuits of Figures 32 and 33 can also be used in conjunction with the circuit of Figure 34. 33mH 40mV VIN 10kV 100kV 2N3904 140mF 9V system current and dynamically control the ADP3801/ADP3802’s charge current. The current setting voltage is produced by R3 and R4 according to the following formula: I SET ≈ VCC BAT I ZERO ≈ 0.1mF DRV EOC CS+ 3.3V CS– A/B BATB ADP3801/ADP3802 RESET ISET AC/DC BRICK PROG GND COMP 10 RCS × × ISET R2 RSS R1 Because the AD8531 is a single supply amplifier with its negative rail at ground, its output does not go below 0.0 V, so any further increase in system current does not change VISET. Designing a charger with a maximum charge current of 3A (RCS = 0.05 Ω) which reduces to zero when the system current reaches 7A (RSS = 0.025 Ω) results in the following resistor values: R1 = 100 kΩ, R2 = 820 kΩ, R3 = 8.3 kΩ, R4 = 10 kΩ. BATA VL SD 10 RCS R3 × VL R3 + R4 This equation is approximate because the impedance of R2 and R1 does effect the resistor divider of R3 and R4, but the impact is small. As the system current increases, the voltage across RSS also increases. This voltage is subtracted from VISET with a gain set by R1 and R2. As the graph in Figure 35 shows, the charge current reduces as the system current increases, and eventually the charge current becomes zero (IZERO). The system current at which this occurs can be set by selecting R1 and R2 according to the following formula: 9V 0.1mF 1 I SYSTEM VCC SYSTEM R1 100kV ADJ R4 10kV RSS R1 100kV OP193 R2 820kV R3 8.3kV Figure 34. VCC Greater Than 20 V Operation The gate drive of the PFET is capacitively coupled to the DRV pin with a 0.1 µF capacitor. While the DRV pin is switching, the voltage swing on the DRV pin is coupled to the gate, but the dc voltage is blocked. This allows the gate of the PFET to be at a voltage that is higher than the absolute maximum rating of the DRV pin. The 9 V Zener diode limits the gate drive voltage and the 100 kΩ resistor provides a dc pull-up to turn the PFET off when the DRV pin is not switching. R2 820kV IBAT RCS DRV VCC CS+ BAT CS– VBAT ADP3801/ADP3802 VL 100kV ISET 0.1mF System Current Sense Reduces Charge Current In many applications the power required for the system and the battery charger exceeds the total power available from the ac/dc adapter. A design where battery charger current is decreased as the system current increases helps to keep a constant power demand on the brick. Dynamically adjusting the charge current keeps the total power output of the brick constant. The circuit in Figure 35 uses an external low cost amplifier to sense the IBAT (ISET) = MAXIMUM CHARGE CURRENT 0 0 IZERO I SYSTEM Figure 35. System Current Sense Reduces Charge Current –18– REV. 0 ADP3801/ADP3802 Board Layout Suggestions When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ADP3801 and ADP3802. These items are also illustrated graphically in the layout diagram on the evaluation board application note. Check the following in your layout: 4) Connect the positive side of CIN as close as possible to the source of the P-channel MOSFET (or the emitter of the PNP). This capacitor provides the ac current to the pass transistor. 1) The IC ground must return to a) the power and b) the signal grounds with as short of leads as possible. If a double layer PCB board is used and a ground plane is available, connect all grounded parts directly to the ground plane. The ground returns to the anode of the Schottky diode and the minus terminal of CIN should have as short of lead lengths as possible. 2) Connect the IC’s current sense pins (CS+ and CS–) to RCS with as short of leads (<0.5 inch) as possible. 5) Connect the input decoupling capacitor (0.l µF) close to the VCC input of the IC. This capacitor carries the DRV peak currents. 6) Connect the 0.1 µF LDO decoupling capacitor as close as possible to the VL pin. 7) The RESET pin has an internal pull-up, and should be pulled low with an external resistor. The RESET pin is high impedance and should not be allowed to float. 3) Route the CS+ and CS– traces together with minimum spacing. The filter capacitors should be close to the IC. REV. 0 –19– ADP3801/ADP3802 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Narrow Body (SOIC) (R-16A) 16 0.1574 (4.00) 0.1497 (3.80) 1 9 8 0.0500 SEATING (1.27) PLANE BSC 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 0.0196 (0.50) x 45° 0.0099 (0.25) 8° 0° 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. PIN 1 0.0098 (0.25) 0.0040 (0.10) C3351–8–10/98 0.3937 (10.00) 0.3859 (9.80) –20– REV. 0