LMC6081 Precision CMOS Single Operational Amplifier General Description Features The LMC6081 is a precision low offset voltage operational amplifier, capable of single supply operation. Performance characteristics include ultra low input bias current, high voltage gain, rail-to-rail output swing, and an input common mode voltage range that includes ground. These features, plus its low offset voltage, make the LMC6081 ideally suited for precision circuit applications. Other applications using the LMC6081 include precision full-wave rectifiers, integrators, references, and sample-and-hold circuits. This device is built with National’s advanced Double-Poly Silicon-Gate CMOS process. For designs with more critical power demands, see the LMC6061 precision micropower operational amplifier. For a dual or quad operational amplifier with similar features, see the LMC6082 or LMC6084 respectively. PATENT PENDING (Typical unless otherwise stated) n Low offset voltage: 150 µV n Operates from 4.5V to 15V single supply n Ultra low input bias current: 10 fA n Output swing to within 20 mV of supply rail, 100k load n Input common-mode range includes V− n High voltage gain: 130 dB n Improved latchup immunity Applications n n n n n n Instrumentation amplifier Photodiode and infrared detector preamplifier Transducer amplifiers Medical instrumentation D/A converter Charge amplifier for piezoelectric transducers Connection Diagram 8-Pin DIP/SO Low-Leakage Sample and Hold DS011423-1 Top View DS011423-12 © 2000 National Semiconductor Corporation DS011423 www.national.com LMC6081 Precision CMOS Single Operational Amplifier August 2000 LMC6081 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ± Supply Voltage Differential Input Voltage Voltage at Input/Output Pin 40 mA (Note 3) Operating Ratings (Note 1) (V+) +0.3V, (V−) −0.3V 16V (Note 10) (Note 2) Supply Voltage (V+ − V−) Output Short Circuit to V+ Output Short Circuit to V− Lead Temperature (Soldering, 10 Sec.) Storage Temp. Range Junction Temperature ESD Tolerance (Note 4) ± 10 mA ± 30 mA Current at Input Pin Current at Output Pin Current at Power Supply Pin Power Dissipation Temperature Range LMC6081AM LMC6081AI, LMC6081I Supply Voltage Thermal Resistance (θJA), (Note 11) N Package, 8-Pin Molded DIP M Package, 8-Pin Surface Mount Power Dissipation (Note 9) 260˚C −65˚C to +150˚C 150˚C 2 kV −55˚C ≤ TJ ≤ +125˚C −40˚C ≤ TJ ≤ +85˚C 4.5V ≤ V+ ≤ 15.5V 115˚C/W 193˚C/W DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol VOS TCVOS Parameter Conditions Input Offset Voltage Typ LMC6081AM LMC6081AI (Note 5) Limit Limit Limit (Note 6) (Note 6) (Note 6) 150 Input Offset Voltage LMC6081I Units 350 350 800 µV 1000 800 1300 Max 1.0 µV/˚C Average Drift IB Input Bias Current 0.010 pA 100 IOS Input Offset Current RIN Input Resistance CMRR Common Mode 4 0.005 V = 15V Positive Power Supply 5V ≤ V+ ≤ 15V Rejection Ratio VO = 2.5V −PSRR Negative Power Supply 0V ≤ V− ≤ −10V VCM Input Common-Mode 85 V+ = 5V and 15V Voltage Range for CMRR ≥ 60 dB 75 66 dB 72 72 63 Min 75 75 66 dB 72 72 63 Min 94 84 84 74 dB 81 81 71 Min −0.4 −0.1 −0.1 −0.1 V 0 0 0 Max V+ − 2.3 V+ − 2.3 V+ − 2.3 V V+ − 2.5 Min 85 V+ − 1.9 + V − 2.6 Large Signal RL = 2 kΩ Voltage Gain (Note 7) Sourcing 1400 Sinking RL = 600Ω 350 Sourcing 1200 Sinking 150 (Note 7) 2 Max 75 Rejection Ratio www.national.com 2 Tera Ω + Rejection Ratio AV 2 > 10 0V ≤ VCM ≤ 12.0V Max pA 100 +PSRR 4 + V − 2.5 400 400 300 V/mV 300 300 200 Min 180 180 90 V/mV 70 100 60 Min 400 400 200 V/mV 150 150 80 Min 100 100 70 V/mV 35 50 35 Min (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol VO Parameter Output Swing Conditions V+ = 5V Typ LMC6081AM LMC6081AI (Note 5) Limit Limit Limit (Note 6) (Note 6) (Note 6) 4.87 4.80 4.80 4.75 V 4.73 4.67 Min 0.13 0.13 0.20 V 0.19 0.17 0.24 Max 4.50 4.50 4.40 V 4.24 4.31 4.21 Min 0.30 0.40 0.40 0.50 V 0.63 0.50 0.63 Max 14.63 14.50 14.50 14.37 V 14.30 14.34 14.25 Min 0.10 4.61 RL = 600Ω to 2.5V V+ = 15V RL = 2 kΩ to 7.5V 0.26 V+ = 15V 13.90 RL = 600Ω to 7.5V 0.79 IO Output Current V Max 13.35 13.35 12.92 V 12.80 12.86 12.44 Min 1.16 1.16 1.33 V 1.42 1.32 1.58 Max 13 mA Min 16 8 10 8 Sinking, VO = 5V 21 16 16 13 mA 11 13 10 Min 28 28 23 mA 18 22 18 Min 28 28 23 mA 19 22 18 Min 750 750 750 µA 900 900 900 Max 850 850 850 µA 950 950 950 Max Sourcing, VO = 0V 30 Sinking, VO = 13V 34 V = 15V (Note 10) Supply Current 0.44 0.56 16 + IS 0.35 0.45 22 V = 5V Output Current 0.35 0.48 Sourcing, VO = 0V + IO Units 4.70 RL = 2 kΩ to 2.5V V+ = 5V LMC6081I V+ = +5V, VO = 1.5V 450 V+ = +15V, VO = 7.5V 550 3 www.national.com LMC6081 DC Electrical Characteristics LMC6081 AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol Parameter Conditions (Note 8) Typ LMC6081AM LMC6081AI (Note 5) Limit Limit Limit (Note 6) (Note 6) (Note 6) 0.8 0.8 0.8 0.5 0.6 0.6 1.5 LMC6081 Units SR Slew Rate V/µs GBW Gain-Bandwidth Product 1.3 MHz φm Phase Margin 50 Deg en Input-Referred Voltage Noise F = 1 kHz 22 in Input-Referred Current Noise F = 1 kHz 0.0002 T.H.D. Total Harmonic Distortion Min F = 10 kHz, AV = −10 RL = 2 kΩ, VO = 8 VPP 0.01 % ± 5V Supply Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of ± 30 mA over long term may adversely affect reliability. Note 3: The maximum power dissipation is a function of TJ(Max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(Max) − TA) /θJA. Note 4: Human body model, 1.5 kΩ in series with 100 pF. Note 5: Typical values represent the most likely parametric norm. Note 6: All limits are guaranteed by testing or statistical analysis. Note 7: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V. Note 8: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Note 9: For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA. Note 10: Do not connect output to V+, when V+ is greater than 13V or reliability will be adversely affected. Note 11: All numbers apply for packages soldered directly into a PC board. Typical Performance Characteristics Distribution of LMC6081 Input Offset Voltage (TA = +25˚C) VS = ± 7.5V, TA = 25˚C, Unless otherwise specified Distribution of LMC6081 Input Offset Voltage (TA = −55˚C) DS011423-15 www.national.com Distribution of LMC6081 Input Offset Voltage (TA = +125˚C) DS011423-16 4 DS011423-17 LMC6081 Typical Performance Characteristics VS = ± 7.5V, TA = 25˚C, Unless otherwise specified (Continued) Input Bias Current vs Temperature Supply Current vs Supply Voltage DS011423-19 DS011423-18 Common Mode Rejection Ratio vs Frequency Input Voltage vs Output Voltage Power Supply Rejection Ratio vs Frequency DS011423-20 Input Voltage Noise vs Frequency DS011423-22 DS011423-23 DS011423-21 Output Characteristics Sourcing Current Output Characteristics Sinking Current Gain and Phase Response vs Temperature (−55˚C to +125˚C) DS011423-24 DS011423-25 5 DS011423-26 www.national.com LMC6081 Typical Performance Characteristics VS = ± 7.5V, TA = 25˚C, Unless otherwise specified (Continued) Gain and Phase Response vs Capacitive Load with RL = 600Ω Gain and Phase Response vs Capacitive Load with RL = 500 kΩ DS011423-29 DS011423-27 Inverting Small Signal Pulse Response DS011423-28 Inverting Large Signal Pulse Response DS011423-30 Non-Inverting Large Signal Pulse Response Open Loop Frequency Response Non-Inverting Small Signal Pulse Response DS011423-31 Stability vs Capacitive Load, RL = 600Ω DS011423-33 DS011423-32 Stability vs Capacitive Load RL = 1 MΩ DS011423-34 DS011423-35 Applications Hints micropower op-amps. These features make the LMC6081 both easier to design with, and provide higher speed than products typically found in this ultra-low power class. AMPLIFIER TOPOLOGY The LMC6081 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional www.national.com COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the LMC6081. 6 LMC6081 Applications Hints (Continued) Although the LMC6081 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phase margins. When high input impedances are demanded, guarding of the LMC6081 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High Impedance Work). The effect of input capacitance can be compensated for by adding a capacitor, Cf, around the feedback resistors (as in Figure 1 ) such that: DS011423-5 FIGURE 2. LMC6081 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads or R1 CIN ≤ R2 Cf Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and LMC662 for a more detailed discussion on compensating for input capacitance. In the circuit of Figure 2, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier’s inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 3). Typically a pull up resistor conducting 500 µA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see electrical characteristics). DS011423-4 FIGURE 1. Cancelling the Effect of Input Capacitance CAPACITIVE LOAD TOLERANCE All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is normally included in this integrator stage. The frequency location of the dominant pole is affected by the resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate resistive load in parallel with the capacitive load (see typical curves). Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp’s output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 2. DS011423-14 FIGURE 3. Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6081, typically less than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6081’s inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp’s inputs, as in Fig7 www.national.com LMC6081 Applications Hints (Continued) ure 4. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6081’s actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 5 for typical connections of guard rings for standard op-amp configurations. DS011423-7 Inverting Amplifier DS011423-8 Non-Inverting Amplifier DS011423-6 FIGURE 4. Example of Guard Ring in P.C. Board Layout DS011423-9 Follower FIGURE 5. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don’t insert the amplifier’s input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 6. DS011423-10 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board). FIGURE 6. Air Wiring Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum curwww.national.com 8 require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. (Continued) rent required to trigger the SCR gate lead. The LMC6061 and LMC6081 are designed to withstand 100 mA surge current on the I/O pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins will also inhibit latchup susceptibility. Figure 7 shows an instrumentation amplifier that features high differential and common mode input resistance ( > 1014Ω), 0.01% gain accuracy at AV = 1000, excellent CMRR with 1 kΩ imbalance in bridge source resistance. Input current is less than 100 fA and offset drift is less than 2.5 µV/˚C. R2 provides a simple means of adjusting gain over a wide range without degrading CMRR. R7 is an initial trim used to maximize CMRR without using super precision matched resistors. For good CMRR over temperature, low drift resistors should be used. Typical Single-Supply Applications (V+ = 5.0 VDC) The extremely high input impedance, and low power consumption, of the LMC6081 make it ideal for applications that DS011423-11 If R1 = R5, R3 = R6, and R4 = R7; then AV ≈ 100 for circuit shown (R2 = 9.822k). FIGURE 7. Instrumentation Amplifier DS011423-12 FIGURE 8. Low-Leakage Sample and Hold 9 www.national.com LMC6081 Latchup LMC6081 Typical Single-Supply Applications (Continued) DS011423-13 FIGURE 9. 1 Hz Square Wave Oscillator Ordering Information Package 8-Pin www.national.com Temperature Range Military Industrial −55˚C to +125˚C −40˚C to +85˚C LMC6081AIN Molded DIP LMC6081IN 8-Pin LMC6081AIM, LMC6081AIMX Small Outline LMC6081IM, LMC6081IMX 10 NSC Drawing Transport Media N08E Rail M08A Rail Tape and Reel LMC6081 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin Small Outline Package Order Number LMC6081AIM, LMC6081AIMX, LMC6081IM or LMC6081IMX NS Package Number M08A 8-Pin Molded Dual-In-Line Package Order Number LMC6081AIN or LMC6081IN NS Package Number N08E 11 www.national.com LMC6081 Precision CMOS Single Operational Amplifier Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.