LXT901A/907A Universal 3.3V Ethernet Transceiver Datasheet The LXT901A and LXT907A are new generation Universal Ethernet Transceivers with improved noise immunity and output filtering. The feature set of the LXT901A/907A has been streamlined, removing Remote Signaling capabilities. The LXT901A and LXT907A provide all the active circuitry to interface most standard 802.3 controllers to either the 10BASE-T media or Attachment Unit Interface (AUI). The LXT901A and LXT907A are identical except for the function of one pin. The LXT901A, with selectable termination impedance allows the use of either shielded or unshielded twistedpair cable. The LXT907A offers a Signal Quality Error disable (DSQE) function. LXT901A and LXT907A functions include Manchester encoding/decoding, receiver squelch and transmit pulse shaping, jabber, link testing and reversed polarity detection/correction. Applications ■ 10BASE-T hub and switching products ■ Computer/workstation 10BASE-T LAN adapter boards Product Features Functional Features ■ ■ ■ ■ ■ Integrated Filters - Simplify FCC Compliance Integrated Manchester Encoder/Decoder 10BASE-T Transceiver AUI Transceiver Full-Duplex Capable (20 Mbps) Diagnostic Features ■ ■ Four LED Drivers AUI/RJ-45 Loopback Convenience Features ■ ■ ■ ■ ■ ■ ■ ■ Automatic/Manual AUI/RJ-45 Selection Automatic Polarity Correction SQE Disable function (LXT907A) Programmable Impedance Driver (LXT901A) Single 3.3V operation Power Down Mode and four loopback modes Available in 64-pin LQFP and 44-pin PLCC packages Commercial (0 to +70oC) As of January 15, 2001, this document replaces the Level One document LXT901A/907A — Universal 3.3V Ethernet Transceiver. Order Number: 249098-001 January 2001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT901A/907A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Contents 1.0 Pin Assignments and Signal Descriptions ...................................................... 8 2.0 Functional Description...........................................................................................12 2.1 2.2 2.3 2.4 2.5 2.6 3.0 Application Information .........................................................................................20 3.1 3.2 3.3 3.4 4.0 4.2 4.3 4.4 Datasheet Twisted-Pair Impedance Matching ......................................................................20 Crystal Information ..............................................................................................20 Magnetics Information .........................................................................................20 Typical Applications.............................................................................................21 3.4.1 Auto Port Select with External Loopback Control...................................21 3.4.2 Full-Duplex Support................................................................................23 3.4.3 Dual Network Support - 10Base-T and Token Ring ...............................24 3.4.4 Manual Port Select with Link Test Function ...........................................25 3.4.5 Three Media Application.........................................................................27 3.4.6 AUI Encoder/Decoder Only ....................................................................28 3.4.7 150 W Shielded Twisted-pair only (LXT901A only)................................29 Test Specifications ..................................................................................................30 4.1 5.0 Controller Compatibility Modes ...........................................................................12 Transmit Function................................................................................................13 2.2.1 Jabber Control Function .........................................................................14 2.2.2 SQE Function .........................................................................................14 2.2.2.1 SQE Disable Function (LXT907A only) .....................................15 Receive Function.................................................................................................15 2.3.1 Polarity Reverse Function ......................................................................16 2.3.2 Collision Detection Function...................................................................16 Loopback Functions ............................................................................................17 2.4.1 Standard TP Loopback...........................................................................17 2.4.2 Forced TP Loopback ..............................................................................17 2.4.3 AUI Loopback.........................................................................................17 2.4.4 External Loopback..................................................................................17 Link Integrity Test Function .................................................................................17 Link Pulse Transmission .....................................................................................19 Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low) Figure 17 through Figure 2234 Timing Diagrams for Mode 2 (MD1=Low, MD0=High) Figure 23 through Figure 2836 Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low) Figure 29 through Figure 3638 Timing Diagrams for Mode 4 (MD1 = High, MD0 = High) Figure 37 through Figure 4241 Mechanical Specifications....................................................................................43 3 LXT901A/907A — Universal 3.3V Ethernet Transceiver Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 4 LXT901A/907A Block Diagram ............................................................................. 7 LXT901A/907A Pin Assignments ......................................................................... 8 TPO Output Waveform ....................................................................................... 13 Jabber Control Function ..................................................................................... 14 SQE Function ..................................................................................................... 15 Collision Detection Function ............................................................................... 16 Link Integrity Test Function ................................................................................ 18 Transmitted Link Integrity Pulse Timing ............................................................. 19 LAN Adapter Board - Auto Port Select with External LPBK Control .................. 22 Full-Duplex Operation ........................................................................................ 23 380C26 Interface for Dual Network Support of 10BASE-T and Token Ring ...... 24 LAN Adapter Board - Manual Port Select with Link Test Function...................... 25 Manual Port Select with Seeq 8005 Controller .................................................. 26 Three Media Application .................................................................................... 27 AUI Encoder/Decoder Only Application ............................................................. 28 150 W Shielded Twisted-Pair Only Application (LXT901A) ............................... 29 Mode 1 RCLK/Start-of-Frame Timing ................................................................ 34 Mode 1 RCLK/End-of-Frame Timing .................................................................. 34 Mode 1 Transmit Timing .................................................................................... 35 Mode 1 Collision Detect Timing ......................................................................... 35 Mode 1 COL/CI Output Timing ........................................................................... 35 Mode 1 Loopback Timing ................................................................................... 35 Mode 2 RCLK/Start-of-Frame Timing ................................................................ 36 Mode 2 RCLK/End-of-Frame Timing .................................................................. 36 Mode 2 Transmit Timing .................................................................................... 37 Mode 2 Collision Detect Timing ......................................................................... 37 Mode 2 COL/CI Output Timing ........................................................................... 37 Mode 2 Loopback Timing ................................................................................... 37 Mode 3 RCLK/Start-of-Frame Timing (LXT901A) .............................................. 38 Mode 3 RCLK/End-of-Frame Timing (LXT901A) .............................................. 38 Mode 3 RCLK/Start-of-Frame Timing (LXT907A) .............................................. 39 Mode 3 RCLK/End-of-Frame Timing (LXT907A) ............................................... 39 Mode 3 Transmit Timing .................................................................................... 40 Mode 3 Collision Detect Timing .......................................................................... 40 Mode 3 COL/CI Output Timing ........................................................................... 40 Mode 3 Loopback Timing ................................................................................... 40 Mode 4 RCLK/Start-of-Frame Timing ................................................................. 41 Mode 4 RCLK/End-of-Frame Timing .................................................................. 41 Mode 4 Transmit Timing .................................................................................... 42 Mode 4 Collision Detect Timing ......................................................................... 42 Mode 4 COL/CI Output Timing ........................................................................... 42 Mode 4 Loopback Timing ................................................................................... 42 44-Pin PLCC ....................................................................................................... 43 64-Pin LQFP ...................................................................................................... 44 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 Datasheet LXT901A/907A Signal Descriptions ...................................................................... 9 Controller Compatibility Modes ...........................................................................13 Suitable Crystals .................................................................................................20 Absolute Maximum Values..................................................................................30 Recommended Operating Conditions .................................................................30 I/O Electrical Characteristics ...............................................................................30 AUI Electrical Characteristics ..............................................................................31 TP Electrical Characteristics ...............................................................................31 Switching Characteristics ....................................................................................32 RCLK/Start-of-Frame Timing...............................................................................32 RCLK/End-of-Frame Timing................................................................................32 Transmit Timing...................................................................................................33 Collision, COL/CI Output and Loopback Timing.................................................33 5 LXT901A/907A — Universal 3.3V Ethernet Transceiver Revision History Revision 6 Date Description Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Figure 1. LXT901A/907A Block Diagram MD0 AUTOSEL MODE SELECT LOGIC Controller Compatibility Port Select Loopback Link test PAUI LBK LI MD1 TCLK CLKI WATCHDOG TIMER XTAL OSC CLKO TEN TWISTED PAIR INTERFACE Select: PLS Only or PLS / MAU TXD CMOS TX AMP PULSE SHAPER AND FILTER TPOPB TPOPA TPONA TPONB RC DO COLLISION/ POLARITY DETECT CORRECT MANCHESTER ENCODER STP (LXT901A only) RC RX SLICER TPIP TPIN DROP CABLE INTERFACE ECL TX AMP SQUELCH / LINK DETECT CD LEDL + DOP - DON LPBK RXD DI MANCHESTER DECODER RCLK DIN CI COLLISION LOGIC COL LEDR LEDT/PDN LEDC/FDE DSQE DIP RX SLICER NTH JAB COLLISION RECEIVER CIP CIN PLR (LXT907A only) Datasheet 7 LXT901A/907A — Universal 3.3V Ethernet Transceiver 1.0 Pin Assignments and Signal Descriptions MD1 MD0 NTH CIN CIP VCC1 DON DOP DIN DIP PAUI 6 5 4 3 2 1 44 43 42 41 40 Figure 2. LXT901A/907A Pin Assignments n/c 7 39 TPIN LI 8 38 TPIP JAB 9 37 DSQE (907A) or STP (901A) 36 TPONB 35 TPONA 34 VCC2 33 GND2 Rev # 10 TCLK 11 TXD 12 TEN 13 CLKO 14 32 TPOPA CLKI 15 31 TPOPB COL 16 30 PLR AUTOSEL 17 29 n/c LXT901A/907APC XX XXXXXX XXXXXXXX 23 24 25 26 27 28 GND1 RBIAS n/c RXD CD RCLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 22 21 LEDC/FDE LBK 19 20 18 LEDR LEDT/PDN LEDL Part # LOT # FPO # n/c n/c TPIN TPIP n/c DSQE (907A) or STP (901A) TPONB TPONA VCC2 GND2 TPOPA TPOPB PLR n/c n/c n/c TEST Rev # Part # LOT # FPO # LXT901A/907ALC XX XXXXXX XXXXXXXX 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 n/c RCLK CD RXD n/c n/c RBIAS n/c GNDA GND1 LBK LEDC/FDE LEDL LEDT/PDN LEDR n/c 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n/c n/c LI n/c JAB TEST TCLK TXD TEN CLKO CLKI COL AUTOSEL n/c n/c n/c n/c n/c PAUI DIP DIN n/c DOP DON VCCA VCC1 CIP CIN NTH MD0 MD1 n/c 8 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Table 1. LXT901A/907A Signal Descriptions Pin # Symbol I/O1 10 56 VCC1 VCC2 – – Power Supply 1 and 2. Power supply inputs of +3.3 volts. – 9 VCCA – Analog Supply. (+3.3V) 2 3 11 12 CIP CIN I I AUI Collision Pair. Differential input to the AUI transceiver CI circuit. The input is collision signaling or SQE. 4 13 NTH I PLCC LQFP 1 34 Description Normal Threshold. Selects normal or reduced threshold. When NTH is High, the normal TP squelch threshold is in effect. When NTH is Low, the normal TP squelch threshold is reduced by 4.5 dB. 5 6 14 15 MD0 MD1 I 8 19 LI I 9 21 JAB O Jabber Indicator. Output goes High to indicate Jabber state. I Mode Select 0 (MD0) and Mode Select 1 (MD1). Mode select pins determine the controller compatibility mode in accordance with Table 2. Link Test Enable. Controls Link Integrity Test; enabled when LI = High, disabled when LI = Low 10 22 TEST I Test. For Intel internal use only. It is recommended to tie this pin High externally. 11 23 TCLK O Transmit Clock. A 10 MHz clock output. This clock signal should be directly connected to the transmit clock input of the controller. 12 24 TXD I Transmit Data. Input signal containing NRZ data to be transmitted on the network. Connect TXD directly to the transmit data output of the controller. 13 25 TEN I Transmit Enable. Enables data transmission and starts the watchdog timer. Synchronous to TCLK (see Test Specifications for details). 14 15 26 27 CLKO CLKI O I Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or a 20 MHz clock applied at CLKI with CLKO left open. 16 28 COL O Collision Detect. Output which drives the collision detect input of the controller. Automatic Port Select. 17 29 AUTOSEL I When High, automatic port selection is enabled (the 901A/907A defaults to the AUI port only if TP link integrity = Fail). When Low, manual port selection is enabled (the PAUI pin determines the active port). 18 19 34 LEDR OD Receive LED. Open drain driver for the receive indicator LED. Output is pulled Low during receive. 35 LEDT/ PDN OD Transmit LED (LEDT)/Power Down (PDN). Open drain driver for the transmit indicator. Output is pulled Low during transmit. Do not allow this pin to float. If unused, tie High. If externally pulled Low, the LXT901A/907A goes to power down state. 20 36 LEDL OD Link LED. Open drain driver for link integrity indicator. Output is pulled Low during link test pass. If externally tied Low, internal circuitry is forced to “Link Pass” state and the 901A/ 907A will transmit link test pulses continuously. 1. I/O Column Coding: I = Input, O = Output, OD = Open Drain Datasheet 9 LXT901A/907A — Universal 3.3V Ethernet Transceiver Table 1. LXT901A/907A Signal Descriptions (Continued) Pin # Symbol PLCC I/O1 Description LQFP Collision LED (LEDC)/Full-Duplex Enable (FDE). Open drain driver for the collision indicator pulls Low during collision. 21 37 LEDC/ FDE LED “On” (i.e., Low output) time is extended by approximately 100 ms. OD If externally tied Low, enables full-duplex operation by disabling the internal TP loopback and collision detection circuits in anticipation of external TP loopback or full-duplex operation. If this pin is not used, tie high or directly to Vcc. 22 38 LBK I Loopback. Enables internal loopback mode. Refer to Functional Description for details. 23 33 39 55 GND1 GND2 – – Ground Returns 1 and 2. Grounds – 40 GNDA – Analog Ground. 24 42 RBIAS I Bias Control. A 12.4 kΩ 1% resistor to ground at this pin controls operating circuit bias. 26 45 RXD O Receive Data. Output signal. Connect directly to the receive data input of the controller. 27 46 CD O Carrier Detect. An output to notify the controller of activity on the network. 28 47 RCLK O Receive Clock. A recovered 10 MHz clock which is synchronous to the received data. Connect to the controller receive clock input. 30 52 PLR O Polarity Reverse. Output goes High to indicate reversed polarity at the TP input. 31 36 53 58 TPOPB TPONB O O 32 35 54 57 TPOPA TPONA O O Twisted-Pair Transmit Pairs A & B. Two differential driver pair outputs (A and B) to the twisted-pair cable. The outputs are pre-equalized. Each pair must be shorted together and tied to the transformer through a 24.9 Ω 1% series resistor to match impedance of 100 Ω. Refer to Figure 16 in the Applications Section for information on 150Ω configurations. STP Select (LXT901A only). 37 59 STP I When STP is Low, 150 Ω termination for shielded TP is selected. When STP is High, 100 Ω termination for unshielded TP is selected. LXT907A is designed for 100Ω UTP termination (not selectable). Disable SQE (LXT907A only). When DSQE is High, the SQE function is disabled. DSQE I When DSQE is Low, the SQE function is enabled. SQE must be disabled for normal operation in Hub/Switch applications. LXT901A operates with SQE enabled (not selectable). 38 39 61 62 TPIP TPIN I I Twisted-Pair Receive Pair. A differential input pair from the TP cable. Receive filter is integrated on-chip. No external filters are required. Port/AUI Select. In Manual Port Select mode (AUTOSEL Low), PAUI selects the active port. 40 3 PAUI I When PAUI is High, the AUI port is selected. When PAUI is Low, the TP port is selected. In Auto Port Select mode, PAUI must be tied to ground. 1. I/O Column Coding: I = Input, O = Output, OD = Open Drain 10 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Table 1. LXT901A/907A Signal Descriptions (Continued) Pin # Symbol I/O1 4 5 DIP DIN I I AUI Receive Pair. Differential input pair from the AUI transceiver DI circuit. The input is Manchester encoded. 43 44 7 8 DOP DON O O AUI Transmit Pair. A differential output driver pair for the AUI transceiver cable. The output is Manchester encoded. 7, 25, 29 1, 2, 6, 16, 17, 18, 20, 30, 31, 32, 33, 41, 43, 44, 48, 49, 50, 51, 60, 63, 64 N/C – No Connect (Internally tied to ground). PLCC LQFP 41 42 Description 1. I/O Column Coding: I = Input, O = Output, OD = Open Drain Datasheet 11 LXT901A/907A — Universal 3.3V Ethernet Transceiver 2.0 Functional Description The LXT901A/907A Universal Ethernet Interface Transceivers perform the physical layer signaling (PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. They function as a PLS-Only device (for use with 10BASE-2 or 10BASE-5 coaxial cable networks) or as an Integrated PLS/MAU (for use with 10BASE-T twisted-pair networks). In addition to standard 10 Mbps operation, they also support full-duplex 20 Mbps operation. The LXT901A/907A interfaces a back-end controller to either an AUI drop cable or a twisted-pair (TP) cable. The controller interface includes transmit and receive clock and NRZ data channels, as well as mode control logic and signaling. The AUI interface comprises three circuits: Data Output (DO), Data Input (DI) and Collision (CI). The twisted-pair interface comprises two circuits: Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces, the LXT901A/907A contains an internal crystal oscillator and four LED drivers for visual status reporting. Functions are defined from the back-end controller side of the interface. The Transmit function refers to data transmitted by the back-end to the AUI cable (PLS-Only mode) or to the twisted-pair network (Integrated PLS/MAU mode). The Receive function refers to data received by the backend from the AUI cable (PLS-Only) or from the twisted-pair network (Integrated PLS/MAU mode). In the integrated PLS/MAU mode, the LXT901A/907A performs all required MAU functions defined by the IEEE 802.3 10BASE–T specification such as collision detection, link integrity testing, signal quality error messaging, jabber control and loopback. In the PLS-Only mode, the LXT901A/907A receives incoming signals from the AUI DI circuit with ± 18 ns of jitter and drives the AUI DO circuit. 2.1 Controller Compatibility Modes The LXT901A/907A are compatible with most industry standard controllers including devices produced by Motorola, AMD, Intel, Fujitsu, National Semiconductor, Seeq and Texas Instruments. Four different control signal timing and polarity schemes (Modes 1 through 4) are required to achieve this compatibility. Mode select pins (MD0 and MD1) determine Controller compatibility modes as listed in Table 2. Refer to Test Specifications for a complete set of timing diagrams for each mode. 12 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Table 2. Controller Compatibility Modes Setting Controller Mode MD1 MD0 Low Low Low High High Low High High Mode 1 For Motorola 68EN360, MPC860, Advanced Micro Devices AM7990 or compatible controllers Mode 2 For Intel 82596 or compatible controllers1 Mode 3 For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005)2 Mode 4 For National Semiconductor 8390 or compatible controllers (TI TMS380C26) 1. Refer to Intel Application Note 51 when designing with Intel Controllers. 2. SEEQ controllers require inverters on CLK1, LBK, RCLK and COL. 2.2 Transmit Function The LXT901A/907A receives NRZ data from the controller at the TXD input, as shown in the block diagram on the first page of this Data Sheet, and passes it through a Manchester encoder. The encoded data is then transferred to either the AUI cable (the DO circuit) or the twisted-pair network (the TPO circuit). The advanced integrated pulse shaping and filtering network produces the output signal on TPON and TPOP as shown in Figure 3. The TPO output is pre-distorted and prefiltered to meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated filters simplify the design work required for FCC compliant EMI performance. During idle periods, the LXT901A/907A transmits link integrity test pulses on the TPO circuit (if LI is enabled and integrated PLS/ MAU mode is selected). External resistors control the termination impedance for the LXT907A. External resistors and the STP Pin control termination impedance on the LXT901A. Figure 3. TPO Output Waveform Datasheet 13 LXT901A/907A — Universal 3.3V Ethernet Transceiver 2.2.1 Jabber Control Function Figure 4 is a state diagram of the LXT901A/907A Jabber control function. The on-chip watchdog timer prevents the DTE from locking into a continuous transmit mode. When a transmission exceeds the time limit, the watchdog timer disables the transmit and loopback functions, and activates the JAB pin. Once the LXT901A/907A is in the jabber state, the TXD circuit must remain idle for a period of 250 to 750 ms before it will exit the jabber state. Figure 4. Jabber Control Function Power On No Output DO=Active Nonjabber Output Start_XMIT_MAX_Timer DO=Active ∗ XMIT_Max_Timer_Done DO=Idle Jab XMIT=Disable LPBK=Disable CI=SQE DO=Idle Unjab Wait Start_Unjab_Timer XMIT=Disable LPBK=Disable CI=SQE Unjab_ Timer_Done 2.2.2 DO=Active ∗ Unjab_Timer_Not_Done SQE Function In the integrated PLS/MAU mode, the LXT901A/907A supports the signal quality error (SQE) function as shown in Figure 5, although the SQE function can be disabled on the LXT907A. After every successful transmission on the 10BASE-T network, when SQE is enabled, the LXT901A/ 907A transmits the SQE signal for 10BT ± 5BT over the internal CI circuit which is indicated on the COL pin of the device. When using the AUI of the LXT901A/907A, the SQE function is determined by the external MAU attached. 14 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A 2.2.2.1 SQE Disable Function (LXT907A only) SQE must be disabled for normal operation in hub and switch applications. The LXT907A is configured with an SQE Disable function. The SQE function is disabled when DSQE is set High, and enabled when DSQE is Low. Figure 5. SQE Function Power On Output Idle DO=Active Output Detected DO=Idle SQE Wait Test Start_SQE_Test__Wait_Timer XMIT=Disable SQE_Test__Wait_Timer_Done ∗ XMIT=Enable SQE Test Start_SQE_Test_Timer CI=SQE SQE_Test_Timer_Done 2.3 Receive Function The LXT901A/907A receive function acquires timing and data from the twisted-pair network (the TPI circuit) or from the AUI (the DI circuit). Valid received signals are passed through the on-chip filters and Manchester decoder, then output as decoded NRZ data and receive timing on the RXD and RCLK pins, respectively. An internal RC filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. The receive function is activated only by valid data streams above the squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the LXT901A/907A receive function enters the idle state. If the polarity of the TPI circuit is reversed, LXT901A/907A detects the polarity reverse and reports it via the PLR output. The LXT901A/907A automatically corrects reversed polarity. Datasheet 15 LXT901A/907A — Universal 3.3V Ethernet Transceiver 2.3.1 Polarity Reverse Function The LXT901A/907A polarity reverse function uses both link pulses and end-of-frame data to determine the polarity of the received signal. A reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are received with a reversed start-of-idle. Whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to zero. If the LXT901A/907A enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. If Link Integrity Testing is disabled, polarity detection is based only on received data. Polarity correction is always enabled. 2.3.2 Collision Detection Function The collision detection function operates on the twisted- pair side of the interface. For standard (half-duplex) 10BASE-T operation, a collision is defined as the simultaneous presence of valid signals on both the TPI circuit and the TPO circuit. The LXT901A/907A reports collisions to the back-end via the COL pin. If the TPI circuit becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end over the RXD circuit, disabling normal loopback. Figure 6 is a state diagram of the LXT901A/907A collision detection function. Refer to Test Specifications for collision detection and COL/CI output timing. (NOTE: For full-duplex operation on the TP or AUI port, the collision detection circuitry must be disabled by setting FDE Low.) Figure 6. Collision Detection Function A DO=Active ∗ TPI=Idle ∗ XMIT=Enable Power On Idle TPI=Active Output Input TPO=DO DI=DO DI=TPI DO=Active ∗ TPI=Active ∗ XMIT=Enable DO=Active ∗ TPI=Active ∗ XMIT=Enable Collision A DO=Idle+ XMIT=Disable TPO=DO DI=TPI CI=SQE DO=Active ∗ TPI=Idle 16 A TPI=Idle DO=Idle Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A 2.4 Loopback Functions 2.4.1 Standard TP Loopback The LXT901A/907A provides the standard loopback function defined by the 10BASE-T specification for the twisted-pair port. The loopback function operates in conjunction with the transmit function. Data transmitted by the back-end is internally looped back within the LXT901A/ 907A from the TXD pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end. This standard loopback function is disabled when a data collision occurs, clearing the RXD circuit for the TPI data. Standard loopback is also disabled during link fail and jabber states. The LXT901A/907A also provides three additional loopback functions. 2.4.2 Forced TP Loopback “Forced” TP loopback is controlled by the LBK pin. When the TP port is selected and LBK is High, TP loopback is “forced”, overriding collisions on the TP circuit. When LBK is Low, normal loopback is in effect. 2.4.3 AUI Loopback AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High, data transmitted by the back-end is internally looped back from the TXD pin through the Manchester encoder/decoder to the RXD pin. When LBK is Low, no AUI loopback occurs. 2.4.4 External Loopback An external loopback mode, useful for system-level testing, is controlled by the LEDC/FDE pin. When LEDC/FDE is tied Low, the LXT901A/907A disables the collision detection and internal loopback circuits, to allow external loopback. External loopback mode can be set on either TP or AUI ports. 2.5 Link Integrity Test Function Figure 7 is a state diagram of the LXT901A/907A Link Integrity test function. The link integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled when the LI pin is tied High. When enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. The LXT901A/907A ignores any link integrity pulse with interval less than 2 - 7 ms. The LXT901A/907A will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses. Datasheet 17 LXT901A/907A — Universal 3.3V Ethernet Transceiver Figure 7. Link Integrity Test Function Power On Idle Test Start_Link_Loss_Timer Start_Link_Test_Min_Timer Link_Loss_Timer_Done ∗ TPI=Idle ∗ Link_Test_Rcvd=False TPI=Active+ (Link_Test_Rcvd=True ∗ Link_Test_Min_Timer_Done) Link Test Fail Reset Link Test Fail Wait Link_Count=0 XMIT=Disable RCVR=Disable TPI=Active XMIT=Disable RCVR=Disable LPBK=Disable Link_Count=Link_Count + 1 Link_Test_Rcvd=False ∗ TPI=Idle TPI=Active Link_Test_Rcvd=Idle ∗ TPI=Idle Link Test Fail Start_Link_Test_Min_Timer Start_Link_Test_Max_Timer XMIT=Disable RCVR=Disable LPBK=Disable TPI=Active + Link_Count=LC_Max Link_Test_Min_Timer_Done ∗ Link_Test_Rcvd=True Link Test Fail Extended XMIT=Disable RCVR=Disable LPBK=Disable TPI=Idle ∗ DO=Idle 18 (TPI=Idle ∗ Link_Test_Max_Timer_Done) + (Link_Test_Min_Timer_Not_Done ∗ Link_Test_Rcvd=True) Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A 2.6 Link Pulse Transmission When not transmitting data, the LXT901A/907A transmits 802.3-compliant standard link pulses. Figure 8 shows the link integrity pulse timing. Figure 8. Transmitted Link Integrity Pulse Timing 10-20 ms Datasheet 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 19 LXT901A/907A — Universal 3.3V Ethernet Transceiver 3.0 Application Information 3.1 Twisted-Pair Impedance Matching Resistors must be installed on each input and output pair to match impedance of the network media being used. The LXT907A is configured with 100Ω termination for Unshielded Twisted-Pair (UTP). In this case, the positive and negative sides of both output pairs are shorted together (TPOPA/TPOPB and TPONA/TPONB) and tied to the transformer through a 24.9 Ω 1% series resistor. The LXT901A is designed with an STP Select pin that allows the device to match both 100Ω and 150Ω media. A dual resistor combination can be configured to accommodate either line termination as shown in Figure 16. When 100Ω termination is selected, both A and B pairs are driven in parallel. When 150Ω termination is selected, the B pair is tri-stated and only the A pair is driven. 3.2 Crystal Information Designers should test and validate crystals before committing to a specific component. Based on limited evaluation, Table 3 lists some suitable crystals. Table 3. Suitable Crystals Manufacturer Part Number MP-1 MTRON MP-2 3.3 Magnetics Information The LXT901A and LXT907A require a 1:1 ratio for the receive transformer and a 1:√2 ratio for the transmit transformer on the twisted-pair interface. The AUI Interface requires a 1:1 ratio for the data-in, data-out, and collision-pair transformers. A cross-reference list of suitable magnetics and part numbers is available in Application Note 73, Magnetic Manufacturers, which can be found on the Intel web site (developer.intel.com/design/network/). Designers must test and validate all components for suitability in their applications. 20 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A 3.4 Typical Applications Figure 9 through Figure 16 show typical LXT901A/907A applications. 3.4.1 Auto Port Select with External Loopback Control Figure 9 is a typical LXT901A/907A application. The diagram is arranged to group similar pins together; it does not represent the actual LXT901A/907A pinout. The controller interface pins (transmit data, clock and enable; receive data and clock; and the collision detect, carrier detect and loopback control pins) are shown at the top left. Programmable option pins are grouped center left. The PAUI pin is tied Low and all other option pins are tied High. This setup selects the following options: • Automatic Port Selection (PAUI Low and AUTOSEL High) • • • • • Normal Receive Threshold (NTH High) Mode 4, compatible with National NS8390 controllers (MD0 High, MD1 High) SQE Disabled (DSQE High for LXT907A only) UTP is selected (STP High for LXT901A only) Link Testing Enabled (LI High) Status outputs are grouped at lower left. Local status outputs drive LED indicators. Power and ground pins are shown at the bottom of the diagram. A single power supply is used for both VCC1 and VCC2 with a decoupling capacitor installed between the power and ground busses. An additional power and ground pin (VCCA and GNDA) is supported in designs using the 64-pin LQFP package. A single power supply is used for all three power and ground pins (VCC1, VCC2, VCCA) and (GND1, GND2, GNDA). Install a decoupling capacitor between each power and ground buss. The TP and AUI interfaces are shown at upper and lower right, respectively. Impedance matching resistors for 100Ω UTP are installed in each I/O pair and no external filters are required. Datasheet 21 LXT901A/907A — Universal 3.3V Ethernet Transceiver Figure 9. LAN Adapter Board - Auto Port Select with External LPBK Control 20 pF 0.1 µF 20 pF 20 MHz 2 TXC NS8390 BACK-END CONTROLLER INTERFACE RXC RXD CRS COL LOOPBACK ENABLE LBK CLKO JAB PLR LINE STATUS 330 Green Red 330 330 Red Red 6 50 Ω TPIP 5 3 14 4 TPONB TPONA 3 24.9 Ω 1% 6 1 : 2 11 2 LXT901A/907A DSQE (907A) STP (901A) LI 1 : 1 16 50 Ω RXD CD COL LBK MD1 1 TPIN PAUI AUTOSEL NTH MD0 PROGRAMMING OPTIONS 330 RJ45 TXD TEN TCLK RCLK TPOPB TPOPA 78 Ω CIN 8 9 1 1 1 16 9 2 10 CIP LEDC/FDE LEDR LEDT/PDN LEDL 24.9 Ω 1% DON 2 3 15 78 Ω 4 1 : 1 13 11 4 12 5 DOP DIN 5 12 78 Ω 7 1 : 1 10 D - CONNECTOR to AUI DROP CABLE TXE CLKI To 10 BASE-T TWISTEDPAIR NETWORK TXD 13 6 14 7 15 8 TEST +3.3 V DIP Fuse 9 12.4 kΩ VCC1 RBIAS VCC2 1% GND1 22 8 GND2 1 1 Bias resistor RBIAS should be located close to the pin and isolated from other signals. 2 Optional: Centertap capacitor may improve EMC depending on board layout and system design. Chassis Gnd + 12 V Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A 3.4.2 Full-Duplex Support Figure 10 shows the LXT907A with a Texas Instruments 380C24 CommProcessor. The 380C24 is compatible with Mode 4 (MD0 and MD1 both High). When used with the 380C24, or other fullduplex capable controller, the LXT907A supports full-duplex Ethernet, effectively doubling the available bandwidth of the network. In this application the SQE function is enabled (DSQE tied Low), and the AUI port is not used. Figure 10. Full-Duplex Operation CLKI 2 TXD TXEN TXC RXC RXD CSN COLL LPBK *TEST0 OUTSEL0 1N914 1 4 CLKO TXD TEN TCLK RCLK RXD CD COL LBK LEDC/FDE RJ45 1 TPIN 6 50 Ω 50 Ω TPIP TPONB TPONA 24.9 Ω 1% 6 1 : 2 11 24.9 Ω 1% 8 9 LI LXT907A 4.7 KΩ NTH MD0 MD1 TPOPB TPOPA 330 Green Red Red 3 JAB PLR DON PAUI DOP LEDR LEDT/PDN LEDL 1 CIN CIP 330 14 2 DSQE (907A) 330 5 3 4 AUTOSEL LINE STATUS 1 : 1 16 10 KΩ *Open Collector Driver PROGRAMMING OPTIONS 0.1 µF 20 pF 20 MHz To 10 BASE-T TWISTEDPAIR NETWORK 20 pF TMS380C24 1 Half/Full Duplex Selection controlled by TMS380C24 Pins Test0 and OUTSEL0. 2 The TMS380C26 may be substituted for dual network support of 10BASE-T and Token Ring. 3 Bias resistor RBIAS should be located close to the pin and isolated from other signals. 4 Optional: Centertap capacitor may improve EMC depending on board layout and system design. DIN DIP TEST +3.3 V VCC1 12.4 kΩ RBIAS VCC2 GND1 GND2 1% 3 Datasheet 23 LXT901A/907A — Universal 3.3V Ethernet Transceiver 3.4.3 Dual Network Support - 10Base-T and Token Ring Figure 11 shows the LXT901A/907A with a Texas Instruments 380C26 CommProcessor. The 380C26 is compatible with Mode 4 (MD0 and MD1 both High). When used with the 380C26, both the LXT901A/907A and a TMS38054 Token Ring transceiver can be tied to a single RJ-45 allowing dual network support from a single connector. The LXT901A/907A AUI port is not used. The DSQE pin on the LXT907A is tied Low and the STP pin on the LXT901A is tied High. Figure 11. 380C26 Interface for Dual Network Support of 10BASE-T and Token Ring From TI TMS38054 Token Ring Transceiver To TI TMS38054 Token Ring Transceiver 380C26 CLKI TXD TXD TXE TXC RXC RXD CRS COL LBK 0.1 µF 20 pF 20 MHz 3 CLKO 2 1 TPIN TEN TCLK 6 50 Ω RCLK RXD 5 50 Ω 3 TPIP 14 CD COL 4 LBK TPONB TPONA AUTOSEL 24.9 Ω 1% 6 1 : 2 11 3 2 NTH MD0 PROGRAMMING OPTIONS RJ45 1 : 1 16 TPOPA MD1 24.9 Ω 1% 8 To 10 BASE-T TWISTEDPAIR NETWORK 20 pF 9 1 TPOPB STP 901A only JAB PLR LINE STATUS 330 330 Green Red 330 330 Red Red TEST PAUI LEDC/FDE LEDR LEDT/PDN LEDL LXT901A/907A DSQE 907A only LI CIN CIP 1 DON DOP Bias resistor RBIAS should be located close to the pin and isolated from other signals. 2 Additional magnetics and switching logic (not shown) are required to implement the dual network solution. 3 Optional: Centertap capacitor may improve EMC depending on board layout and system design. DIN DIP +3.3 V 12.4 kΩ VCC1 RBIAS VCC2 1% GND1 24 GND2 1 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A 3.4.4 Manual Port Select with Link Test Function With MD0 tied Low and MD1 tied High, the LXT901A/907A logic and framing are set to Mode 3 (compatible with Fujitsu MB86950 and MB86960, and Seeq 8005 controllers). Figure 12 shows the setup for Fujitsu controllers. Figure 13 shows the four inverters required to interface with the Seeq 8005 controller. As in Figure 9 on page 22 both these Mode 3 applications show the LI pin tied High, enabling Link Testing; and the STP (LXT901A only) and NTH pins are both tied High, selecting the standard receiver threshold and 100Ω termination for unshielded TP cable. However, in these applications AUTOSEL is tied Low, allowing external port selection through the PAUI pin. Figure 12. LAN Adapter Board - Manual Port Select with Link Test Function 20 pF 0.1 µF 20 pF 20 MHz TCKN MB86950 or MB86960 BACK-END/ CONTROLLER INTERFACE RCKN RXD XCD XCOL LBC Port Selection LINE STATUS 330 330 Green Red 330 Red 330 Red LEDC/FDE LEDR LEDT/PDN LEDL 6 5 50 Ω 3 14 4 TPONB TPONA 24.9 Ω 1% 6 1 : 2 11 24.9 Ω 1% 9 3 2 LXT901A/907A JAB PLR 16 TPIP PAUI AUTOSEL NTH DSQE (907A) STP (901A) 1:1 50 Ω CD COL LBK MD0 MD1 RJ45 1 TPIN RCLK RXD LI 2 CLKO TPOPA TPOPB 78 Ω CIN 8 1 1 1 16 9 2 10 2 CIP 78 Ω DON 3 15 11 4 1:1 4 13 12 5 5 DOP 78 Ω DIN To 10 BASE-T TWISTEDPAIR NETWORK TEN CLKI TXD TEN TCLK 7 12 1:1 10 D - CONNECTOR to AUI DROP CABLE TXD 13 6 14 7 15 8 TEST +3.3 V 8 DIP 12.4 kΩ VCC1 RBIAS VCC2 1% GND1 GND2 1 Datasheet Fuse 9 1 Bias resistor RBIAS should be located close to the pin and isolated from other signals. 2 Optional: Centertap capacitor may improve EMC depending on board layout and system design. Chassis Gnd + 12 V 25 LXT901A/907A — Universal 3.3V Ethernet Transceiver Figure 13. Manual Port Select with Seeq 8005 Controller External 20 MHz Source RxD RxC COLL TxEN TxC TxD Port Selection DSQE (907A) STP (901A) LI JAB PLR LINE STATUS 330 Green 330 Red 330 Red 330 Red LEDC/FDE LEDR LEDT/PDN LEDL RJ45 1 TPIN 16 6 50 Ω 5 50 Ω 3 14 TPIP 4 TPONB TPONA 24.9 Ω 1% 6 1 : 2 3 11 2 TPOPA 24.9 Ω 1% 8 9 1 TPOPB 78 Ω CIN 1 1 16 9 2 10 2 CIP 78 Ω DON 3 15 11 4 1:1 4 13 12 5 5 TEST 1:1 To 10 BASE-T TWISTEDPAIR NETWORK CSN 2 CLKO 12 13 6 DOP 78 W DIN 7 1:1 10 D - CONNECTOR to AUI DROP CABLE CLKI LBK CD RXD RCLK COL TEN TCLK TXD PAUI AUTOSEL NTH MD0 MD1 LPBK 8005 0.1 µF LXT901A/907A CLKI Left Open 14 7 15 8 8 DIP +3.3 V VCC1 RBIAS VCC2 12.4 kΩ 1% GND1 GND2 1 26 Fuse 9 1 Bias resistor RBIAS should be located close to the pin and isolated from other signals. 2 Optional: Centertap capacitor may improve EMC depending on board layout and system design. Chassis Gnd + 12 V Datasheet Datasheet 0.1 µF +3.3 V 10 k Ω Power Down 10 k Ω LINE STATUS MODE SELECT LinkTest Enable PROGRAMMING OPTIONS LBK CDT CRS RXD RXC RTS TXC TXD CLK 1 CLKO 12.4 kΩ 1% RBIAS TEST VCC2 VCC1 LEDL LEDT/PDN LEDR LEDC/FDE PLR JAB MD0 MD1 LI PAUI DSQE (907A) NTH AUTOSEL LBK COL CD RXD RCLK TCLK TEN TXD CLKI GND1 GND2 DIP DIN DOP DON CIP CIN TPOPB TPOPA TPONA TPONB TPIP TPIN 24.9 Ω 1% 24.9 Ω 1% 50 Ω 50 Ω 1:1 8 6 1:2 3 1 2 9 11 14 16 78 Ω 78 Ω 78 Ω 1 2 3 4 5 6 9 8 12 13 15 16 9 10 12 13 10 1:1 1:1 15 16 To 10BASE-T TWISTEDPAIR NETWORK 7 5 4 2 1 8 7 5 4 2 1 RJ45 Bias resistor RBIAS should be located close to the pin and isolated from other signals. 8 7 6 5 4 3 2 1.5 kΩ + 12 V Fuse D - CONNECTOR to AUI DROP CABLE (Thick Coax) HBE GND RXRX+ RR+ RR- VEE RXI TXD CDS TX+ VEE VEE TX- CD+ CD- DP8392 0.01 µF 1/2 W 1 MΩ -9V 1 kΩ 1% 1N916 0V 9 13 12 V- N/C V+ 24 23 3 1 2 75 µF / 1 kV GND GND EN 5V 5V PM6044 BNC to THIN COAX NETWORK Optional: Centertap capacitor may improve EMC depending on board layout and system design. 1 Chassis Gnd 15 14 13 12 11 10 9 2 1 +5 V 3.4.5 82596 BACK-END/ CONTROLLER INTERFACE 20 MHz System Clock 0.1 µF Universal 3.3V Ethernet Transceiver — LXT901A/907A Three Media Application Figure 14 shows the LXT907A in Mode 2 (compatible with Intel 82596 controllers) with additional media options for the AUI port. Two transformers are used to couple the AUI port to either a D-connector or a BNC connector. A DP8392 coax transceiver with PM6044 power supply are required to drive the thin coax network through the BNC. Figure 14. Three Media Application LXT907A 27 LXT901A/907A — Universal 3.3V Ethernet Transceiver 3.4.6 AUI Encoder/Decoder Only In this application (see Figure 15) the DTE is connected to a coaxial network through the AUI. AUTOSEL is tied Low and PAUI is tied High to manually select the AUI port. The twisted-pair port is not used. With MD1 and MD0 both Low, the logic and framing are set to Mode 1 (compatible with AMD AM7990 controllers). The LI pin is tied Low, disabling the link test function. The DSQE pin is also Low, enabling the SQE function on the LXT907A. The LBK input controls loopback. A 20 MHz system clock is supplied at CLK1 with CLK0 left open. Figure 15. AUI Encoder/Decoder Only Application Left Open 20 MHz TX TENA TCLK RCLK AM7990 BACK-END/ CONTROLLER INTERFACE RX RENA CLSN LOOPBACK CONTROL LBK CLKI CLKO TXD TEN TCLK RCLK RXD CD COL LBK AUTOSEL 78 Ω PAUI NTH MD0 MD1 PROGRAMMING OPTIONS CIN LINE STATUS 330 330 330 PLR 9 2 CIP LXT907A JAB 16 10 DSQE (907A) LI 1 1 DON 2 78 Ω 4 3 15 11 4 13 12 5 DOP DIN 5 78 Ω 7 13 12 6 14 10 D - CONNECTOR to AUI DROP CABLE SYSTEM CLOCK 7 330 15 8 GREEN Red Red Red LEDC/FDE LEDR LEDT/PDN LEDL 8 DIP Fuse 9 Chassis Gnd TEST +3.3 V VCC1 1 RBIAS VCC2 12.4 kΩ 1% GND1 GND2 28 + 12 V 1 Bias resistor RBIAS should be located close to the pin and isolated from the other signals Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A 150 Ω Shielded Twisted-pair only (LXT901A only) 3.4.7 Figure 16 shows the LXT901A in a typical twisted-pair only application. The DTE is connected to a 10BASE-T network through the twisted-pair RJ-45 connector. Note that the AUI port is not used. With MD0 tied High and MD1 Low, the LXT901A logic and framing are set to Mode 2 (compatible with Intel 82596 controllers). A 20 MHz system clock input at CLK1 is used in place of the crystal oscillator. (CLK0 is left open). The L1 pin externally controls the link test function. The STP and NTH pins are both tied Low, selecting the reduced receiver threshold and 150 Ω termination for shielded TP cable. The switch at LEDT/PDN manually controls the power down mode. Figure 16. 150 Ω Shielded Twisted-Pair Only Application (LXT901A) CLK TXD RTS TXC RXC RXD CRS CDT LBK 82596 BACK-END/ CONTROLLER INTERFACE 2 CLK1 TXD TEN TCLK RCLK RXD RCLK CD COL LBK AUTOSEL PAUI NTH MD0 PROGRAMMING OPTIONS MD1 STP RJ45 1 LINE STATUS 16 TPIN 6 75 Ω 75 Ω 5 3 14 TPIP 4 75 Ω 1% TPONB 6 TPONA 1: 2 11 37.5 Ω 1% 37.5 Ω 1% TPOPA 3 2 8 9 1 TPOPB 75 Ω 1% 10K JAB PLR TEST LEDC/FDE LEDR LEDL +3.3 V RBIAS LEDT/PDN VCC1 VCC2 Datasheet 1:1 LI Link Test Enable 10K 0.1 µF CLK0 To 10 BASE-T TWISTEDPAIR NETWORK Left Open LXT901A 20 MHz SYSTEM CLOCK 12.4 kΩ 1% 1 GND1 GND2 1 Bias resistor RBIAS should be located close to the pin and isolated from other signals. 2 Optional: Centertap capacitor may improve EMC depending on board layout and system design. 29 LXT901A/907A — Universal 3.3V Ethernet Transceiver 4.0 Test Specifications Note: Table 4. Table 4 through Table 13 and Figure 17 through Figure 42 represent the performance specifications of the LXT901A/907A. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in Table 6 through Table 13 apply over the recommended operating conditions specified in Table 5. Absolute Maximum Values Parameter Supply voltage Ambient operating temperature (Commercial) Storage temperature Symbol Min Max Units VCC -0.3 6 V TA 0 +70 ºC TSTG -65 +150 ºC Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5. Recommended Operating Conditions Parameter Recommended supply voltage Symbol Min Typ Max Units VCC 3.13 3.3 3.47 V TOP 0 – +70 ºC 1 Recommended operating temperature (Commercial) 1. Voltages with respect to ground unless otherwise specified. Power supply should be filtered to suppress high frequency transients, consistent with good PCB design. Table 6. I/O Electrical Characteristics Parameter Sym Min Typ1 Max Units Test Conditions Input Low voltage2 VIL – – 0.8 V Input High voltage2 VIH 2.0 – – V VOL – – 0.4 V IOL = 1.6 mA VOL – – 10 %VCC IOL < 10 µA VOLL – – 0.7 %VCC IOLL = 10 mA VOH 2.4 – – V IOH = 40 µA VOH 90 – – %VCC IOH < 10 µA Output Low voltage Output Low voltage (Open drain LED driver) Output High voltage Output rise time CMOS – – 7 12 ns TCLK & RCLK TTL – – 7 8 ns Output fall time CMOS – – 7 12 ns TCLK & RCLK TTL – – 7 8 ns CLKI rise time (externally driven) – – – 10 ns CLKI duty cycle (externally driven) – – 40/60 % CLOAD = 20 pF CLOAD= 20 pF 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0V and 3V. 30 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Table 6. I/O Electrical Characteristics (Continued) Parameter Supply current Normal Mode Power Down Mode Sym Min Typ1 ICC – ICC – ICC ICC Max Units Test Conditions 65 85 mA Idle Mode 95 120 mA Transmitting on TP – 95 120 mA Transmitting on AUI – 0.03 2 mA 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0V and 3V. Table 7. AUI Electrical Characteristics Symbol Min Typ1 Max Units Input Low current IIL – – -700 µA Input High current IIH – – 500 µA Differential output voltage VOD ±550 – ±1200 mV Differential squelch threshold VDS 150 250 350 mV Parameter Test Conditions 5 MHz square wave input 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Table 8. TP Electrical Characteristics Symbol Min Typ1 Max Units ZOUT – 5 – Ω Transmit timing jitter addition2 – – ±3.3 ±10 ns 0 line length for internal MAU Transmit timing jitter added by the MAU and PLS sections2, 3 – – ±3.3 ±5.5 ns After line model specified by IEEE 802.3 for 10BASE-T internal MAU ZIN – 20 – kΩ Between TPIP/TPIN, CIP/ CIN & DIP/DIN Normal threshold; NTH = 1 VDS 300 400 585 mV 5 MHz square wave input Reduced threshold; NTH = 0 VDS 180 250 345 mV 5 MHz square wave input Parameter Transmit output impedance Receive input impedance Differential squelch Threshold Test Conditions 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. 3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. Datasheet 31 LXT901A/907A — Universal 3.3V Ethernet Transceiver Table 9. Switching Characteristics Parameter Symbol Minimum Typical1 Maximum Units Maximum transmit time – 20 – 150 ms Unjab time – 250 – 750 ms Time link loss receive – 50 – 150 ms Link min receive – 2 – 7 ms Link max receive – 50 – 150 ms Link transmit period – 8 10 24 ms Jabber Timing Link Integrity Timing 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Table 10. RCLK/Start-of-Frame Timing Symbol Minimum Typical1 Maximum Units AUI tDATA – 900 1100 ns TP tDATA – 1200 1500 ns Parameter Decoder acquisition time AUI tCD – 25 200 ns TP tCD – 425 550 ns CD turn-on delay Receive data setup from RCLK Mode 1 tRDS 60 70 – ns Modes 2, 3 and 4 tRDS 30 45 – ns Receive data hold from RCLK Mode 1 tRDH 10 20 – ns Modes 2, 3 and 4 tRDH 30 45 – ns RCLK shut off delay from CD assert (LXT907A only; Mode 3) tsws – ±100 – ns 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. Table 11. RCLK/End-of-Frame Timing Parameter Type Sym Mode 1 Mode 2 Mode 3 Mode 4 Units RCLK after CD off Min tRC 5 1 27 5 BT Rcv data throughput delay Max tRD 400 375 375 375 ns 2 Max tCDOFF 500 475 475 475 ns Receive block out after TEN off Typ1 tIFG 5 50 – – BT RCLK switching delay after CD off (LXT907A only; Mode 3) Typ1 tSWE – – 120(±80) – ns CD turn off delay 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. 2. CD turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last bit. 32 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Table 12. Transmit Timing Parameter Symbol Minimum Typical 1 Maximum Units TEN setup from TCLK tEHCH 22 – – ns TXD setup from TCLK tDSCH 22 – – ns TEN hold after TCLK tCHEL 5 – – ns TXD hold after TCLK tCHDU 5 – – ns Transmit start-up delay - AUI tSTUD – 220 450 ns Transmit start-up delay - TP tSTUD – 430 450 ns Transmit through-put delay - AUI tTPD – – 300 ns Transmit through-put delay - TP tTPD – 300 350 ns 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. Table 13. Collision, COL/CI Output and Loopback Timing Typical1 Maximum Units – 40 500 ns – 420 500 ns tSQED 0.65 1.2 1.6 µs COL (SQE) Pulse Duration tSQEP 500 1000 1500 ns LBK setup from TEN tKHEH 10 25 – ns LBK hold after TEN tKHEL 10 0 – ns Parameter Symbol Minimum COL turn-on delay tCOLD COL turn-off delay tCOLOFF COL (SQE) Delay after TEN off 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 33 LXT901A/907A — Universal 3.3V Ethernet Transceiver 4.1 Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low) Figure 17 through Figure 22 Figure 17. Mode 1 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN or DIP/DIN tCD CD RCLK tRDS tRDH tDATA RXD 1 0 1 0 1 0 1 Figure 18. Mode 1 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN tCDOFF CD tRD tRC RCLK RXD 1 34 0 1 0 1 0 1 0 0 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Figure 19. Mode 1 Transmit Timing TEN tCHEL tEHCH TCLK tDSCH tCHDU TXD tSTUD tTPD TPO Figure 20. Mode 1 Collision Detect Timing CI tCOLD tCOLOFF COL Figure 21. Mode 1 COL/CI Output Timing TEN tSQED COL tSQEP Figure 22. Mode 1 Loopback Timing LBK tKHEH tKHEL TEN Datasheet 35 LXT901A/907A — Universal 3.3V Ethernet Transceiver 4.2 Timing Diagrams for Mode 2 (MD1=Low, MD0=High) Figure 23 through Figure 28 Figure 23. Mode 2 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN or DIP/DIN tCD CD RCLK tRDS tRDH tDATA RXD 1 0 1 0 1 0 1 Figure 24. Mode 2 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN CD tCDOFF tRD RCLK RXD 1 36 0 1 0 1 0 1 0 0 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Figure 25. Mode 2 Transmit Timing TEN tCHEL tEHCH TCLK tDSCH tCHDU TXD tSTUD tTPD TPO Figure 26. Mode 2 Collision Detect Timing CI tCOLD tCOLOFF COL Figure 27. Mode 2 COL/CI Output Timing tIFG TEN tSQED COL tSQEP Figure 28. Mode 2 Loopback Timing LBK tKHEH tKHEL TEN Datasheet 37 LXT901A/907A — Universal 3.3V Ethernet Transceiver 4.3 Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low) Figure 29 through Figure 36 Figure 29. Mode 3 RCLK/Start-of-Frame Timing (LXT901A) 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 TPIP/TPIN or DIP/DIN tCD CD RCLK tRDS tRDH tDATA RXD 1 0 1 0 1 1 0 1 Figure 30. Mode 3 RCLK/End-of-Frame Timing (LXT901A) 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN tCDOFF CD tRD RCLK 27 bits RXD 1 38 0 1 0 1 0 1 0 0 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A Figure 31. Mode 3 RCLK/Start-of-Frame Timing (LXT907A) 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 TPIP/TPIN or DIP/DIN tCD CD tSWS Recovered from Input Data Stream RCLK tRDS Generated from TCLK tRDH tDATA RXD 1 0 1 0 1 0 1 0 1 1 1 0 1 Figure 32. Mode 3 RCLK/End-of-Frame Timing (LXT907A) 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN tCDOFF CD tRD tSWE RCLK Recovered Clock Generated from TCLK RXD 1 Datasheet 0 1 0 1 0 1 0 0 39 LXT901A/907A — Universal 3.3V Ethernet Transceiver Figure 33. Mode 3 Transmit Timing TEN tCHEL tEHCH TCLK tDSCH tCHDU TXD tSTUD tTPD TPO Figure 34. Mode 3 Collision Detect Timing CI tCOLOFF tCOLD COL Figure 35. Mode 3 COL/CI Output Timing TEN tSQED tSQEP COL Figure 36. Mode 3 Loopback Timing LBK tKHEH tKHEL TEN 40 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A 4.4 Timing Diagrams for Mode 4 (MD1 = High, MD0 = High) Figure 37 through Figure 42 Figure 37. Mode 4 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 TPIP/TPIN or DIP/DIN tCD CD RCLK tRDS tRDH tDATA RXD 1 0 1 0 1 0 1 0 1 1 1 0 1 Figure 38. Mode 4 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN tCDOFF CD tRD RCLK RXD 1 Datasheet 0 1 0 1 0 1 0 0 41 LXT901A/907A — Universal 3.3V Ethernet Transceiver Figure 39. Mode 4 Transmit Timing TEN tCHEL tEHCH TCLK tDSCH tCHDU TXD tTPD tSTUD TPO Figure 40. Mode 4 Collision Detect Timing CI tCOLOFF tCOLD COL Figure 41. Mode 4 COL/CI Output Timing TEN tSQED COL tSQEP Figure 42. Mode 4 Loopback Timing LBK tKHEH tKHEL TEN 42 Datasheet Universal 3.3V Ethernet Transceiver — LXT901A/907A 5.0 Mechanical Specifications Figure 43. 44-Pin PLCC 44-Pin Plastic Leaded Chip Carrier • Part Number LXT901APC and LXT907APC (Commercial Temperature Range) CL Inches Millimeters C Dim Min Max Min Max A 0.165 0.180 4.191 4.572 A1 0.090 0.120 2.286 3.048 A2 0.062 0.083 1.575 2.108 B 0.050 – 1.270 – C 0.026 0.032 0.660 0.813 D 0.685 0.695 17.399 17.653 D1 0.650 0.656 16.510 16.662 F 0.013 0.021 0.330 0.533 B D1 D D A2 A A1 F Datasheet 43 LXT901A/907A — Universal 3.3V Ethernet Transceiver Figure 44. 64-Pin LQFP 64-Pin Low-Profile Quad Flat Package • Part Number LXT901ALC and LXT907ALC (Commercial Temperature Range) D Inches Millimeters D1 Dim Min Max Min Max A – 0.063 – 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.007 .011 0.17 0.27 D 0.472 BSC 12.00 BSC D1 0.394 BSC 10.00 BSC E 0.472 BSC 12.00 BSC E1 0.394 BSC 10.00 BSC e 0.020 BSC 0.50 BSC L 0.018 L1 θ3 θ 0.030 0.45 0.039 REF 11o 0 o e e/ 2 0.75 o 11o 0 o 13o θ3 L1 7o A2 A A1 L 44 E 1.00 REF 13o 7 E1 B θ θ3 Datasheet