AD ADSP-BF537KBCZ-6AV

Blackfin
Embedded Processor
ADSP-BF534/ADSP-BF536/ADSP-BF537
FEATURES
PERIPHERALS
Up to 600 MHz high performance Blackfin processor
Three 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.3 V core VDD with on-chip voltage regulation
2.5 V and 3.3 V-compliant I/O with specific 5 V-tolerant pins
182-ball and 208-ball CSP_BGA packages
IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and
ADSP-BF537 only)
Controller area network (CAN) 2.0B interface
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting eight stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 32 interrupt inputs
Serial peripheral interface (SPI) compatible
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timer/counters with PWM support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), 8 with high current drivers
On-chip PLL capable of 0.5ⴛ to 64ⴛ frequency multiplication
Debug/JTAG interface
MEMORY
Up to 132K bytes of on-chip memory
Instruction SRAM/cache and instruction SRAM
Data SRAM/cache plus additional dedicated data SRAM
Scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from SPI, TWI, and UART host devices
Memory management unit providing memory protection
JTAG TEST AND EMULATION
VOLTAGE REGULATOR
PERIPHERAL ACCESS BUS
B
L1
DATA
MEMORY
DMA
CONTROLLER
RTC
CAN
TWI
DMA CORE BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
PORT
J
SPORT0
SPORT1
DMA ACCESS BUS
EXTERNAL
ACCESS
BUS
INTERRUPT
CONTROLLER
DMA
EXTERNAL
BUS
L1
INSTRUCTION
MEMORY
PERIPHERAL ACCESS BUS
WATCHDOG TIMER
PPI
GPIO
PORT
G
UART 0-1
SPI
GPIO
PORT
F
TIMERS 0-7
16
ETHERNET MAC
(ADSP-BF536/
ADSP-BF537 ONLY)
BOOT ROM
GPIO
PORT
H
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADSP-BF534/ADSP-BF536/ADSP-BF537
TABLE OF CONTENTS
Features ................................................................. 1
Clock Signals ...................................................... 14
Memory ................................................................ 1
Booting Modes ................................................... 16
Peripherals ............................................................. 1
Instruction Set Description .................................... 17
Revision History ...................................................... 2
Development Tools .............................................. 17
General Description ................................................. 3
Designing an Emulator-Compatible Processor Board ... 18
Automotive Products ............................................. 3
Related Documents .............................................. 18
Portable Low Power Architecture ............................. 3
Pin Descriptions .................................................... 19
System Integration ................................................ 3
Specifications ........................................................ 24
Blackfin Processor Peripherals ................................. 3
Operating Conditions ........................................... 24
Blackfin Processor Core .......................................... 4
Electrical Characteristics ....................................... 26
Memory Architecture ............................................ 5
Absolute Maximum Ratings ................................... 29
DMA Controllers .................................................. 8
ESD Sensitivity ................................................... 30
Real-Time Clock ................................................... 9
Package Information ............................................ 30
Watchdog Timer .................................................. 9
Timing Specifications ........................................... 31
Timers ............................................................... 9
Output Drive Currents ......................................... 53
Serial Ports (SPORTs) .......................................... 10
Power Dissipation ............................................... 55
Serial Peripheral Interface (SPI) Port ....................... 10
Test Conditions .................................................. 55
UART Ports ...................................................... 10
Thermal Characteristics ........................................ 59
Controller Area Network (CAN) ............................ 11
182-Ball CSP_BGA Ball Assignment ........................... 60
TWI Controller Interface ...................................... 11
208-Ball Sparse CSP_BGA Ball Assignment .................. 63
10/100 Ethernet MAC .......................................... 11
Outline Dimensions ................................................ 66
Ports ................................................................ 12
Surface Mount Design .......................................... 67
Parallel Peripheral Interface (PPI) ........................... 12
Ordering Guide ..................................................... 68
Dynamic Power Management ................................ 13
Voltage Regulation .............................................. 14
REVISION HISTORY
3/08—Rev. D to Rev. E
Added new Automotive section. See Automotive Products 3
Added all 600 MHz data. See Processor Comparison ........ 3
Operating Conditions ............................................. 23
Electrical Characteristics .......................................... 25
Timing Specifications ............................................. 30
Added detailed static and dynamic power data and Activity
Scaling Factors.
Static Current–Low Power Process (mA) ..................... 27
Static Current–High Speed Process (mA) ..................... 27
Activity Scaling Factors ........................................... 28
Corrected General-Purpose Port Timing ..................... 45
Revised Figure 30, 10/100 Ethernet MAC Controller Timing:
RMII Receive Signal ............................................... 51
Revised Ordering Guide .......................................... 67
Rev. E |
Page 2 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
GENERAL DESCRIPTION
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are
members of the Blackfin® family of products, incorporating the
Analog Devices/Intel Micro Signal Architecture (MSA).
Blackfin processors combine a dual-MAC, state-of-the-art signal processing engine, the advantages of a clean, orthogonal
RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
AUTOMOTIVE PRODUCTS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are
completely code and pin compatible. They differ only with
respect to their performance, on-chip memory, and presence of
the Ethernet MAC module. Specific performance, memory, and
feature configurations are shown in Table 1.
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduction in power consumption, compared with just varying the
frequency of operation. This allows longer battery life for
portable appliances.
ADSP-BF536
ADSP-BF537
Features
Ethernet MAC
CAN
TWI
SPORTs
UARTs
SPI
GP Timers
Watchdog Timers
RTC
Parallel Peripheral Interface
GPIOs
L1 Instruction
SRAM/Cache
L1 Instruction
SRAM
Memory
L1 Data
Configuration SRAM/Cache
L1 Data SRAM
L1 Scratchpad
L3 Boot ROM
Maximum Speed Grade
Package Options:
Sparse CSP_BGA
CSP_BGA
ADSP-BF534
Table 1. Processor Comparison
—
1
1
2
2
1
8
1
1
1
48
16K bytes
1
1
1
2
2
1
8
1
1
1
48
16K bytes
1
1
1
2
2
1
8
1
1
1
48
16K bytes
48K bytes
48K bytes 48K bytes
32K bytes
32K bytes 32K bytes
32K bytes
4K bytes
2K bytes
500 MHz
—
4K bytes
2K bytes
400 MHz
32K bytes
4K bytes
2K bytes
600 MHz
208-Ball
182-Ball
208-Ball
182-Ball
208-Ball
182-Ball
PORTABLE LOW POWER ARCHITECTURE
SYSTEM INTEGRATION
By integrating a rich set of industry-leading system peripherals
and memory, the Blackfin processors are the platform of choice
for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal
processing in one integrated package.
Rev. E |
Some ADSP-BF534 models are available for automotive applications with controlled manufacturing. Note that these special
models may have specifications which differ from the general
release models. For information on which models are available
as automotive, see the Ordering Guide on Page 67.
The Blackfin processor is a highly integrated system-on-a-chip
solution for the next generation of embedded network-connected applications. By combining industry-standard interfaces
with a high performance signal processing core, cost-effective
applications can be developed quickly, without the need for
costly external components. The system peripherals include an
IEEE-compliant 802.3 10/100 Ethernet MAC (ADSP-BF536 and
ADSP-BF537 only), a CAN 2.0B controller, a TWI controller,
two UART ports, an SPI port, two serial ports (SPORTs), nine
general-purpose 32-bit timers (eight with PWM capability), a
real-time clock, a watchdog timer, and a parallel peripheral
interface (PPI).
BLACKFIN PROCESSOR PERIPHERALS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors contain a rich set of peripherals connected to the core via several
high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see
Figure 1). The processors contain dedicated network communication modules and high speed serial and parallel ports, an
interrupt controller for flexible management of interrupts from
the on-chip peripherals or external sources, and power management control functions to tailor the performance and power
characteristics of the processor and system to many application
scenarios.
All of the peripherals, except for the general-purpose I/O, CAN,
TWI, real-time clock, and timers, are supported by a flexible
DMA structure. There are also separate memory DMA channels
dedicated to data transfers between the processor’s various
memory spaces, including external SDRAM and asynchronous
memory. Multiple on-chip buses running at up to 133 MHz
provide enough bandwidth to keep the processor core running
along with activity on all of the on-chip and external
peripherals.
Page 3 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
The Blackfin processors include an on-chip voltage regulator in
support of the processors’ dynamic power management capability. The voltage regulator provides a range of core voltage levels
when supplied from a single 2.25 V to 3.6 V input. The voltage
regulator can be bypassed at the user’s discretion.
BLACKFIN PROCESSOR CORE
As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
The 40-bit shifter can perform shifts and rotates, and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
ADDRESS ARITHMETIC UNIT
I3
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
DA1 32
DA0 32
P1
TO MEMORY
P0
32
PREG
32
RAB
SD 32
LD1 32
LD0 32
ASTAT
32
32
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
SEQUENCER
ALIGN
16
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
A0
32
40
40
A1
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
Rev. E |
Page 4 of 68 |
March 2008
LOOP BUFFER
CONTROL
UNIT
ADSP-BF534/ADSP-BF536/ADSP-BF537
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have
three blocks of on-chip memory providing high-bandwidth
access to the core.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view
memory as a single unified 4G byte address space, using 32-bit
addresses. All resources, including internal memory, external
memory, and I/O control registers, occupy separate sections of
this common address space. The memory portions of this
address space are arranged in a hierarchical structure to provide
a good cost/performance balance of some very fast, low latency
on-chip memory as cache or SRAM, and larger, lower cost, and
performance off-chip memory systems. (See Figure 3).
The on-chip L1 memory system is the highest performance
memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 516M bytes of
physical memory.
Rev. E |
Internal (On-Chip) Memory
The first block is the L1 instruction memory, consisting of
64K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The third memory block is a 4K byte scratchpad SRAM, which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM, and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 512M bytes of SDRAM. A separate row can
be open for each SDRAM internal bank, and the SDRAM controller supports up to 4 internal SDRAM banks, improving
overall performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
I/O Memory Space
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do
not define a separate I/O space. All resources are mapped
through the flat 32-bit address space. On-chip I/O devices have
their control registers mapped into memory-mapped registers
(MMRs) at addresses near the top of the 4G byte address space.
These are separated into two smaller blocks, one which contains
the control MMRs for all core functions, and the other which
contains the registers needed for setup and control of the onchip peripherals outside of the core. The MMRs are accessible
only in supervisor mode and appear as reserved space to onchip peripherals.
Page 5 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
ADSP-BF534/ADSP-BF537 MEMORY MAP
ADSP-BF536 MEMORY MAP
0xFFFF FFFF
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTES)
CORE MMR REGISTERS (2M BYTES)
0xFFE0 0000
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTES)
SYSTEM MMR REGISTERS (2M BYTES)
0xFFC0 0000
0xFFC0 0000
RESERVED
RESERVED
SCRATCHPAD SRAM (4K BYTES)
SCRATCHPAD SRAM (4K BYTES)
0xFFB0 0000
0xFFB0 0000
RESERVED
INSTRUCTION SRAM/CACHE (16K BYTES)
0xFFA1 0000
RESERVED
0xFFA0 C000
INSTRUCTION BANK B SRAM (16K BYTES)
0xFFA0 8000
INSTRUCTION BANK A SRAM (32K BYTES)
0xFFA0 0000
RESERVED
0xFF90 8000
0xFFA1 4000
INTERNAL MEMORY MAP
RESERVED
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTES)
0xFFA1 0000
RESERVED
0xFFA0 C000
INSTRUCTION BANK B SRAM (16K BYTES)
0xFFA0 8000
INSTRUCTION BANK A SRAM (32K BYTES)
0xFFA0 0000
INTERNAL MEMORY MAP
0xFFB0 1000
0xFFB0 1000
RESERVED
0xFF90 8000
DATA BANK B SRAM/CACHE (16K BYTES)
DATA BANK B SRAM/CACHE (16K BYTES)
0xFF90 4000
0xFF90 4000
RESERVED
DATA BANK B SRAM (16K BYTES)
0xFF90 0000
0xFF90 0000
RESERVED
RESERVED
0xFF80 8000
0xFF80 8000
DATA BANK A SRAM/CACHE (16K BYTES)
DATA BANK A SRAM/CACHE (16K BYTES)
0xFF80 4000
0xFF80 4000
RESERVED
DATA BANK A SRAM (16K BYTES)
0xFF80 0000
0xFF80 0000
0xEF00 0800
BOOT ROM (2K BYTES)
EXTERNAL MEMORY MAP
BOOT ROM (2K BYTES)
0xEF00 0000
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTES)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTES)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTES)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTES)
0xEF00 0000
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTES)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTES)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTES)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTES)
EXTERNAL MEMORY MAP
RESERVED
RESERVED
0xEF00 0800
0x2000 0000
0x2000 0000
SDRAM MEMORY (16M BYTES TO 512M BYTES)
SDRAM MEMORY (16M BYTES TO 512M BYTES)
0x0000 0000
0x0000 0000
Figure 3. ADSP-BF534/ADSP-BF536/ADSP-BF537 Memory Maps
Booting
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
The Blackfin processor contains a small on-chip boot kernel,
which configures the appropriate peripheral for booting. If the
Blackfin processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot
ROM. For more information, see Booting Modes on Page 16.
• Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
Event Handling
The event controller on the Blackfin processor handles all asynchronous and synchronous events to the processor. The
Blackfin processor provides event handling that supports both
nesting and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for
five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
Rev. E |
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The Blackfin processor event controller consists of two stages:
the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system
interrupt controller to prioritize and control all system events.
Page 6 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Conceptually, interrupts from the peripherals enter into the
SIC, and are then routed directly into the general-purpose interrupts of the CEC.
Table 3. System Interrupt Controller (SIC)
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the Blackfin processor.
Table 2 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
Table 2. Core Event Controller (CEC)
Priority
(0 Is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General-Purpose Interrupt 7
General-Purpose Interrupt 8
General-Purpose Interrupt 9
General-Purpose Interrupt 10
General-Purpose Interrupt 11
General-Purpose Interrupt 12
General-Purpose Interrupt 13
General-Purpose Interrupt 14
General-Purpose Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment
registers (IAR). Table 3 describes the inputs into the SIC and the
default mappings into the CEC.
Rev. E |
Page 7 of 68 |
Peripheral Interrupt Event
PLL Wakeup
DMA Error (Generic)
DMAR0 Block Interrupt
DMAR1 Block Interrupt
DMAR0 Overflow Error
DMAR1 Overflow Error
CAN Error
Ethernet Error (ADSP-BF536 and
ADSP-BF537 only)
SPORT 0 Error
SPORT 1 Error
PPI Error
SPI Error
UART0 Error
UART1 Error
Real-Time Clock
DMA Channel 0 (PPI)
DMA Channel 3 (SPORT 0 Rx)
DMA Channel 4 (SPORT 0 Tx)
DMA Channel 5 (SPORT 1 Rx)
DMA Channel 6 (SPORT 1 Tx)
TWI
DMA Channel 7 (SPI)
DMA Channel 8 (UART0 Rx)
DMA Channel 9 (UART0 Tx)
DMA Channel 10 (UART1 Rx)
DMA Channel 11 (UART1 Tx)
CAN Rx
CAN Tx
DMA Channel 1 (Ethernet Rx,
ADSP-BF536 and ADSP-BF537 only)
Port H Interrupt A
DMA Channel 2 (Ethernet Tx,
ADSP-BF536 and ADSP-BF537 only)
Port H Interrupt B
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Port F, G Interrupt A
Port G Interrupt B
March 2008
Default
Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
Peripheral
Interrupt ID
0
1
1
1
1
1
2
2
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
2
2
2
2
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
IVG11
IVG11
17
18
IVG11
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
18
19
20
21
22
23
24
25
26
27
28
ADSP-BF534/ADSP-BF536/ADSP-BF537
• SIC interrupt wake-up enable register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more information, see Dynamic Power Management on Page 13.)
Table 3. System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event
DMA Channels 12 and 13
(Memory DMA Stream 0)
DMA Channels 14 and 15
(Memory DMA Stream 1)
Software Watchdog Timer
Port F Interrupt B
Default
Mapping
IVG13
Peripheral
Interrupt ID
29
IVG13
30
IVG13
IVG13
31
31
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
Event Control
The Blackfin processor provides a very flexible mechanism to
control the processing of events. In the CEC, three registers are
used to coordinate and control events. Each register is
16 bits wide:
• CEC interrupt latch register (ILAT) – Indicates when
events have been latched. The appropriate bit is set when
the processor has latched the event and cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared.
• CEC interrupt mask register (IMASK) – Controls the
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register may be read or
written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with
the STI and CLI instructions, respectively.)
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 7.
• SIC interrupt mask register (SIC_IMASK) – Controls the
masking and unmasking of each peripheral interrupt event.
When a bit is set in the register, that peripheral event is
unmasked and is processed by the system when asserted. A
cleared bit in the register masks the peripheral event, preventing the processor from servicing the event.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
DMA CONTROLLERS
The Blackfin processors have multiple, independent DMA
channels that support automated data transfers with minimal
overhead for the processor core. DMA transfers can occur
between the processor’s internal memories and any of its DMAcapable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and
external devices connected to the external memory interfaces,
including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the Ethernet
MAC (ADSP-BF536 and ADSP-BF537 only), SPORTs, SPI port,
UARTs, and PPI. Each individual DMA-capable peripheral has
at least one dedicated DMA channel.
The DMA controller supports both one-dimensional (1-D) and
two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of
parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be deinterleaved on the fly.
Examples of DMA types supported by the DMA controller
include
• SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.
Rev. E |
Page 8 of 68 |
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page.
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the processor system. This enables transfers of blocks of data between any of the memories—including
external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
RTXI
X1
C1
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors also
have an external DMA controller capability via dual external
DMA request pins when used in conjunction with the external
bus interface unit (EBIU). This functionality can be used when a
high speed interface is required for external FIFOs and high
bandwidth communications peripherals such as USB 2.0. It
allows control of the number of data transfers for memDMA.
The number of transfers per edge is programmable. This feature
can be programmed to allow memDMA to have an increased
priority on the external bus relative to the core.
REAL-TIME CLOCK
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the
processor. The RTC peripheral has dedicated power supply pins
so that it can remain powered up and clocked even when the
rest of the processor is in a low-power state. The RTC provides
several programmable interrupt options, including interrupt
per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a
programmed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day, while the second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the processor
from sleep mode upon generation of any RTC wake-up event.
Additionally, an RTC wake-up event can wake up the processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from the hibernate operating mode.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 4.
WATCHDOG TIMER
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
include a 32-bit timer that can be used to implement a software
watchdog function. A software watchdog can improve system
availability by forcing the processor to a known state through
generation of a system reset, nonmaskable interrupt (NMI), or
Rev. E |
RTXO
R1
C2
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12pF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22pF
C2 = 22pF
R1 = 10M⍀
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF.
Figure 4. External Components for RTC
general-purpose interrupt, if the timer expires before being reset
by software. The programmer initializes the count value of the
timer, enables the appropriate interrupt, then enables the timer.
Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are nine general-purpose programmable timer units in
the processor. Eight timers have an external pin that can be configured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized to an external clock input to the several other associated PF pins, to an external clock input to the
PPI_CLK input pin, or to the internal SCLK.
The timer units can be used in conjunction with the two UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generating periodic interrupts in an operating system.
Page 9 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
SERIAL PORTS (SPORTs)
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
incorporate two dual-channel synchronous serial ports
(SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features:
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 bits to 32 bits in length, transferred most significant
bit first or least significant bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
port provides a full-duplex, synchronous serial interface, which
supports both master/slave modes and multimaster
environments.
The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
f SCLK
SPI Clock Rate = -----------------------------------2 × SPI_BAUD
Where the 16-bit SPI_BAUD register contains a value of 2
to 65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
UART PORTS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors provide two full-duplex universal asynchronous receiver and
transmitter (UART) ports, which are fully compatible with PCstandard UARTs. Each UART port provides a simplified UART
interface to other peripherals or hosts, supporting full-duplex,
DMA-supported, asynchronous transfers of serial data. A
UART port includes support for five to eight data bits, one or
two stop bits, and none, even, or odd parity. Each UART port
supports two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer, or buffers,
through DMA.
• Multichannel capability – Each SPORT supports 128 channels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
Each UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK/16) bits per second.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have
an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master InputSlave Output, MISO) and a clock pin (serial clock, SCK). An SPI
chip select input pin (SPISS) lets other SPI devices select the
processor, and seven SPI chip select output pins (SPISEL7–1) let
the processor select other SPI devices. The SPI select pins are
reconfigured programmable flag pins. Using these pins, the SPI
Rev. E |
• Supporting data formats from 7 bits to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
f SCLK
UART Clock Rate = -------------------------------------------------16 × UARTx_Divisor
Where the 16-bit UARTx_Divisor comes from the
UARTx_DLH register (most significant 8 bits) and
UARTx_DLL register (least significant 8 bits).
Page 10 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
In conjunction with the general-purpose timer functions, autobaud detection is supported.
The capabilities of the UARTs are further extended with support for the infrared data association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
CONTROLLER AREA NETWORK (CAN)
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors offer
a CAN controller that is a communication controller implementing the CAN 2.0B (active) protocol. This protocol is an
asynchronous communications protocol used in both industrial
and automotive control systems. The CAN protocol is wellsuited for control applications due to its capability to communicate reliably over a network, since the protocol incorporates
CRC checking message error tracking, and fault node
confinement.
10/100 ETHERNET MAC
The ADSP-BF536 and ADSP-BF537 processors offer the capability to directly connect to a network by way of an embedded
fast Ethernet Media Access Controller (MAC) that supports
both 10-BaseT (10 Mbps) and 100-BaseT (100 Mbps) operation.
The 10/100 Ethernet MAC peripheral is fully compliant to the
IEEE 802.3-2002 standard, and it provides programmable features designed to minimize supervision, bus use, or message
processing by the rest of the processor system.
Some standard features are
• Support of MII and RMII protocols for external PHYs.
• Full duplex and half duplex modes.
• Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS.
• Media access management (in half-duplex operation): collision and contention handling, including control of
retransmission of collision frames and of back-off timing.
The CAN controller offers the following features:
• 32 mailboxes (eight receive only, eight transmit only, 16
configurable for receive or transmit).
• Flow control (in full-duplex operation): generation and
detection of PAUSE frames.
• Dedicated acceptance masks for each mailbox.
• Additional data filtering on first two bytes.
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers.
• Support for both the standard (11-bit) and extended
(29-bit) identifier (ID) message formats.
• Support for remote frames.
• SCLK operating range down to 25 MHz (active and sleep
operating modes).
• Active or passive network support.
• Internal loopback from Tx to Rx.
• CAN wake-up from hibernation mode (lowest static power
consumption mode).
Some advanced features are
• Interrupts, including: Tx complete, Rx complete, error,
global.
The electrical characteristics of each network connection are
very demanding so the CAN interface is typically divided into
two parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
CAN module represents only the controller part of the interface.
The controller interface supports connection to 3.3 V highspeed, fault-tolerant, single-wire transceivers.
TWI CONTROLLER INTERFACE
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
include a 2-wire interface (TWI) module for providing a simple
exchange method of control data between multiple devices. The
TWI is compatible with the widely used I2C® bus standard. The
TWI module offers the capabilities of simultaneous master and
slave operation, support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for
transferring clock (SCL) and data (SDA) and supports the
protocol at speeds up to 400 kbps. The TWI interface pins are
compatible with 5 V logic levels.
Additionally, the processor’s TWI module is fully compatible
with serial camera control bus (SCCB) functionality for easier
control of various CMOS camera sensor devices.
• Buffered crystal output to external PHY for support of a
single crystal system.
• Automatic checksum computation of IP header and IP
payload fields of Rx frames.
• Independent 32-bit descriptor-driven Rx and Tx DMA
channels.
• Frame status delivery to memory via DMA, including
frame completion semaphores, for efficient buffer queue
management in software.
• Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations.
• Convenient frame alignment modes support even 32-bit
alignment of encapsulated Rx or Tx IP packet data in memory after the 14-byte MAC header.
• Programmable Ethernet event interrupt supports any combination of
• Any selected Rx or Tx frame status conditions.
• PHY interrupt condition.
• Wake-up frame detected.
• Any selected MAC management counter(s) at
half-full.
• DMA descriptor error.
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value.
Rev. E |
Page 11 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
• Programmable Rx address filters, including a 64-bit
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, unicast, control, and damaged frames.
• GPIO interrupt sensitivity registers – The two GPIO interrupt sensitivity registers specify whether individual pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
• Advanced power management supporting unattended
transfer of Rx and Tx frames and status to/from external
memory via DMA during low power sleep mode.
• System wake-up from sleep operating mode upon magic
packet or any of four user-definable wake-up frame filters.
• Support for 802.3Q tagged VLAN frames.
• Programmable MDC clock rate and preamble suppression.
• In RMII operation, 7 unused pins may be configured as
GPIO pins for other purposes.
PORTS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
group the many peripheral signals to four ports—Port F, Port G,
Port H, and Port J. Most of the associated pins are shared by
multiple signals. The ports function as multiplexer controls.
Eight of the pins (Port F7–0) offer high source/high sink current
capabilities.
General-Purpose I/O (GPIO)
The processors have 48 bidirectional, general-purpose I/O
(GPIO) pins allocated across three separate GPIO modules—
PORTFIO, PORTGIO, and PORTHIO, associated with Port F,
Port G, and Port H, respectively. Port J does not provide GPIO
functionality. Each GPIO-capable pin shares functionality with
other processor peripherals via a multiplexing scheme; however,
the GPIO functionality is the default state of the device upon
power-up. Neither GPIO output or input drivers are active by
default. Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt
registers:
PARALLEL PERIPHERAL INTERFACE (PPI)
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel A/D and D/A converters, video
encoders and decoders, and other general-purpose peripherals.
The PPI consists of a dedicated input clock pin, up to three
frame synchronization pins, and up to 16 data pins. The input
clock supports parallel data rates up to half the system clock rate
and the synchronization signals can be configured as either
inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex
bidirectional transfer of 8- or 10-bit video data. Additionally,
on-chip decode of embedded start-of-line (SOL) and start-offield (SOF) preamble packets is supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
1. Input mode – Frame syncs and data are inputs into the PPI.
2. Frame capture mode – Frame syncs are outputs from the
PPI, but data are inputs.
• GPIO direction control register – Specifies the direction of
each individual GPIO pin as input or output.
• GPIO control and status registers – The processors employ
a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO
pins. Four control registers are provided. One register is
written in order to set pin values, one register is written in
order to clear pin values, one register is written in order to
toggle pin values, and one register is written in order to
specify a pin value. Reading the GPIO status register allows
software to interrogate the sense of the pins.
• GPIO interrupt mask registers – The two GPIO interrupt
mask registers allow each individual GPIO pin to function
as an interrupt to the processor. Similar to the two GPIO
control registers that are used to set and clear individual
pin values, one GPIO interrupt mask register sets bits to
enable interrupt function, and the other GPIO interrupt
mask register clears bits to disable interrupt function.
Rev. E |
3. Output mode – Frame syncs and data are outputs from the
PPI.
Input Mode
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit and 10-bit
through 16-bit data, programmable in the PPI_CONTROL
register.
Page 12 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Frame Capture Mode
Full-On Operating Mode—Maximum Performance
Frame capture mode allows the video source(s) to act as a slave
(for frame capture for example). The ADSP-BF534/
ADSP-BF536/ADSP-BF537 processors control when to read
from the video source(s). PPI_FS1 is an HSYNC output and
PPI_FS2 is a VSYNC output.
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
Output Mode
Active Operating Mode—Moderate Power Savings
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hardware signaling.
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured
L1 memories.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applications. Three distinct submodes are supported:
1. Active video only mode
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Sleep Operating Mode—High Dynamic Power Savings
2. Vertical blanking only mode
3. Entire field mode
Active Video Mode
Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_COUNT register).
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wake-up causes the processor
to sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transitions to the active mode.
System DMA access to L1 memory is not supported in
sleep mode.
Table 4. Power Settings
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Mode
Full On
Active
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
DYNAMIC POWER MANAGEMENT
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors provide five operating modes, each with a different performance
and power profile. In addition, dynamic power management
provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation.
Control of clocking to each of the peripherals also reduces
power consumption. See Table 4 for a summary of the power
settings for each mode. Also, see Table 15, Table 16 and
Table 17.
Rev. E |
PLL
PLL
Bypassed
Enabled No
Enabled/ Yes
Disabled
Enabled —
Disabled —
Sleep
Deep
Sleep
Hibernate Disabled
—
Core
Clock
(CCLK)
Enabled
Enabled
System
Clock
(SCLK)
Enabled
Enabled
Internal
Power
(VDDINT)
On
On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the
Page 13 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
processor to transition to the active mode. Assertion of RESET
while in deep sleep mode causes the processor to transition to
the full-on mode.
Hibernate State—Maximum Static Power Savings
reduction in power dissipation, while reducing the voltage by
25% reduces power dissipation by more than 40%. Further,
these power savings are additive, in that if the clock frequency
and supply voltage are both reduced, the power savings can be
dramatic, as shown in the following equations.
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all of
the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0 V to provide the greatest power savings. To
preserve the processor state, prior to removing power, any critical information stored internally (memory contents, register
contents, etc.) must be written to a nonvolatile storage device.
The power savings factor (PSF) is calculated as:
Since VDDEXT is still supplied in this mode, all of the external pins
three-state, unless otherwise specified. This allows other devices
that are connected to the processor to still have power applied
without drawing unwanted current.
VDDINTNOM is the nominal internal supply voltage
The Ethernet or CAN modules can wake up the internal supply
regulator. If the PH6 pin does not connect as PHYINT signal to
an external PHY device, it can be pulled low by any other device
to wake the processor up. The regulator can also be woken up by
a real-time clock wake-up event or by asserting the RESET pin.
All hibernate wake-up events initiate the hardware reset
sequence. Individual sources are enabled by the VR_CTL
register.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hibernate state. State variables may be held in external SRAM or
SDRAM. The SCKELOW bit in the VR_CTL register controls
whether SDRAM operates in self-refresh mode which allows it
to retain its content while the processor is in reset.
Power Savings
As shown in Table 5, the processors support three different
power domains which maximizes flexibility, while maintaining
compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
Table 5. Power Domains
Power Domain
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
f CCLKRED ⎛ V DDINTRED ⎞ 2 ⎛ T RED ⎞
- × -------------------------- × ------------PSF = -------------------f CCLKNOM ⎝ V DDINTNOM⎠ ⎝ T NOM ⎠
where:
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTRED is the reduced internal supply voltage
TNOM is the duration running at fCCLKNOM
TRED is the duration running at fCCLKRED
The percent power savings is calculated as
% power savings = ( 1 – PSF ) × 100%
VOLTAGE REGULATION
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors provide an on-chip voltage regulator that can generate appropriate
VDDINT voltage levels from the VDDEXT supply. See Operating
Conditions on Page 23 for regulator tolerances and acceptable
VDDEXT ranges for specific models.
Figure 5 shows the typical external components required to
complete the power management system. The regulator controls the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while keeping I/O power supplied. While in
hibernate mode, VDDEXT can still be applied, eliminating the need
for external buffers. The voltage regulator can be activated from
this power-down state by asserting the RESET pin, which then
initiates a boot sequence. The regulator can also be disabled and
bypassed at the user’s discretion. For additional information on
voltage regulation, see Switching Regulator Design Considerations for the ADSP-BF533 Blackfin Processors (EE-228).
VDD Range
VDDINT
VDDRTC
VDDEXT
The dynamic power management feature allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be
dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
Rev. E |
Page 14 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
VDDEXT
(LOW-INDUCTANCE)
BLACKFIN
SET OF DECOUPLING
CAPACITORS
CLKOUT
TO PLL CIRCUITRY
VDDEXT
+
EN
100µF
CLKBUF
10µH
100nF
+
VDDINT
+
100µF
EN
CLKIN
FDS9431A
100µF
10µF
LOW ESR
XTAL
330⍀*
FOR OVERTONE
OPERATION ONLY:
ZHCS1000
VROUT
18pF*
SHORT AND LOWINDUCTANCE WIRE
18pF*
VROUT
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
GND
Figure 6. External Crystal Connections
Figure 5. Voltage Regulator Circuit
CLOCK SIGNALS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors can
be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processors include an on-chip oscillator circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 6. A
parallel-resonant, fundamental frequency, microprocessorgrade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 kΩ range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in
Figure 6 fine-tune phase and amplitude of the sine frequency.
The capacitor and resistor values shown in Figure 6 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations of multiple
devices over temperature range.
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 6. A design procedure for third-overtone operation is discussed in detail in the application note Using Third
Overtone Crystals with the ADSP-218x DSP (EE-168).
The CLKBUF pin is an output pin, and is a buffer version of the
input clock. This pin is particularly useful in Ethernet applications to limit the number of required clock sources in the
Rev. E |
system. In this type of application, a single 25 MHz or 50 MHz
crystal may be applied directly to the processors. The 25 MHz or
50 MHz output of CLKBUF can then be connected to an external Ethernet MII or RMII PHY device.
Because of the default 10× PLL multiplier, providing a 50 MHz
CLKIN exceeds the recommended operating conditions of the
lower speed grades. Because of this restriction, an RMII PHY
requiring a 50 MHz clock input cannot be clocked directly from
the CLKBUF pin for the lower speed grades. In this case, either
provide a separate 50 MHz clock source, or use an RMII PHY
with 25 MHz clock input options. The CLKBUF output is active
by default and can be disabled using the VR_CTL register for
power savings.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 7, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 0.5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 10×, but it can be modified by a software instruction sequence in the PLL_CTL register.
On-the-fly CCLK and SCLK frequency changes can be effected
by simply writing to the PLL_DIV register. Whereas the maximum allowed CCLK and SCLK rates depend on the applied
voltages VDDINT and VDDEXT, the VCO is always permitted to run
up to the frequency specified by the part’s speed grade. The
CLKOUT pin reflects the SCLK frequency to the off-chip world.
It belongs to the SDRAM interface, but it functions as reference
signal in other timing specifications as well. While active by
default, it can be disabled using the EBIU_SDGCTL and
EBIU_AMGCTL registers.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Page 15 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 8. Booting Modes
FINE ADJUSTMENT
REQUIRES PLL SEQUENCING
COURSE ADJUSTMENT
ON-THE-F LY
ⴜ 1, 2, 4, 8
CLKIN
PLL
0.5⫻ TO 64⫻
BMODE2–0
000
CCLK
001
VCO
ⴜ 1 TO 15
SCLK
010
011
100
101
110
111
SCLK ≤ CCLK
SCLK ≤ 133MHz
Figure 7. Frequency Modification Methods
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, implement the following modes:
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
0001
0110
1010
Divider Ratio
VCO/SCLK
1:1
6:1
10:1
Example Frequency Ratios
(MHz)
VCO
SCLK
100
100
300
50
500
50
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
Example Frequency Ratios
(MHz)
VCO
CCLK
300
300
300
150
500
125
200
25
The maximum CCLK frequency not only depends on the part’s
speed grade (see Ordering Guide on Page 67), it also depends on
the applied VDDINT voltage (see Table 10, Table 11, and Table 12
on Page 24 for details). The maximal system clock rate (SCLK)
depends on the chip package and the applied VDDEXT voltage (see
Table 14 on Page 24).
BOOTING MODES
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor has six
mechanisms (listed in Table 8) for automatically loading internal and external memory after a reset. A seventh mode is
provided to execute from external memory, bypassing the boot
Rev. E |
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit and 16-bit external flash memory – The
8-bit or 16-bit flash boot routine located in Boot ROM
memory space is set up using asynchronous memory
bank 0. All configuration settings are set for the slowest
device possible (3-cycle hold time; 15-cycle R/W access
times; 4-cycle setup). The Boot ROM evaluates the first
byte of the boot stream at address 0x2000 0000. If it is 0x40,
8-bit boot is performed. A 0x60 byte assumes a 16-bit
memory device and performs 8-bit DMA. A 0x20 byte also
assumes 16-bit memory but performs 16-bit DMA.
• Boot from serial SPI memory (EEPROM or flash) – 8-, 16-,
or 24-bit addressable devices are supported as well as
AT45DB041, AT45DB081, AT45DB161, AT45DB321,
AT45DB642, and AT45DB1282 DataFlash® devices from
Atmel. The SPI uses the PF10/SPI SSEL1 output pin to
select a single SPI EEPROM/flash device, submits a read
command and successive address bytes (0x00) until a valid
8-, 16-, or 24-bit, or Atmel addressable device is detected,
and begins clocking data into the processor.
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Description
Execute from 16-bit external memory (bypass
boot ROM)
Boot from 8-bit or 16-bit memory
(EPROM/flash)
Reserved
Boot from serial SPI memory (EEPROM/flash)
Boot from SPI host (slave mode)
Boot from serial TWI memory (EEPROM/flash)
Boot from TWI host (slave mode)
Boot from UART host (slave mode)
Page 16 of 68 |
• Boot from SPI host device – The Blackfin processor operates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is chosen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
• Boot from UART – Using an autobaud handshake
sequence, a boot-stream-formatted program is downloaded
by the host. The host agent selects a baud rate within the
UART’s clocking capabilities. When performing the autobaud, the UART expects an [email protected] (boot stream) character
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
(8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD
pin to determine the bit rate. It then replies with an
acknowledgement that is composed of 4 bytes: 0xBF, the
value of UART_DLL, the value of UART_DLH, and 0x00.
The host can then download the boot stream. When the
processor needs to hold off the host, it deasserts CTS.
Therefore, the host must monitor this signal.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• Boot from serial TWI memory (EEPROM/flash) – The
Blackfin processor operates in master mode and selects the
TWI slave with the unique ID 0xA0. It submits successive
read commands to the memory device starting at 2-byte
internal address 0x0000 and begins clocking data into the
processor. The TWI memory device should comply with
Philips I2C Bus Specification version 2.1 and have the capability to auto-increment its internal address counter such
that the contents of the memory device can be read
sequentially.
• Boot from TWI host – The TWI host agent selects the slave
with the unique ID 0x5F. The processor replies with an
acknowledgement and the host can then download the
boot stream. The TWI host agent should comply with
Philips I2C Bus Specification version 2.1. An I2C multiplexer can be used to select one processor at a time when
booting multiple processors from a single TWI.
For each of the boot modes, a 10-byte header is first brought in
from an external device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
To augment the boot modes, a secondary software loader can be
added to provide additional booting mechanisms. This secondary loader could provide the capability to boot from flash,
variable baud rate, and other sources. In all boot modes except
bypass, program execution starts from on-chip L1 memory
address 0xFFA0 0000.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the
programmer to use many of the processor core resources in a
single instruction. Coupled with many features more often seen
on microcontrollers, this instruction set is very efficient when
compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor
resources.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
DEVELOPMENT TOOLS
Blackfin processors are supported with a complete set of
CROSSCORE®† software and hardware development tools,
including Analog Devices emulators and the VisualDSP++®‡
development environment. The same emulator hardware that
supports other Analog Devices processors also fully emulates
the Blackfin processor family.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler that is based on an algebraic
syntax, an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient
translation of C/C++ code to Blackfin assembly. The Blackfin
processor has architectural features that improve the efficiency
of compiled C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
†
‡
Rev. E |
Page 17 of 68 |
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can
• View mixed C/C++ and assembly code (interleaved source
and object information).
• Insert breakpoints.
• Set conditional breakpoints on registers, memory, and
stacks.
• Trace instruction execution.
Analog Devices emulators use the IEEE 1149.1 JTAG test access
port of the Blackfin to monitor and control the target board
processor during emulation. The emulator provides full-speed
emulation, allowing inspection and modification of memory,
registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the
emulator does not affect target system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
• Perform linear or statistical profiling of program execution.
EZ-KIT Lite® Evaluation Board
• Fill, dump, and graphically plot the contents of memory.
For evaluation of ADSP-BF534/ADSP-BF536/ADSP-BF537
processors, use the ADSP-BF537 EZ-KIT Lite board available
from Analog Devices. Order part number
ADDS-BF537-EZLITE. The board comes with on-chip
emulation capabilities and is equipped to enable software
development. Multiple daughter cards are available.
• Perform source level debugging.
• Create custom debugger windows.
The VisualDSP++ IDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all development tools,
including color syntax highlighting in the VisualDSP++ editor.
These capabilities permit programmers to
• Control how the development tools process inputs and
generate outputs.
• Maintain a one-to-one correspondence with the tool’s
command line switches.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of embedded, real-time
programming. These capabilities enable engineers to develop
code more effectively, eliminating the need to start from the
very beginning when developing new application code. The
VDK features include threads, critical and unscheduled regions,
semaphores, events, and device flags. The VDK also supports
priority-based, pre-emptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be
scalable. If the application does not use a specific feature, the
support code for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used with standard
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks
and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the
system state when debugging an application that uses the VDK.
The expert linker can be used to visually manipulate the placement of code and data in the embedded system. Memory
utilization can be viewed in a color-coded graphical form. Code
and data can be easily moved to different areas of the processor
or external memory with the drag of the mouse. Runtime stack
and heap usage can be examined. The expert linker is fully compatible with existing linker definition file (LDF), allowing the
developer to move between the graphical and textual
environments.
Rev. E |
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every system developer needs in order to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG processor. The
emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
processor must be halted to send data and commands, but once
an operation has been completed by the emulator, the processor
system is set running at full speed with no impact on
system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see Analog Devices JTAG Emulation Technical Reference
(EE-68) on the Analog Devices website under
www.analog.com/ee-notes. This document is updated regularly
to keep pace with improvements to emulator support.
RELATED DOCUMENTS
The following publications that describe the ADSP-BF534/
ADSP-BF536/ADSP-BF537 processors (and related processors)
can be ordered from any Analog Devices sales office or accessed
electronically on our website:
Page 18 of 68 |
• Getting Started with Blackfin Processors
• ADSP-BF537 Blackfin Processor Hardware Reference
• ADSP-BF53x/ADSP-BF56x Blackfin Processor Programming Reference
• ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
PIN DESCRIPTIONS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pin
definitions are listed in Table 9. In order to maintain maximum
functionality and reduce package size and pin count, some pins
have dual, multiplexed functions. In cases where pin function is
reconfigurable, the default state is shown in plain text, while the
alternate function is shown in italics. Pins shown with an asterisk after their name (*) offer high source/high sink current
capabilities.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchronous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate. If, however
the BR pin is asserted, then the memory pins are also threestated.
All I/O pins have their input buffers disabled with the exception
of the pins noted in the data sheet that need pull-ups or pulldowns if unused.
The SDA (serial data) and SCL (serial clock) pins are open drain
and therefore require a pull-up resistor. Consult version 2.1 of
the I2C specification for the proper resistor value.
Table 9. Pin Descriptions
Pin Name
Memory Interface
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
Asynchronous Memory Control
AMS3–0
ARDY
AOE
ARE
AWE
Synchronous Memory Control
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Driver
Type1
Type Function
O
I/O
O
I
O
O
Address Bus for Async Access
Data Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access
Bus Request (This pin should be pulled high when not used)
Bus Grant
Bus Grant Hang
O
I
O
O
O
Bank Select
Hardware Ready Control
Output Enable
Read Enable
Write Enable
A
A
A
O
O
O
O
O
O
O
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable (This pin is three-stated during hibernate.
Clock Output
A10 Pin
Bank Select
A
A
A
A
B
A
A
Rev. E |
Page 19 of 68 |
A
A
A
A
A
A
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 9. Pin Descriptions (Continued)
Pin Name
Port F: GPIO/UART1–0/Timer7–0/SPI/
External DMA Request/PPI
(* = High Source/High Sink Pin)
PF0* – GPIO/UART0 TX/DMAR0
PF1* – GPIO/UART0
RX/DMAR1/TACI1
PF2* – GPIO/UART1 TX/TMR7
PF3* – GPIO/UART1 RX/TMR6/TACI6
PF4* – GPIO/TMR5/SPI SSEL6
PF5* – GPIO/TMR4/SPI SSEL5
PF6* – GPIO/TMR3/SPI SSEL4
PF7* – GPIO/TMR2/PPI FS3
PF8 – GPIO/TMR1/PPI FS2
PF9 – GPIO/TMR0/PPI FS1
PF10 – GPIO/SPI SSEL1
PF11 – GPIO/SPI MOSI
PF12 – GPIO/SPI MISO
Type Function
Driver
Type1
I/O
I/O
GPIO/UART0 Transmit/DMA Request 0
GPIO/UART0 Receive/DMA Request 1/Timer1 Alternate Input Capture
C
C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/UART1 Transmit/Timer7
GPIO/UART1 Receive/Timer6/Timer6 Alternate Input Capture
GPIO/Timer5/SPI Slave Select Enable 6
GPIO/Timer4/SPI Slave Select Enable 5
GPIO/Timer3/SPI Slave Select Enable 4
GPIO/Timer2/PPI Frame Sync 3
GPIO/Timer1/PPI Frame Sync 2
GPIO/Timer0/PPI Frame Sync 1
GPIO/SPI Slave Select Enable 1
GPIO/SPI Master Out Slave In
GPIO/SPI Master In Slave Out (This pin should be pulled high through a 4.7 kΩ
resistor if booting via the SPI port)
GPIO/SPI Clock
GPIO/SPI Slave Select/Alternate Timer0
Clock Input
GPIO/PPI Clock/External Timer Reference
C
C
C
C
C
C
C
C
C
C
C
GPIO/PPI Data 0
GPIO/PPI Data 1
GPIO/PPI Data 2
GPIO/PPI Data 3
GPIO/PPI Data 4
GPIO/PPI Data 5
GPIO/PPI Data 6
GPIO/PPI Data 7
GPIO/PPI Data 8/SPORT1 Receive Data
Secondary
GPIO/PPI Data 9/SPORT1 Transmit Data Secondary
GPIO/PPI Data 10/SPORT1 Receive Serial Clock
GPIO/PPI Data 11/SPORT1 Receive Frame Sync
GPIO/PPI Data 12/SPORT1 Receive Data Primary
GPIO/PPI Data 13/SPORT1 Transmit Serial Clock
GPIO/PPI Data 14/SPORT1 Transmit Frame Sync
GPIO/PPI Data 15/SPORT1 Transmit Data Primary
C
C
C
C
C
C
C
C
C
PF13 – GPIO/SPI SCK
PF14 – GPIO/SPI SS/TACLK0
I/O
I/O
PF15 – GPIO/PPI CLK/TMRCLK
Port G: GPIO/PPI/SPORT1
PG0 – GPIO/PPI D0
PG1 – GPIO/PPI D1
PG2 – GPIO/PPI D2
PG3 – GPIO/PPI D3
PG4 – GPIO/PPI D4
PG5 – GPIO/PPI D5
PG6 – GPIO/PPI D6
PG7 – GPIO/PPI D7
PG8 – GPIO/PPI D8/DR1SEC
I/O
PG9 – GPIO/PPI D9/DT1SEC
PG10 – GPIO/PPI D10/RSCLK1
PG11 – GPIO/PPI D11/RFS1
PG12 – GPIO/PPI D12/DR1PRI
PG13 – GPIO/PPI D13/TSCLK1
PG14 – GPIO/PPI D14/TFS1
PG15 – GPIO/PPI D15/DT1PRI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Rev. E |
Page 20 of 68 |
March 2008
D
C
C
C
D
C
C
D
C
C
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 9. Pin Descriptions (Continued)
Pin Name
Port H: GPIO/10/100 Ethernet MAC (On
ADSP-BF534, these pins are GPIO only)
PH0 – GPIO/ETxD0
PH1 – GPIO/ETxD1
PH2 – GPIO/ETxD2
PH3 – GPIO/ETxD3
PH4 – GPIO/ETxEN
PH5 – GPIO/MII TxCLK/RMII
REF_CLK
PH6 – GPIO/MII PHYINT/RMII
MDINT
PH7 – GPIO/COL
PH8 – GPIO/ERxD0
PH9 – GPIO/ERxD1
PH10 – GPIO/ERxD2
PH11 – GPIO/ERxD3
PH12 – GPIO/ERxDV/TACLK5
PH13 – GPIO/ERxCLK/TACLK6
PH14 – GPIO/ERxER/TACLK7
PH15 – GPIO/MII CRS/RMII CRS_DV
Port J: SPORT0/TWI/SPI Select/CAN
PJ0 – MDC
PJ1 – MDIO
PJ2 – SCL
PJ3 – SDA
PJ4 – DR0SEC/CANRX/TACI0
PJ5 – DT0SEC/CANTX/SPI SSEL7
PJ6 – RSCLK0/TACLK2
PJ7 – RFS0/TACLK3
PJ8 – DR0PRI/TACLK4
PJ9 – TSCLK0/TACLK1
PJ10 – TFS0/SPI SSEL3
PJ11 – DT0PRI/SPI SSEL2
Real-Time Clock
RTXI
RTXO
JTAG Port
TCK
TDO
TDI
TMS
TRST
EMU
Type Function
Driver
Type1
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/Ethernet MII or RMII Transmit D0
GPIO/Ethernet MII or RMII Transmit D1
GPIO/Ethernet MII Transmit D2
GPIO/Ethernet MII Transmit D3
GPIO/Ethernet MII or RMII Transmit Enable
GPIO/Ethernet MII Transmit Clock/RMII Reference Clock
E
E
E
E
E
E
I/O
GPIO/Ethernet MII PHY Interrupt/RMII Management Data Interrupt (This pin
should be pulled high when used as a hibernate wake-up.)
GPIO/Ethernet Collision
GPIO/Ethernet MII or RMII Receive D0
GPIO/Ethernet MII or RMII Receive D1
GPIO/Ethernet MII Receive D2
GPIO/Ethernet MII Receive D3
GPIO/Ethernet MII Receive Data Valid/Alternate Timer5 Input Clock
GPIO/Ethernet MII Receive Clock/Alternate
Timer6 Input Clock
GPIO/Ethernet MII or RMII Receive Error/Alternate Timer7 Input Clock
GPIO/Ethernet MII Carrier Sense/Ethernet RMII Carrier Sense and Receive Data
Valid
E
E
I/O
I/O
I
O
I/O
I/O
I
I/O
I/O
O
Ethernet Management Channel Clock (On ADSP-BF534 processors, do not
connect this pin, and tie PJ1 to ground)
Ethernet Management Channel Serial Data (On ADSP-BF534 processors, tie this
pin to ground)
TWI Serial Clock
TWI Serial Data
SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input Capture
SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select Enable 7
SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input
SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input
SPORT0 Receive Data Primary/Alternate Timer4 Clock Input
SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input
SPORT0 Transmit Frame Sync/SPI Slave Select Enable 3
SPORT0 Transmit Data Primary/SPI Slave Select Enable 2
I
O
RTC Crystal Input (This pin should be pulled low when not used)
RTC Crystal Output
I
O
I
I
I
O
JTAG Clock
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset (This pin should be pulled low if the JTAG port is not used)
Emulation Output
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
Rev. E |
Page 21 of 68 |
March 2008
E
E
E
E
E
E
E
E
E
E
F
F
C
D
C
D
C
C
C
C
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 9. Pin Descriptions (Continued)
Pin Name
Clock
CLKIN
XTAL
CLKBUF
Mode Controls
RESET
NMI
BMODE2–0
Voltage Regulator
VROUT0
VROUT1
Supplies
VDDEXT
VDDINT
VDDRTC
GND
1
Type Function
Driver
Type1
I
O
O
Clock/Crystal Input
Crystal Output
Buffered XTAL Output
E
I
I
I
Reset
Nonmaskable Interrupt (This pin should be pulled high when not used)
Boot Mode Strap 2-0
O
O
External FET Drive
External FET Drive
P
P
P
G
I/O Power Supply
Internal Power Supply (regulated from 2.25 V to 3.6 V)
Real-Time Clock Power Supply
External Ground
See Output Drive Currents on Page 52 for more information about each driver types.
Rev. E |
Page 22 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
VDDINT
Internal Supply Voltage1
TJ
Internal Supply Voltage1
Internal Supply Voltage1
Internal Supply Voltage1
External Supply Voltage
External Supply Voltage
Real-Time Clock Power
Supply Voltage
High Level Input Voltage3, 4
High Level Input Voltage5
5.0 V Tolerant Pins, High
Level Input Voltage6
5.0 V Tolerant Pins, High
Level Input Voltage7
Low Level Input Voltage3, 8
5.0 V Tolerant Pins, Low
Level Input Voltage6
5.0 V Tolerant Pins, Low
Level Input Voltage6, 7
Junction Temperature
TJ
Junction Temperature
TJ
Junction Temperature
TJ
Junction Temperature
TJ
Junction Temperature
VDDINT
VDDINT
VDDINT
VDDEXT
VDDEXT
VDDRTC
VIH
VIHCLKIN
VIH5V
VIH5V
VIL
VIL5V
VIL5V
Conditions
Nonautomotive 300 MHz, 400 MHz and 500 MHz speed
grade models2
Nonautomotive 533 MHz speed grade models2
Nonautomotive 600 MHz speed grade models2
Automotive grade models2
Nonautomotive grade models2
Automotive grade models2
Min
0.8
Nominal
1.2
Max
1.32
Unit
V
0.8
0.8
0.95
2.25
2.7
2.25
1.25
1.3
1.2
2.5 or 3.3
3.0 or 3.3
1.375
1.43
1.32
3.6
3.6
3.6
V
V
V
V
V
V
@ VDDEXT = Maximum
@ VDDEXT = Maximum
2.0
2.2
0.7 × VDDEXT
3.6
3.6
5.5
V
V
V
@ VDDEXT = Maximum
2.0
5.5
V
@ VDDEXT = Minimum
–0.3
–0.3
+0.6
0.3 × VDDEXT
V
V
@ VDDEXT = Minimum
–0.3
+0.8
V
208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @
TAMBIENT = –40°C to +105°C
208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @
TAMBIENT = –40°C to +85°C
208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @
TAMBIENT = 0°C to +70°C
182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @
TAMBIENT = –40°C to +85°C
182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @
TAMBIENT = 0°C to +70°C
–40
+120
°C
–40
+105
°C
0
+95
°C
–40
+105
°C
0
+100
°C
1
The regulator can generate VDDINT at levels of 0.85V to 1.2 V with –5% to +10% tolerance, 1.25 V with –4% to +10% tolerance, and 1.3 V with –0% to +10% tolerance. The
required VDDINT is a function of speed grade and operating frequency. See Table 10, Table 11, and Table 12 for details.
2
See Ordering Guide on Page 67.
3
Bidirectional pins (DATA15–0, PF15–0, PG15–0, PH15–0, TFS0, TSCLK0, RSCLK0, RFS0, MDIO) and input pins (BR, ARDY, DR0PRI, DR0SEC, RTXI, TCK, TDI, TMS,
TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF534/ADSP-BF536/ADSP-BF537 are 3.3 V-tolerant (always accept up to 3.6 V maximum VIH). Voltage
compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
4
Parameter value applies to all input and bidirectional pins except CLKIN, SDA, and SCL.
5
Parameter value applies to CLKIN pin only.
6
Applies to pins PJ2/SCL and PJ3/SDA which are 5.0 V tolerant (always accept up to 5.5 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply
voltage.
7
Applies to pin PJ4/DR0SEC/CANRX/TACI0 which is 5.0 V tolerant (always accepts up to 5.5 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT
supply voltage.
8
Parameter value applies to all input and bidirectional pins except SDA and SCL.
Rev. E |
Page 23 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 10 through Table 12 describe the Voltage/Frequency
requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537
processor clocks. Take care in selecting MSEL, SSEL, and CSEL
ratios so as not to exceed the maximum core clock and system
clock. Table 13 describes phase-locked loop operating
conditions.
Table 10. Core Clock Requirements—500 MHz, 533 MHz and 600 MHz Speed Grades1
Parameter
fCCLK
Core Clock Frequency (VDDINT =1.30 V Minimum)2
fCCLK
Core Clock Frequency (VDDINT = 1.20 V Minimum)3
fCCLK
Core Clock Frequency (VDDINT =1.14 V Minimum)
Core Clock Frequency (VDDINT =1.045 V Minimum)
fCCLK
fCCLK
Core Clock Frequency (VDDINT = 0.95 V Minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.85 V Minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.8 V Minimum)
Internal Regulator Setting
1.30 V
1.25 V
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Max
600
533
500
444
400
333
250
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1
See Ordering Guide on Page 67.
Applies to 600 MHz models only. See Ordering Guide on Page 67.
3
Applies to 533 and 600 MHz models only. See Ordering Guide on Page 67.
2
Table 11. Core Clock Requirements—400 MHz Speed Grade1
Parameter
fCCLK Core Clock Frequency (VDDINT =1.14 V Minimum)
fCCLK Core Clock Frequency (VDDINT =1.045 V Minimum)
fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum)
fCCLK Core Clock Frequency (VDDINT = 0.85 V Minimum)
fCCLK Core Clock Frequency (VDDINT = 0.8 V Minimum)
1
2
120°C ≥ TJ > 105°C
Internal Regulator Setting Max
1.20 V
400
1.10 V
333
1.00 V
295
0.90 V
0.85 V
All2 Other TJ
Max
400
363
333
280
250
Unit
MHz
MHz
MHz
MHz
MHz
See Ordering Guide on Page 67.
See Operating Conditions on Page 23.
Table 12. Core Clock Requirements—300 MHz Speed Grade1
Parameter
fCCLK
Core Clock Frequency (VDDINT =1.14 V Minimum)
fCCLK
Core Clock Frequency (VDDINT =1.045 V Minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.95 V Minimum)
Core Clock Frequency (VDDINT = 0.85 V Minimum)
fCCLK
fCCLK
Core Clock Frequency (VDDINT = 0.8 V Minimum)
1
Internal Regulator Setting
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Max
300
255
210
180
160
Unit
MHz
MHz
MHz
MHz
MHz
See Ordering Guide on Page 67.
Table 13. Phase-Locked Loop Operating Conditions
Parameter
fVCO
1
Min
50
Voltage Controlled Oscillator (VCO) Frequency
Max
Speed Grade1
Unit
MHz
See Ordering Guide on Page 67.
Table 14. System Clock Requirements
Parameter
fSCLK
fSCLK
1
2
Condition
VDDEXT = 3.3 V or 2.5 V, VDDINT ≥ 1.14 V1
VDDEXT = 3.3 V or 2.5 V, VDDINT < 1.14 V1
Max
1332
100
fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 26 on Page 34.
Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 26 on Page 34.
Rev. E |
Page 24 of 68 |
March 2008
Unit
MHz
MHz
ADSP-BF534/ADSP-BF536/ADSP-BF537
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
3
VOH
High Level
@ VDDEXT = 3.3 V ± 10%,
Output Voltage IOH = –0.5 mA
@ VDDEXT = 2.5 V ± 10%,
IOH = –0.5 mA
@ VDDEXT = 3.3 V ± 10%,
VOH4
IOH = –8 mA
@ VDDEXT = 2.5 V ± 10%,
IOH = –6 mA
VOH5
IOH = –2 mA
IOH
IOH6
VOL3
VOL4
VOL5
IOL6
IIH
IOL6
IIH5V
IIL
IIHP
IOZH
IOZH5V
IOZL
CIN
Min
VDDEXT – 0.5
VDDEXT – 0.5
Low Power1
Typ
Max
Min
VDDEXT – 0.5
VDDEXT – 0.5
High Speed2
Typ
Max
Unit
V
V
VDDEXT – 0.5
VDDEXT – 0.5
VDDEXT – 0.5
VDDEXT – 0.5
V
V
VDDEXT – 0.5
VDDEXT – 0.5
V
High Level
VOH = VDDEXT – 0.5 V Min
Output Current
VOH = VDDEXT – 0.5 V Min
Low Level
@ VDDEXT = 3.3 V ± 10%,
Output Voltage IOL = 2.0 mA
@ VDDEXT = 2.5 V ± 10%,
IOL = 2.0 mA
@ VDDEXT = 3.3 V ± 10%,
IOL = 8 mA
@ VDDEXT = 2.5 V ± 10%,
IOL = 6 mA
IOL = 2 mA
VOL = 0.5 V Max
High Level Input @ VDDEXT =3.6 V, VIN = 3.6 V
Current7
Low Level
VOL = 0.5 V Max
Output Current
High Level Input @ VDDEXT =3.6 V, VIN = 5.5 V
Current8
Low Level Input @ VDDEXT =3.6 V, VIN = 0 V
Current2
High Level Input @ VDDEXT = 3.6 V, VIN = 3.6 V
Current JTAG9
Three-State
@ VDDEXT = 3.6 V, VIN = 3.6 V
Leakage
Current10
Three-State
@ VDDEXT =3.6 V, VIN = 5.5 V
Leakage
Current11
Three-State
@ VDDEXT = 3.6 V, VIN = 0 V
Leakage
Current5
Input
fIN = 1 MHz, TAMBIENT = 25°C,
Capacitance12, 13 VIN = 2.5 V
Rev. E |
Page 25 of 68 |
–64
–64
mA
–144
–144
mA
0.4
0.4
V
0.5
0.5
0.5
0.5
V
V
0.5
64
10
0.5
64
10
V
mA
μA
144
144
mA
10
10
μA
10
10
μA
50
50
μA
10
10
μA
10
10
μA
10
10
μA
8
8
pF
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Parameter
IDDDEEPSLEEP14 VDDINT Current in
Deep Sleep
Mode
IDDSLEEP
VDDINT Current in
Sleep Mode
IDD-IDLE
VDDINT Current in
Idle
IDD-TYP
VDDINT Current
IDD-TYP
IDD-TYP
IDD-TYP
IDDHIBERNATE14
IDDRTC
IDDSLEEP14, 15
IDDDEEPSLEEP14
IDDINT15, 16
Test Conditions
Min
VDDINT = 1.0 V, fCCLK = 0 MHz,
TJ = 25°C, ASF = 0.00
VDDINT = 1.0 V, fCCLK = 25 MHz,
TJ = 25°C
VDDINT = 1.0 V, fCCLK = 50 MHz,
TJ = 25°C, ASF = 0.43
VDDINT = 1.14 V, fCCLK = 300
MHz, TJ = 25°C, ASF = 1.00
VDDINT Current
VDDINT = 1.14 V, fCCLK = 400
MHz, TJ = 25°C, ASF = 1.00
VDDINT Current
VDDINT = 1.14 V, fCCLK = 533
MHz, TJ = 25°C, ASF = 1.00
VDDINT Current
VDDINT = 1.14 V, fCCLK = 600
MHz, TJ = 25°C, ASF = 1.00
VDDEXT Current in VDDEXT = 3.30 V, TJ = 25°C
Hibernate State with voltage regulator off
(VDDINT = 0 V)
VDDRTC Current
VDDRTC = 3.3 V, TJ= 25°C
VDDINT Current in fSCLK = 0 MHz
Sleep Mode
VDDINT Current in fCCLK = 0 MHz
Deep Sleep
Mode
VDDINT Current
fCCLK > 0 MHz
Low Power1
Typ
Max
6
High Speed2
Typ
Max
16
Unit
mA
9.5
19.5
mA
14
24
mA
100
113
mA
125
138
mA
185
mA
227
mA
25
μA
20
Table 15 + (0.14 ×
VDDINT × fSCLK)
Table 15
μA
Table 16 + (0.14 × mA
VDDINT × fSCLK)
Table 16
mA
Table 15 +
(Table 18 × ASF)
Table 16 +
mA
(Table 18 × ASF)
25
20
1
Min
Applies to all 300 MHz and 400 MHz speed grade models. See Ordering Guide on Page 67.
Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 67.
3
Applies to all output and bidirectional pins except port F pins, port G pins, and port H pins.
4
Applies to port F pins PF7–0.
5
Applies to port F pins PF15–8, all port G pins, and all port H pins.
6
Maximum total current for all port F, port G, and port H pins.
7
Applies to all input pins except PJ4.
8
Applies to input pin PJ4 only.
9
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
10
Applies to three-statable pins.
11
Applies to bidirectional pins PJ2 and PJ3.
12
Applies to all signal pins.
13
Guaranteed, but not tested.
14
See the ADSP-BF537 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
15
Guaranteed maximum specifications.
16
See Table 17 for the list of IDDINT power vectors covered.
2
Rev. E |
Page 26 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
System designers should refer to Estimating Power for the
ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297), which
provides detailed information for optimizing designs for lowest
power. All topics discussed in this section are described in detail
in EE-297. Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 25 shows the
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation as a function of voltage (VDDINT) and
temperature (see Table 15 or Table 16), and IDDINT specifies the
total power specification for the listed test conditions, including
the dynamic component as a function of voltage (VDDINT) and frequency (Table 18).
The dynamic component is also subject to an Activity Scaling
Factor (ASF) which represents application code running on the
processor (Table 17).
Table 15. Static Current–Low Power Process (mA)1
TJ (°C) 0.80 V
-40
2.60
0
6.60
25
12.20
40
17.20
55
25.70
70
37.60
85
53.70
100
75.10
105
84.50
2
115
103.80
115.50
1202
1
2
0.85 V
3.20
7.80
13.50
19.00
27.80
41.30
58.30
82.30
91.20
111.80
123.60
0.90 V
3.70
8.40
14.80
20.60
30.90
44.80
63.70
88.50
98.20
120.30
132.20
0.95 V
4.50
9.90
16.40
22.90
33.70
48.90
69.00
95.80
106.00
127.60
141.90
1.00 V
5.50
10.90
18.20
25.90
37.30
53.90
75.90
104.00
114.20
138.00
152.30
1.05 V
6.60
12.30
19.90
28.20
41.40
58.60
82.90
112.50
123.00
148.50
163.70
Voltage (VDDINT)
1.10 V 1.15 V
7.90
9.30
13.80
15.50
22.70
25.60
31.60
34.90
44.80
50.00
63.90
69.70
90.50
98.40
121.80 130.60
132.40 143.30
159.60 171.40
175.60 189.30
1.20 V
10.50
17.50
28.40
38.90
54.80
76.90
106.40
141.30
155.00
184.60
202.80
1.25 V
12.50
19.60
31.80
42.90
59.40
84.00
115.30
153.20
167.40
198.80
217.70
1.30 V
13.90
21.70
35.70
47.60
66.10
92.20
124.60
164.80
179.80
213.40
232.30
1.32 V
14.80
23.11
37.21
49.50
68.40
94.98
128.12
169.73
185.43
219.66
238.65
1.35 V
16.10
25.40
39.60
52.50
72.00
99.30
133.60
177.40
194.20
229.40
248.50
1.40 V
18.20
28.40
43.60
58.20
79.90
108.40
144.70
191.90
209.20
244.90
266.20
Values are guaranteed maximum IDDDEEPSLEEP specifications for 300 MHz and 400 MHz speed-grade devices.
Applies to automotive grade models only.
Table 16. Static Current–High Speed Process (mA)1
TJ (°C) 0.80 V
-40
3.9
0
17.0
25
35.0
40
53.0
55
76.7
70
110.1
85
150.1
100
202.3
105
223.8
1
0.85 V
4.7
19.2
39.2
59.2
84.6
120.0
164.5
219.2
241.4
0.90 V
6.8
21.9
44.3
65.3
93.6
130.9
178.7
236.5
260.4
0.95 V
8.2
25.0
50.8
71.9
103.1
142.2
193.2
255.8
282.0
1.00 V
9.9
28.2
56.1
79.1
113.7
156.5
210.4
277.8
303.4
1.05 V
12.0
32.1
63.3
88.0
123.9
171.3
228.9
299.8
328.7
Voltage (VDDINT)
1.10 V 1.15 V
14.6
17.3
36.9
41.8
69.1
76.4
96.6
108.0
136.3
148.3
185.2
201.7
247.7
268.8
323.8
351.2
354.5
381.7
1.20 V
20.3
47.7
84.7
120.0
162.8
220.6
291.4
378.8
410.8
1.25 V
24.1
53.8
93.5
130.7
178.4
239.7
314.1
407.5
443.6
Values are guaranteed maximum IDDDEEPSLEEP specifications for 500 MHz, 533 MHz, and 600 MHz speed-grade devices.
Rev. E |
Page 27 of 68 |
March 2008
1.30 V
27.1
61.0
104.5
142.6
194.4
259.8
341.1
440.4
477.8
1.32 V
28.57
63.82
109.14
148.50
201.45
268.80
351.19
453.39
492.19
1.35 V
30.9
68.3
116.5
157.8
212.5
282.9
366.9
473.6
514.6
1.40 V
35.5
75.8
128.9
173.7
232.5
306.7
398.0
511.3
553.3
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 17. Activity Scaling Factors
IDDINT Power Vector1
IDD-PEAK
IDD-HIGH
IDD-TYP
IDD-APP
IDD-NOP
IDD-IDLE
1
2
Activity Scaling Factor (ASF)2
1.33
1.29
1.00
0.88
0.72
0.43
See EE-297 for power vector definitions.
All ASF values determined using a 10:1 CCLK:SCLK ratio.
Table 18. Dynamic Current (mA, with ASF = 1.0)1
Frequency
50 MHz
100 MHz
200 MHz
300 MHz
400 MHz
500 MHz
533 MHz
600 MHz
1
0.80 V
11.00
27.90
36.90
N/A
N/A
N/A
N/A
N/A
0.85 V
13.70
22.70
42.60
61.50
N/A
N/A
N/A
N/A
0.90 V
19.13
30.80
55.00
79.20
104.30
N/A
N/A
N/A
0.95 V
18.20
28.40
49.20
70.40
92.40
N/A
N/A
N/A
1.00 V
18.67
29.30
51.50
74.60
97.20
N/A
N/A
N/A
1.05 V
19.13
30.80
55.00
79.20
104.30
N/A
N/A
N/A
Voltage (VDDINT)
1.10 V 1.15 V
19.60 21.20
32.90 35.30
58.30 62.90
84.40 90.70
109.80 116.50
134.30 142.30
N/A
N/A
N/A
N/A
1.20 V
24.10
37.80
67.00
94.30
121.90
149.30
158.60
N/A
1.25 V
25.50
40.60
69.70
99.10
128.00
157.50
167.03
N/A
1.30 V
28.50
43.50
73.00
103.90
134.60
164.70
174.37
193.70
1.32 V
28.64
43.74
74.08
105.54
136.68
166.74
176.66
196.50
1.35 V
28.85
44.10
75.70
108.00
139.80
169.80
180.10
200.70
1.40 V
29.20
45.80
80.70
113.40
145.10
176.90
187.93
210.00
The values are not guaranteed as stand-alone maximum specifications, they must be combined with static current per the equations of Electrical Characteristics on Page 25.
Table 20. Maximum Duty Cycle for Input1 Transient Voltage
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 19 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
1
Table 19. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage (VDDINT)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage1
Input Voltage1, 2
Output Voltage Swing
Load Capacitance3
Storage Temperature Range
Junction Temperature Underbias
VIN Min (V)
–0.50
–0.70
–0.80
–0.90
–1.00
2
1
Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT ± 0.2 V.
2
Applies to 5 V tolerant pins SCL, SDA, and PJ4. For duty cycles, see Table 20.
3
For proper SDRAM controller operation, the maximum load capacitance is 50 pF
(at 3.3 V) or 30 pF (at 2.5 V) for ADDR19–1, DATA15–0, ABE1–0/SDQM1–0,
CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.
Page 28 of 68 |
Maximum Duty Cycle
100%
40%
25%
15%
10%
Applies to all signal pins with the exception of CLKIN, XTAL, and VROUT1–0.
Only one of the listed options can apply to a particular design.
Rating
–0.3 V to +1.43 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to +5.5 V
–0.5 V to VDDEXT +0.5 V
200 pF
–65°C to +150°C
+125°C
Rev. E |
VIN Max (V)2
+3.80
+4.00
+4.10
+4.20
+4.30
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
PACKAGE INFORMATION
The information presented in Figure 8 and Table 21 provide
details about the package branding for the Blackfin processors.
For a complete listing of product availability, see Ordering
Guide on Page 67.
a
ADSP-BF5xx
tppZccc
vvvvvv.x n.n
yyww country_of_origin
B
Figure 8. Product Information on Package
Table 21. Package Brand Information
Brand Key
t
pp
Z
ccc
vvvvvv.x
n.n
yyww
Field Description
Temperature Range
Package Type
Lead Free Option (optional)
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
Rev. E |
Page 29 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
TIMING SPECIFICATIONS
Table 22. Clock Input and Reset Timing
Parameter
Timing Requirements
tCKIN
CLKIN Period1, 2, 3, 4
tCKINL
CLKIN Low Pulse
tCKINH
CLKIN High Pulse
tBUFDLAY
CLKIN to CLKBUF Delay
RESET Asserted Pulse Width Low5
tWRST
Min
Max
Unit
20.0
8.0
8.0
100.0
ns
ns
ns
ns
ns
10
11 tCKIN
1
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 10 through Table 14. Since
by default the PLL is multiplying the CLKIN frequency by 10, 300 MHz and 400 MHz speed grade parts can not use the full CLKIN period range.
2
Applies to PLL bypass mode and PLL non bypass mode.
3
CLKIN frequency must not change on the fly.
4
If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH
tBUFDLAY
tBUFDLAY
CLKBUF
tWRST
RESET
Figure 9. Clock and Reset Timing
Rev. E |
Page 30 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Asynchronous Memory Read Cycle Timing
Table 23. Asynchronous Memory Read Cycle Timing
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
tHO
1
Min
Max
Unit
2.1
0.8
4.0
0.0
ns
ns
ns
ns
6.0
ns
ns
0.8
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
HOLD
1 CYCLE
ACCESS EXTENDED
3 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tSARDY
tHARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 10. Asynchronous Memory Read Cycle Timing
Rev. E |
Page 31 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Asynchronous Memory Write Cycle Timing
Table 24. Asynchronous Memory Write Cycle Timing
Parameter
Timing Requirements
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
tHO
1
Min
4.0
0.0
1.0
6.0
0.8
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
1 CYCLE
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
t HARDY
t SARDY
ARDY
tSARDY
t ENDAT
DATA15–0
t DDAT
WRITE DATA
Figure 11. Asynchronous Memory Write Cycle Timing
Rev. E |
Page 32 of 68 |
March 2008
Unit
ns
ns
6.0
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
Max
ns
ns
ns
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
External Port Bus Request and Grant Cycle Timing
Table 25 and Figure 12 describe external port bus request and
bus grant operations.
Table 25. External Port Bus Request and Grant Cycle Timing
Parameter1, 2
Timing Requirements
tBS
BR Asserted to CLKOUT Low Setup
tBH
CLKOUT Low to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
tSE
tDBG
CLKOUT High to BG Asserted Setup
tEBG
CLKOUT High to BG Deasserted Hold Time
tDBH
CLKOUT High to BGH Asserted Setup
tEBH
CLKOUT High to BGH Deasserted Hold Time
1
2
Min
Max
4.6
0.0
ns
ns
4.5
4.5
3.6
3.6
3.6
3.6
These are preliminary timing parameters that are based on worst-case operating conditions.
The pad loads for these timing parameters are 20 pF.
CLKOUT
tBS
tBH
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 12. External Port Bus Request and Grant Cycle Timing
Rev. E |
Page 33 of 68 |
March 2008
Unit
tEBH
ns
ns
ns
ns
ns
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
SDRAM Interface Timing
Table 26. SDRAM Interface Timing
Parameter
Timing Requirements
tSSDAT
DATA15–0 Setup Before CLKOUT
tHSDAT
DATA15–0 Hold After CLKOUT
Switching Characteristics
tDCAD
COMMAND, ADDR19–1, DATA15–0 Delay After CLKOUT1
tHCAD
COMMAND, ADDR19–1, DATA15–0 Hold After CLKOUT1
tDSDAT
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
tENSDAT
tSCLK
CLKOUT Period TJ ≤ +105°C2
tSCLK
CLKOUT Period TJ > +105°C2
tSCLKH
CLKOUT Width High
tSCLKL
CLKOUT Width Low
1
2
Min
1.5
0.8
1.0
6.0
1.0
7.5
10
2.5
2.5
tSCLK
tSCLKH
CLKOUT
tSSDAT
tSCLKL
tHSDAT
DATA15-0 (IN)
tDCAD
tENSDAT
tDSDAT
tHCAD
DATA15-0 (OUT)
tDCAD
COMMAND ADDR19-1
(OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 13. SDRAM Interface Timing
Page 34 of 68 |
March 2008
Unit
ns
ns
4.0
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
These limits are specific to the SDRAM interface only. In addition, CLKOUT must always comply with the limits in Table 14 on Page 24.
Rev. E |
Max
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
External DMA Request Timing
Table 27 and Figure 14 describe the external DMA request
operations.
Table 27. External DMA Request Timing
Parameter
Timing Requirements
tDR
DMARx Asserted to CLKOUT High Setup
tDH
CLKOUT High to DMARx Deasserted Hold Time
tDMARACT
DMARx Active Pulse Width
tDMARINACT
DMARx Inactive Pulse Width
Min
6.0
0.0
1.0 × tSCLK
1.75 × tSCLK
CLKOUT
tDR
DMAR0/1
(ACTIVE LOW)
DMAR0/1
(ACTIVE HIGH)
tDH
tDMARACT
tDMARINACT
tDMARACT
tDMARINACT
Figure 14. External DMA Request Timing
Rev. E |
Page 35 of 68 |
March 2008
Max
Unit
ns
ns
ns
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
Parallel Peripheral Interface Timing
Table 28 and Figure 15 on Page 36, Figure 19 on Page 40, and
Figure 20 on Page 41 describe parallel peripheral interface
operations.
Table 28. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
PPI_CLK Width1
tPCLKW
tPCLK
PPI_CLK Period1
Timing Requirements—GP Input and Frame Capture Modes
tSFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
External Frame Sync Hold After PPI_CLK
tSDRPE
Receive Data Setup Before PPI_CLK
tHDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
tDDTPE
Transmit Data Delay After PPI_CLK
tHDTPE
Transmit Data Hold After PPI_CLK
1
Min
PPI_CLK
POLC = 1
tDFSPE
tHOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tHDRPE
PPI_DATA
Figure 15. PPI GP Rx Mode with Internal Frame Sync Timing
Page 36 of 68 |
ns
1.0
3.5
1.5
ns
ns
ns
8.0
PPI_CLK
Rev. E |
6.7
1.8
POLC = 0
tSDRPE
ns
ns
8.0
DATA0
IS
SAMPLED
March 2008
Unit
6.0
15.0
1.7
PPI_CLK frequency cannot exceed fSCLK/2.
FRAME
SYNC IS
DRIVEN
OUT
Max
ns
ns
ns
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
DATA1 IS
SAMPLED
DATA0 IS
SAMPLED
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
SFSPE
t
HFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tSDRPE
t
HDRPE
PPI_DATA
Figure 16. PPI GP Rx Mode with External Frame Sync Timing
FRAME
SYNC IS
DRIVEN
OUT
DATA0 IS
DRIVEN
OUT
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
DFSPE
t
HOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
t
DDTPE
HDTPE
PPI_DATA
DATA0
Figure 17. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. E |
Page 37 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
HFSPE
t
SFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tDDTPE
t
HDTPE
PPI_DATA
Figure 18. PPI GP Tx Mode with External Frame Sync Timing
Rev. E |
Page 38 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Ports
Table 29 through Table 32 on Page 40 and Figure 19 on Page 40
through Figure 20 on Page 41 describe serial port operations.
Table 29. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRE
Receive Data Setup Before RSCLKx1
tHDRE
Receive Data Hold After RSCLKx1
TSCLKx/RSCLKx Width
tSCLKEW
tSCLKE
TSCLKx/RSCLKx Period
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)2
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)2
tDDTE
Transmit Data Delay After TSCLKx2
Transmit Data Hold After TSCLKx2
tHDTE
1
2
Min
Max
3.0
3.0
3.0
3.0
4.5
15.0
Unit
ns
ns
ns
ns
ns
ns
10.0
0
10.0
0
ns
ns
ns
ns
Referenced to sample edge.
Referenced to drive edge.
Table 30. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRI
Receive Data Setup Before RSCLKx1
tHDRI
Receive Data Hold After RSCLKx1
TSCLKx/RSCLKx Width
tSCLKEW
tSCLKE
TSCLKx/RSCLKx Period
Switching Characteristics
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
tDDTI
Transmit Data Delay After TSCLKx2
Transmit Data Hold After TSCLKx2
tHDTI
tSCLKIW
TSCLKx/RSCLKx Width
1
2
Min
Max
8.0
–1.5
8.0
–1.5
4.5
15.0
Unit
ns
ns
ns
ns
ns
ns
3.0
3.0
ns
ns
ns
ns
ns
Max
Unit
−1.0
−1.0
4.5
Referenced to sample edge.
Referenced to drive edge.
Table 31. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLKx1
tDDTTE
Data Disable Delay from External TSCLKx1
tDTENI
Data Enable Delay from Internal TSCLKx1
Data Disable Delay from Internal TSCLKx1
tDDTTI
1
Min
0
10.0
–2.0
3.0
Referenced to drive edge.
Rev. E |
Page 39 of 68 |
March 2008
ns
ns
ns
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 32. External Late Frame Sync
Parameter
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFSx or External RFSx with MCE = 1, MFD = 01, 2
Data Enable from Late FS or MCE = 1, MFD = 01, 2
tDTENLFS
1
2
Min
Max
Unit
10.0
ns
ns
0
MCE = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFS.
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLKx
RSCLKx
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
RFSx
tSFSE
tHFSE
tSDRE
tHDRE
RFSx
tSDRI
tHDRI
DRx
DRx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DRIVE
EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
SAMPLE
EDGE
tSCLKEW
TSCLKx
TSCLKx
tDFSI
tHOFSI
tDFSE
tSFSI
tHFSI
TFSx
tHOFSE
tSFSE
TFSx
tDDTI
tDDTE
tHDTI
tHDTE
DTx
DTx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 19. Serial Ports
Rev. E |
Page 40 of 68 |
March 2008
tHFSE
ADSP-BF534/ADSP-BF536/ADSP-BF537
EXTERNAL RFSx WITH MCE = 1, MFD = 0
DRIVE
RSCLKx
SAMPLE
DRIVE
tSFSE/I
tHOFSE/I
RFSx
tDDTTE/I
tDTENE/I
tDTENLFS
1ST BIT
DTx
2ND BIT
tDDTLFSE
LATE EXTERNAL TFSx
DRIVE
TSCLKx
SAMPLE
DRIVE
tHOFSE/I
tSFSE/I
TFSx
tDDTTE/I
tDTENE/I
tDTENLFS
1ST BIT
DTx
2ND BIT
tDDTLFSE
Figure 20. External Late Frame Sync
Rev. E |
Page 41 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Peripheral Interface Port—Master Timing
Table 33 and Figure 21 describe SPI port master operations.
Table 33. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
tHSPIDM
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tSDSCIM
SPISELx Low to First SCK Edge
tSPICHM
Serial Clock High Period
tSPICLM
Serial Clock Low Period
tSPICLK
Serial Clock Period
tHDSM
Last SCK Edge to SPISELx High
Sequential Transfer Delay
tSPITDM
tDDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
Min
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
MOSI
(OUTPUT)
tHDSPIDM
MSB
CPHA = 1
tSSPIDM
MISO
(INPUT)
LSB
tHSPIDM
tSSPIDM
MSB VALID
LSB VALID
tDDSPIDM
MOSI
(OUTPUT)
CPHA = 0
MISO
(INPUT)
tHDSPIDM
MSB
tSSPIDM
tHSPIDM
LSB
tHSPIDM
MSB VALID
LSB VALID
Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. E |
Page 42 of 68 |
March 2008
Unit
7.5
–1.5
ns
ns
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
0
6
–1.0
+4.0
ns
ns
ns
ns
ns
ns
ns
ns
SPISELx
(OUTPUT)
tSDSCIM
Max
tSPITDM
ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Peripheral Interface Port—Slave Timing
Table 34 and Figure 22 describe SPI port slave operations.
Table 34. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial Clock High Period
tSPICLS
Serial Clock Low Period
Serial Clock Period
tSPICLK
tHDS
Last SCK Edge to SPISS Not Asserted
tSPITDS
Sequential Transfer Delay
tSDSCI
SPISS Assertion to First SCK Edge
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
tHSPID
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tDSOE
SPISS Assertion to Data Out Active
tDSDHI
SPISS Deassertion to Data High Impedance
tDDSPID
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
Min
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
1.6
0
0
0
0
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MISO
(OUTPUT)
tSSPID
MOSI
(INPUT)
LSB
tHSPID
tSSPID
tHSPID
LSB VALID
tDDSPID
tDSDHI
MSB
LSB
tHSPID
CPHA = 0
MOSI
(INPUT)
tDSDHI
MSB VALID
tDSOE
MISO
(OUTPUT)
tDDSPID
MSB
CPHA = 1
tSSPID
MSB VALID
LSB VALID
Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. E |
Max
Page 43 of 68 |
March 2008
Unit
ns
ns
ns
ns
ns
ns
ns
ns
8
8
10
10
ns
ns
ns
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
Figure 23 describes the UART ports receive and transmit operations. The maximum baud rate is SCLK/16. As shown in
Figure 23 there is some latency between the generation of
internal UART interrupts and the external data operations.
These latencies are negligible at the data transmission rates for
the UART.
CLKOUT
(SAMPLE CLOCK)
RX
DATA(5–8)
STOP
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
TX
DATA(5–8)
STOP (1–2)
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 23. UART Ports—Receive and Transmit Timing
Rev. E |
Page 44 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
General-Purpose Port Timing
Table 35 and Figure 24 describe general-purpose
port operations.
Table 35. General-Purpose Port Timing
Parameter
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
Switching Characteristic
tGPOD
General-Purpose Port Pin Output Delay from CLKOUT Low
Min
tSCLK + 1
0
CLKOUT
tGPOD
GPP OUTPUT
tWFI
GPP INPUT
Figure 24. General-Purpose Port Timing
Rev. E |
Page 45 of 68 |
Max
March 2008
Unit
ns
6
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
Timer Cycle Timing
Table 36 and Figure 25 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz.
Table 36. Timer Cycle Timing
Parameter
Timing Characteristics
tWL
Timer Pulse Width Input Low (Measured In SCLK Cycles)1
tWH
Timer Pulse Width Input High (Measured In SCLK Cycles)1
Timer Input Setup Time Before CLKOUT Low2
tTIS
tTIH
Timer Input Hold Time After CLKOUT Low2
Switching Characteristics
tHTO
Timer Pulse Width Output (Measured In SCLK Cycles)
tTOD
Timer Output Update Delay After CLKOUT High
1
2
Min
Max
Unit
1 × tSCLK
1 × tSCLK
5
–2
ns
ns
ns
ns
1 × tSCLK
(232–1) × tSCLK ns
6
ns
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKO UT
t TO D
TIME R O UTPUT
tH T O
t T IS
t TIH
TIM E R INPUT
tW H , tW L
Figure 25. Timer Cycle Timing
Rev. E |
Page 46 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
Timer Clock Timing
Table 37 and Figure 26 describe timer clock timing.
Table 37. Timer Clock Timing
Parameter
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
Min
PPI CLOCK
tTODP
TIMER OUTPUT
Figure 26. Timer Clock Timing
Rev. E |
Page 47 of 68 |
March 2008
Max
Unit
12
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
JTAG Test and Emulation Port Timing
Table 38 and Figure 27 describe JTAG port operations.
Table 38. JTAG Port Timing
Parameter
Timing Parameters
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
tHTAP
tSSYS
System Inputs Setup Before TCK High1
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulse Width2 (Measured in TCK Cycles)
Switching Characteristics
tDTDO
TDO Delay From TCK Low
System Outputs Delay After TCK Low3
tDSYS
Min
Max
20
4
4
4
5
4
0
1
Unit
ns
ns
ns
ns
ns
TCK
10
12
ns
ns
System Inputs = DATA15–0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH15–0, MDIO, TCK, TD1, TMS, TRST, RESET,
NMI, BMODE2–0.
2
50 MHz maximum
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,
DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTXO, TDO, EMU, XTAL, VROUT.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 27. JTAG Port Timing
Rev. E |
Page 48 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
10/100 Ethernet MAC Controller Timing
Table 39 through Table 44 and Figure 28 through Figure 33
describe the 10/100 Ethernet MAC controller operations. This
feature is only available on the ADSP-BF536 and ADSP-BF537
processors. For more information, see Table 1 on Page 3.
Table 39. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
1
Parameter1
tERXCLKF
ERxCLK Frequency (fSCLK = SCLK Frequency)
Min
None
tERXCLKW
tERXCLKIS
tERXCLKIH
ERxCLK Width (tERxCLK = ERxCLK Period)
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
tERxCLK × 35%
7.5
7.5
Max
25 MHz + 1%
fSCLK + 1%
tERxCLK × 65%
Unit
ns
ns
ns
ns
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
Table 40. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
1
Parameter1
tETF
ETxCLK Frequency (fSCLK = SCLK Frequency)
tETXCLKW
tETXCLKOV
tETXCLKOH
ETxCLK Width (tETxCLK = ETxCLK Period)
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold)
Min
None
tETxCLK × 35%
Max
25 MHz + 1%
fSCLK + 1%
tETxCLK × 65%
20
Unit
ns
Max
50 MHz + 1%
2 × fSCLK + 1%
tEREFCLK × 65%
Unit
ns
0
ns
ns
ns
MII outputs synchronous to ETxCLK are ETxD3–0.
Table 41. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
1
Parameter1
tEREFCLKF
REF_CLK Frequency (fSCLK = SCLK Frequency)
Min
None
tEREFCLKW
tEREFCLKIS
tEREFCLKIH
EREF_CLK Width (tEREFCLK = EREFCLK Period)
Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup)
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold)
tEREFCLK × 35%
4
2
ns
ns
ns
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
Table 42. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter1
tEREFCLKOV
tEREFCLKOH
1
Min
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)
RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
Rev. E |
Page 49 of 68 |
March 2008
2
Max
7.5
Unit
ns
ns
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 43. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter1, 2
tECOLH
COL Pulse Width High
tECOLL
COL Pulse Width Low
tECRSH
tECRSL
CRS Pulse Width High
CRS Pulse Width Low
Min
tETxCLK × 1.5
tERxCLK × 1.5
tETxCLK × 1.5
tERxCLK × 1.5
tETxCLK × 1.5
tETxCLK × 1.5
Max
Unit
ns
ns
ns
ns
ns
ns
1
MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2
The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Table 44. 10/100 Ethernet MAC Controller Timing: MII Station Management
Parameter1
tMDIOS
tMDCIH
tMDCOV
tMDCOH
1
Min
10
10
25
–1
MDIO Input Valid to MDC Rising Edge (Setup)
MDC Rising Edge to MDIO Input Invalid (Hold)
MDC Falling Edge to MDIO Output Valid
MDC Falling Edge to MDIO Output Invalid (Hold)
Max
Unit
ns
ns
ns
ns
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
tERXCLK
ERxCLK
tERXCLKW
ERxD3-0
ERxDV
ERxER
tERXCLKIS
tERXCLKIH
Figure 28. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
tETXCLK
MII TxCLK
tETXCLKW
tETXCLKOH
ETxD3-0
ETxEN
tETXCLKOV
Figure 29. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Rev. E |
Page 50 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
tREFCLK
RMII_REF_CLK
tREFCLKW
ERxD1-0
ERxDV
ERxER
tERXCLKIS
tERXCLKIH
Figure 30. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
tREFCLK
RMII REF_CLK
tEREFCLKOH
ETxD1-0
ETxEN
tEREFCLKOV
Figure 31. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
MII CRS, COL
tECRSH
tECOLH
tECRSL
tECOLL
Figure 32. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
MDC (OUTPUT)
tMDCOH
MDIO (OUTPUT)
tMDCOV
MDIO (INPUT)
tMDIOS
tMDCIH
Figure 33. 10/100 Ethernet MAC Controller Timing: MII Station Management
Rev. E |
Page 51 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
OUTPUT DRIVE CURRENTS
120
V D DE XT = 2.25V @ 95°C
100
V D DE XT = 2.50V @ 25°C
SOURCE CURRENT (mA)
80
V D DE XT = 2.75V @ -40°C
60
150
VD D EX T = 2. 25V @ 95°C
VD DE XT = 2.75V @ -40°C
50
V OH
0
-50
V OL
-100
V OH
40
V DD E XT = 2.50V @ 25° C
100
SOURCE CURRENT (mA)
Figure 34 through Figure 45 show typical current-voltage characteristics for the output drivers of the processors. The curves
represent the current drive capability of the output drivers as a
function of output voltage. See Table 9 on Page 19 for information about which driver type corresponds to a particular pin.
20
-150
0
0
0.5
1. 0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
-20
-40
V OL
Figure 36. Drive Current B (Low VDDEXT)
-60
-80
200
-100
0
0.5
1.0
1.5
2.0
3. 0
2.5
SOURCE CURRENT (mA)
150
VD D EX T = 3.0V @ 95°C
VD D EX T = 3.3V @ 25°C
VD D EX T = 3.6V @ -40°C
SOURCE CURRENT (mA)
V DD E XT = 3.3V @ 25°C
VD D EX T = 3.6V @ - 40°C
100
Figure 34. Drive Current A (Low VDDEXT)
100
V DD E XT = 3.0V @ 95°C
150
SOURCE VOL TAGE (V)
VO H
50
0
-50
-100
VOL
50
-150
VO H
-200
0
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
-50
VOL
Figure 37. Drive Current B (High VDDEXT)
-100
-150
0
0.5
1.0
1.5
2.0
2.5
3. 0
3.5
4.0
SOURCE VOLTAGE (V)
Figure 35. Drive Current A (High VDDEXT)
Rev. E |
Page 52 of 68 |
March 2008
3. 0
3.5
4.0
ADSP-BF534/ADSP-BF536/ADSP-BF537
150
80
V D DE XT = 3.0V @ 95° C
V D DE XT = 3.3V @ 25° C
VD D EXT = 2.25V @ 95°C
VD D EXT = 2.50V @ 25°C
60
100
V DD E XT = 3.6V @ -40°C
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
VD D EX T = 2.75V @ -40°C
40
V OH
20
0
-20
VOL
50
VOH
0
-50
V OL
-100
-40
-60
-150
0
0.5
1. 0
1.5
2.0
2.5
0
3.0
0.5
1.0
1.5
Figure 38. Drive Current C (Low VDDEXT)
3. 0
3.5
4.0
50
60
VD D EX T = 3. 0V @ 95°C
40
VD D EX T = 2.25V @ 95° C
VD D EX T = 3. 3V @ 25°C
V DD E XT = 3.6V @ -40°C
30
VD D EX T = 2.50V @ 25° C
VD D EX T = 2.75V @ - 40°C
SOURCE CURRENT (mA)
80
SOURCE CURRENT (mA)
2.5
Figure 41. Drive Current D (High VDDEXT)
100
40
VOH
20
0
-20
-40
20
VOH
10
0
-10
-20
-30
VO L
V OL
-60
-40
-50
-80
0
0.5
1.0
1.5
2.0
2.5
3. 0
0
4.0
3.5
0.5
1.0
Figure 39. Drive Current C (High VDDEXT)
2.0
80
V D DE XT = 2.25V @ 95°C
V D DE XT = 2.50V @ 25°C
60
VD D EX T = 3. 0V @ 95°C
40
V DD E XT = 3.6V @ -40°C
VD D E XT = 2.75V @ -40°C
VD D EX T = 3. 3V @ 25°C
SOURCE CURRENT (mA)
60
3. 0
2.5
Figure 42. Drive Current E (Low VDDEXT)
100
80
1.5
SOURCE VOL TAGE (V)
SOURCE VOLTAGE (V)
SOURCE CURRENT (mA)
2.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
40
VOH
20
0
-20
-40
V OL
-60
20
VO H
0
-20
-40
VOL
-60
-80
0
0.5
1.0
1.5
2.0
2. 5
3.0
-80
0
SOURCE VOLTAGE (V)
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
Figure 40. Drive Current D (Low VDDEXT)
Figure 43. Drive Current E (High VDDEXT)
Rev. E |
Page 53 of 68 |
March 2008
3. 0
3.5
4.0
ADSP-BF534/ADSP-BF536/ADSP-BF537
tENA_MEASURED is the interval from when the reference signal
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time tTRIP is the interval from when the
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time tENA is calculated as shown in
the equation:
0
V DD E XT = 2.25V @ 95°C
V DD E XT = 2.50V @ 25°C
VD D EX T = 2.75V @ -40° C
SOURCE CURRENT (mA)
- 10
- 20
- 30
t ENA = t ENA_MEASURED – t TRIP
V OL
- 40
If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
- 50
Output Disable Time
- 60
0
0.5
1.0
1.5
2.0
2.5
3.0
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, CL, and the
load current, IL. This decay time can be approximated by
the equation:
SOURCE VOLTAGE (V)
Figure 44. Drive Current F (Low VDDEXT)
SOURCE CURRENT (mA)
0
-10
VD D EX T = 3.0V @ 95°C
VD D EX T = 3.3V @ 25°C
-20
V D D EXT = 3.6V @ -40°C
t DECAY = ( C L ΔV ) ⁄ I L
-30
The output disable time tDIS is the difference between
tDIS_MEASURED and tDECAY as shown in Figure 46. The time
tDIS_MEASURED is the interval from when the reference signal
switches to when the output voltage decays ΔV from the measured output-high or output-low voltage. The time tDECAY is
calculated with the test loads CL and IL, and with ΔV
equal to 0.5 V.
-40
VOL
-50
-60
-70
-80
0
0.5
1.0
1.5
2.0
2.5
3. 0
4.0
3.5
SOURCE VOLTAGE (V)
Figure 45. Drive Current F (High VDDEXT)
REFERENCE
SIGNAL
POWER DISSIPATION
tDIS_MEASURED
Many operating conditions can affect power dissipation. System
designers should refer to Estimating Power for
ADSP-BF531/BF532/BF533 Blackfin Processors (EE-229) on the
Analog Devices website (www.analog.com)—use site search on
“EE-229.” This document provides detailed information for
optimizing your design for lowest power.
tDIS
tENA_MEASURED
tENA
VOH
(MEASURED)
VOL
(MEASURED)
VOH(MEASURED)
VOH (MEASURED) ⴚ ⌬V
VTRIP (HIGH)
VOL (MEASURED) + ⌬V
VTRIP (LOW)
VOL (MEASURED)
tDECAY
See the ADSP-BF537 Blackfin Processor Hardware Reference
Manual for definitions of the various operating modes and for
instructions on how to minimize system power.
OUTPUT STOPS DRIVING
tTRIP
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
TEST CONDITIONS
Figure 46. Output Enable/Disable
All timing parameters appearing in this data sheet were
measured under the conditions described in this section.
Example System Hold Time Calculation
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (Figure 46). The time
Rev. E |
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. A
typical ΔV is 0.4 V. CL is the total bus capacitance (per data line),
Page 54 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
50⍀
TO
OUTPUT
PIN
VLOAD
30pF
Figure 47. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
12
RISE AND FALL TIME ns (10% to 90%)
and IL is the total leakage or three-state current (per data line).
The hold time is tDECAY plus the minimum disable time (for
example, tDSDAT for an SDRAM write cycle).
10
RISE TIME
8
FALL TIME
6
4
2
0
INPUT
OR
OUTPUT
VMEAS
0
50
VMEAS
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 50. Typical Output Delay or Hold for Driver A at VDDEXT Max
Figure 48. Voltage Reference Levels for AC Measurements (Except
Output Enable/Disable)
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 47). Figure 49 through Figure 58 on
Page 57 show how output rise time varies with capacitance. The
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
RISE AND FALL TIME ns (10% to 90%)
14
RISE AND FALL TIME ns (10% to 90%)
12
Capacitive Loading
10
RISE TIME
8
FALL TIME
6
4
2
12
0
RISE TIME
0
10
FALL TIME
8
4
2
0
50
100
150
LOAD CAPACITANCE (pF)
100
150
LOAD CAPACITANCE (pF)
200
Figure 51. Typical Output Delay or Hold for Driver B at VDDEXT Min
6
0
50
200
250
Figure 49. Typical Output Delay or Hold for Driver A at VDDEXT Min
Rev. E |
Page 55 of 68 |
March 2008
250
ADSP-BF534/ADSP-BF536/ADSP-BF537
20
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
10
9
8
RISE TIME
7
6
FALL TIME
5
4
3
2
1
0
16
RISE TIME
14
12
FALL TIME
10
8
6
4
2
0
50
100
150
LOAD CAPACITANCE (pF)
200
0
250
Figure 52. Typical Output Delay or Hold for Driver B at VDDEXT Max
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 54. Typical Output Delay or Hold for Driver C at VDDEXT Max
30
18
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
18
25
RISE TIME
20
15
FALL TIME
10
16
14
RISE TIME
12
10
FALL TIME
8
6
4
5
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 53. Typical Output Delay or Hold for Driver C at VDDEXT Min
Rev. E |
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
Figure 55. Typical Output Delay or Hold for Driver D at VDDEXT Min
Page 56 of 68 |
March 2008
250
ADSP-BF534/ADSP-BF536/ADSP-BF537
36
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
14
12
RISE TIME
10
FALL TIME
8
6
4
2
32
28
RISE TIME
24
20
16
FALL TIME
12
8
4
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 56. Typical Output Delay or Hold for Driver D at VDDEXT Max
Figure 58. Typical Output Delay or Hold for Driver E at VDDEXT Max
36
32
28
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
36
RISE TIME
24
20
FALL TIME
16
12
8
32
28
RISE TIME
24
20
16
FALL TIME
12
8
4
4
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
Figure 57. Typical Output Delay or Hold for Driver E at VDDEXT Min
Figure 59. Typical Output Delay or Hold for Driver F at VDDEXT Min
Rev. E |
Page 57 of 68 |
March 2008
250
ADSP-BF534/ADSP-BF536/ADSP-BF537
JESD51-9 (BGA). The junction-to-case measurement complies
with MIL-STD-883 (Method 1012.1). All measurements use a
2S2P JEDEC test board.
RISE AND FALL TIME ns (10% to 90%)
36
Industrial applications using the 208-ball BGA package require
thermal vias, to an embedded ground plane, in the PCB. Refer to
JEDEC standard JESD51-9 for printed circuit board thermal
ball land and thermal via design information.
32
28
RISE TIME
24
Table 45. Thermal Characteristics (182-Ball BGA)
20
16
Parameter
θJA
θJMA
θJMA
θJB
θJC
ΨJT
ΨJT
ΨJT
FALL TIME
12
8
4
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 60. Typical Output Delay or Hold for Driver F at VDDEXT Max
THERMAL CHARACTERISTICS
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
32.80
29.30
28.00
20.10
7.92
0.19
0.35
0.45
Unit
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
Table 46. Thermal Characteristics (208-Ball BGA Without
Thermal Vias in PCB)
To determine the junction temperature on the application
printed circuit board use:
Parameter
θJA
θJMA
θJMA
θJB
θJC
ΨJT
ΨJT
ΨJT
T J = T CASE + ( Ψ JT × P D )
where:
TJ = Junction temperature (ⴗC)
TCASE = Case temperature (ⴗC) measured by customer at top
center of package.
ΨJT = From Table 45
PD = Power dissipation (see Power Dissipation on Page 54 for
the method to calculate PD)
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
23.30
20.20
19.20
13.05
6.92
0.18
0.27
0.32
Unit
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
Table 47. Thermal Characteristics (208-Ball BGA with
Thermal Vias in PCB)
T J = T A + ( θ JA × P D )
where:
TA = Ambient temperature (ⴗC)
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
Parameter
θJA
θJMA
θJMA
θJB
θJC
ΨJT
ΨJT
ΨJT
Values of θJB are provided for package comparison and printed
circuit board design considerations.
In Table 45 through Table 47, airflow measurements comply
with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. Test
board and thermal via design comply with JEDEC standards
Rev. E |
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Page 58 of 68 |
March 2008
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
22.60
19.40
18.40
13.20
6.85
0.16
0.27
0.32
Unit
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ADSP-BF534/ADSP-BF536/ADSP-BF537
182-BALL CSP_BGA BALL ASSIGNMENT
Table 48 lists the CSP_BGA ball assignment by signal mnemonic. Table 49 on Page 60 lists the CSP_BGA ball assignment
by ball number.
Table 48. 182-Ball CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic)
Mnemonic
ABE0
ABE1
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BMODE2
BR
CLKBUF
CLKIN
Ball No.
H13
H12
J14
M13
M14
N14
N13
N12
M11
N11
P13
P12
P11
K14
L14
J13
K13
L13
K12
L12
M12
E14
F14
F13
G12
G13
E13
G14
H14
P10
N10
N4
P3
L5
D14
A7
A12
Mnemonic
CLKOUT
DATA0
DATA1
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
B14
M9
N9
N6
P6
M5
N5
P5
P4
P9
M8
N8
P8
M7
N7
P7
M6
M2
A10
A14
D4
E7
E9
F5
F6
F10
F11
G4
G5
G11
H11
J4
J5
J9
J10
K6
K11
Mnemonic
GND
GND
GND
GND
GND
GND
NMI
PF0
PF1
PF10
PF11
PF12
PF13
PF14
PF15
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PG0
PG1
PG10
PG11
PG12
PG13
PG14
PG15
PG2
PG3
PG4
PG5
PG6
PG7
Rev. E |
Ball No.
L6
L8
L10
M4
M10
P14
B10
M1
L1
J2
J3
H1
H2
H3
H4
L2
L3
L4
K1
K2
K3
K4
J1
G1
G2
D1
D2
D3
D5
D6
C1
G3
F1
F2
F3
E1
E2
Page 59 of 68 |
Mnemonic
PG8
PG9
PH0
PH1
PH10
PH11
PH12
PH13
PH14
PH15
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PJ0
PJ1
PJ10
PJ11
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
RESET
RTXO
RTXI
SA10
SCAS
SCKE
SMS
March 2008
Ball No.
E3
E4
C2
C3
B6
A2
A3
A4
A5
A6
C4
C5
C6
B1
B2
B3
B4
B5
C7
B7
D10
D11
B11
C11
D7
D8
C8
B8
D9
C9
C10
A8
A9
E12
C14
B13
C13
Mnemonic
SRAS
SWE
TCK
TDI
TDO
TMS
TRST
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Ball No.
D13
D12
P2
M3
N3
N2
N1
A1
C12
E6
E11
F4
F12
H5
H10
J11
J12
K7
K9
L7
L9
L11
P1
E5
E8
E10
G10
K5
K8
K10
B9
A13
B12
A11
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 49. 182-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
C8
C9
Mnemonic
VDDEXT
PH11
PH12
PH13
PH14
PH15
CLKBUF
RTXO
RTXI
GND
XTAL
CLKIN
VROUT0
GND
PH5
PH6
PH7
PH8
PH9
PH10
PJ1
PJ7
VDDRTC
NMI
PJ2
VROUT1
SCKE
CLKOUT
PG15
PH0
PH1
PH2
PH3
PH4
PJ0
PJ6
PJ9
Ball No.
C10
C11
C12
C13
C14
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
F1
F2
F3
F4
Mnemonic
RESET
PJ3
VDDEXT
SMS
SCAS
PG10
PG11
PG12
GND
PG13
PG14
PJ4
PJ5
PJ8
PJ10
PJ11
SWE
SRAS
BR
PG6
PG7
PG8
PG9
VDDINT
VDDEXT
GND
VDDINT
GND
VDDINT
VDDEXT
SA10
ARDY
AMS0
PG3
PG4
PG5
VDDEXT
Ball No.
F5
F6
F10
F11
F12
F13
F14
G1
G2
G3
G4
G5
G10
G11
G12
G13
G14
H1
H2
H3
H4
H5
H10
H11
H12
H13
H14
J1
J2
J3
J4
J5
J9
J10
J11
J12
J13
Rev. E |
Mnemonic
GND
GND
GND
GND
VDDEXT
AMS2
AMS1
PG0
PG1
PG2
GND
GND
VDDINT
GND
AMS3
AOE
ARE
PF12
PF13
PF14
PF15
VDDEXT
VDDEXT
GND
ABE1
ABE0
AWE
PF9
PF10
PF11
GND
GND
GND
GND
VDDEXT
VDDEXT
ADDR4
Page 60 of 68 |
Ball No.
J14
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
March 2008
Mnemonic
ADDR1
PF5
PF6
PF7
PF8
VDDINT
GND
VDDEXT
VDDINT
VDDEXT
VDDINT
GND
ADDR7
ADDR5
ADDR2
PF1
PF2
PF3
PF4
BMODE2
GND
VDDEXT
GND
VDDEXT
GND
VDDEXT
ADDR8
ADDR6
ADDR3
PF0
EMU
TDI
GND
DATA12
DATA9
DATA6
DATA3
Ball No.
M9
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Mnemonic
DATA0
GND
ADDR15
ADDR9
ADDR10
ADDR11
TRST
TMS
TDO
BMODE0
DATA13
DATA10
DATA7
DATA4
DATA1
BGH
ADDR16
ADDR14
ADDR13
ADDR12
VDDEXT
TCK
BMODE1
DATA15
DATA14
DATA11
DATA8
DATA5
DATA2
BG
ADDR19
ADDR18
ADDR17
GND
ADSP-BF534/ADSP-BF536/ADSP-BF537
Figure 61 shows the top view of the CSP_BGA
ball configuration. Figure 62 shows the bottom view of the
CSP_BGA ball configuration.
1
2
3
4
5
6
7
8
9
10 11 12 13 14
14 13 12 11 10 9
8
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
KEY:
KEY:
VDDINT
VDDEXT
GND
I/O
VDDRTC
VDDINT
VROUT
VDDEXT
Figure 61. 182-Ball CSP_BGA Configuration (Top View)
Rev. E |
GND
I/O
VDDRTC
VROUT
Figure 62. 182-Ball CSP_BGA Configuration (Bottom View)
Page 61 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
208-BALL SPARSE CSP_BGA BALL ASSIGNMENT
Table 50 lists the sparse CSP_BGA ball assignment by signal
mnemonic. Table 51 on Page 63 lists the sparse CSP_BGA ball
assignment by ball number.
Table 50. 208-Ball Sparse CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic)
Mnemonic
ABE0
ABE1
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BMODE2
BR
CLKBUF
CLKIN
CLKOUT
DATA0
DATA1
DATA10
DATA11
Ball No.
P19
P20
R19
W18
Y18
W17
Y17
W16
Y16
W15
Y15
W14
Y14
T20
T19
U20
U19
V20
V19
W20
Y19
M20
M19
G20
G19
N20
J19
N19
R20
Y11
Y12
W13
W12
W11
F19
B14
A18
H19
Y10
W10
Y5
W5
Mnemonic
DATA12
DATA13
DATA14
DATA15
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
Y4
W4
Y3
W3
Y9
W9
Y8
W8
Y7
W7
Y6
W6
T1
A1
A13
A20
B2
G11
H9
H10
H11
H12
H13
J9
J10
J11
J12
J13
K9
K10
K11
K12
K13
L9
L10
L11
L12
L13
M9
M10
M11
M12
Mnemonic
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NMI
PF0
PF1
PF10
PF11
PF12
PF13
PF14
PF15
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PG0
PG1
PG10
PG11
PG12
PG13
PG14
PG15
PG2
PG3
PG4
PG5
Rev. E |
Ball No.
M13
N9
N10
N11
N12
N13
P11
V2
W2
W19
Y1
Y13
Y20
C20
T2
R1
L2
K1
K2
J1
J2
H1
R2
P1
P2
N1
N2
M1
M2
L1
H2
G1
C2
B1
A2
A3
B3
A4
G2
F1
F2
E1
Page 62 of 68 |
Mnemonic
PG6
PG7
PG8
PG9
PH0
PH1
PH10
PH11
PH12
PH13
PH14
PH15
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PJ0
PJ1
PJ10
PJ11
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
RESET
RTXO
RTXI
SA10
SCAS
SCKE
SMS
SRAS
SWE
TCK
March 2008
Ball No.
E2
D1
D2
C1
B4
A5
B9
A10
B10
A11
B11
A12
B5
A6
B6
A7
B7
A8
B8
A9
B12
B13
B19
C19
D19
E19
B18
A19
B15
B16
B17
B20
D20
A15
A14
L20
K20
H20
J20
K19
L19
W1
Mnemonic
TDI
TDO
TMS
TRST
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Ball No.
V1
Y2
U2
U1
G7
G8
G9
G10
H7
H8
J7
J8
K7
K8
L7
L8
M7
M8
N7
N8
P7
P8
P9
P10
G12
G13
G14
H14
J14
K14
L14
M14
N14
P12
P13
P14
A16
E20
F20
A17
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 51 lists the sparse CSP_BGA ball assignment by ball number. Table 50 on Page 62 lists the sparse CSP_BGA ball
assignment by signal mnemonic.
Table 51. 208-Ball Sparse CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
C2
Mnemonic
GND
PG12
PG13
PG15
PH1
PH3
PH5
PH7
PH9
PH11
PH13
PH15
GND
RTXI
RTXO
VDDRTC
XTAL
CLKIN
PJ5
GND
PG11
GND
PG14
PH0
PH2
PH4
PH6
PH8
PH10
PH12
PH14
PJ0
PJ1
CLKBUF
PJ6
PJ7
PJ8
PJ4
PJ10
PJ9
PG9
PG10
Ball No.
C19
C20
D1
D2
D19
D20
E1
E2
E19
E20
F1
F2
F19
F20
G1
G2
G7
G8
G9
G10
G11
G12
G13
G14
G19
G20
H1
H2
H7
H8
H9
H10
H11
H12
H13
H14
H19
H20
J1
J2
J7
J8
Mnemonic
PJ11
NMI
PG7
PG8
PJ2
RESET
PG5
PG6
PJ3
VROUT0
PG3
PG4
BR
VROUT1
PG1
PG2
VDDEXT
VDDEXT
VDDEXT
VDDEXT
GND
VDDINT
VDDINT
VDDINT
AMS3
AMS2
PF15
PG0
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
CLKOUT
SCKE
PF13
PF14
VDDEXT
VDDEXT
Ball No.
J9
J10
J11
J12
J13
J14
J19
J20
K1
K2
K7
K8
K9
K10
K11
K12
K13
K14
K19
K20
L1
L2
L7
L8
L9
L10
L11
L12
L13
L14
L19
L20
M1
M2
M7
M8
M9
M10
M11
M12
M13
M14
Rev. E |
Mnemonic
GND
GND
GND
GND
GND
VDDINT
ARDY
SMS
PF11
PF12
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
SRAS
SCAS
PF9
PF10
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
SWE
SA10
PF7
PF8
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
Page 63 of 68 |
Ball No.
M19
M20
N1
N2
N7
N8
N9
N10
N11
N12
N13
N14
N19
N20
P1
P2
P7
P8
P9
P10
P11
P12
P13
P14
P19
P20
R1
R2
R19
R20
T1
T2
T19
T20
U1
U2
U19
U20
V1
V2
V19
V20
March 2008
Mnemonic
AMS1
AMS0
PF5
PF6
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
ARE
AOE
PF3
PF4
VDDEXT
VDDEXT
VDDEXT
VDDEXT
GND
VDDINT
VDDINT
VDDINT
ABE0
ABE1
PF1
PF2
ADDR1
AWE
EMU
PF0
ADDR3
ADDR2
TRST
TMS
ADDR5
ADDR4
TDI
GND
ADDR7
ADDR6
Ball No.
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Mnemonic
TCK
GND
DATA15
DATA13
DATA11
DATA9
DATA7
DATA5
DATA3
DATA1
BMODE2
BMODE1
BMODE0
ADDR18
ADDR16
ADDR14
ADDR12
ADDR10
GND
ADDR8
GND
TDO
DATA14
DATA12
DATA10
DATA8
DATA6
DATA4
DATA2
DATA0
BG
BGH
GND
ADDR19
ADDR17
ADDR15
ADDR13
ADDR11
ADDR9
GND
ADSP-BF534/ADSP-BF536/ADSP-BF537
Figure 63 shows the top view of the sparse CSP_BGA ball configuration. Figure 64 shows the bottom view of the sparse
CSP_BGA ball configuration.
1
2
3
4
5
6
7
8
9
20 19 18 17 16 15 14 13 12 11 10
10 11 12 13 14 15 16 17 18 19 20
9
8
7
6
5
4
3
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
T
T
U
U
V
V
W
W
Y
Y
KEY:
VDDEXT
GND
I/O
VDDINT
VDDRTC
VDDEXT
VROUT
GND
I/O
VDDRTC
VROUT
Figure 64. 208-Ball CSP_BGA Configuration (Bottom View)
Figure 63. 208-Ball CSP_BGA Configuration (Top View)
Rev. E |
1
A
KEY:
VDDINT
2
Page 64 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
OUTLINE DIMENSIONS
Dimensions in Figure 65 and Figure 66 are shown in
millimeters.
A1 CORNER
INDEX AREA
12.00 BSC SQ
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
PIN A1
INDICATOR
LOCATION
10.40
BSC
SQ
0.80
BSC
TYP
TOP VIEW
BOTTOM VIEW
1.31
1.21
1.10
DETAIL A
1.70 MAX
0.25 MIN
SEATING
PLANE
NOTES:
1. COMPLIANT TO JEDEC STANDARD MO-205-AE,
EXCEPT FOR BALL DIAMETER.
2. CENTER DIMENSIONS ARE NOMINAL.
3. THE ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE
TO THE PACKAGE EDGES
0.50
0.12
0.45
COPLANARITY
0.40
(BALL
DIAMETER)
DETAIL A
Figure 65. 182-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-182)
Dimensions shown in millimeters
Rev. E |
Page 65 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
17.10
17.00 SQ
16.90
A1 CORNER
INDEX AREA
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9
7 5
3 1
A1 BALL
CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
15.20
BSC SQ
0.80
BSC
TOP VIEW
BOTTOM VIEW
DETAIL A
*1.75
1.61
1.46
DETAIL A
1.36
1.26
1.16
0.35 NOM
0.30 MIN
SEATING
PLANE
*0.50
0.45
0.40
BALL
DIAMETER
COPLANARITY
0.12
*COMPLIANT TO JEDEC STANDARDS MO-205-AM WITH
EXCEPTION TO PACKAGE HEIGHT AND BALL DIAMETER.
Figure 66. 208-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-208-2)
Dimensions shown in millimeters
SURFACE MOUNT DESIGN
The following table is provided as an aid to PCB design. For
industry-standard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pattern Standard.
Package
182-Ball CSP_BGA (BC-182)
208-Ball Sparse CSP_BGA (BC-208-2)
Ball Attach Type
Solder Mask Defined
Solder Mask Defined
Rev. E |
Page 66 of 68 |
Solder Mask Opening
0.40 mm diameter
0.40 mm diameter
March 2008
Ball Pad Size
0.55 mm diameter
0.55 mm diameter
ADSP-BF534/ADSP-BF536/ADSP-BF537
ORDERING GUIDE
Model
ADSP-BF534BBC-4A
ADSP-BF534BBCZ-4A2, 3
ADSP-BF534BBC-5A
ADSP-BF534BBCZ-5A2
ADSP-BF534BBCZ-4B2, 3
ADSP-BF534YBCZ-4B2, 3
ADSP-BF534BBCZ-5B2
ADSP-BF536BBC-3A
ADSP-BF536BBCZ-3A2
ADSP-BF536BBC-4A
ADSP-BF536BBCZ-4A2
ADSP-BF536BBCZ-3B2
ADSP-BF536BBCZ-4B2
ADSP-BF537BBC-5A
ADSP-BF537BBCZ-5A2
ADSP-BF537BBCZ-5B2
ADSP-BF537BBCZ-5AV2
ADSP-BF537BBCZ-5BV2
ADSP-BF537KBCZ-6AV2
ADSP-BF537KBCZ-6BV2
Temperature
Range1
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
Speed Grade
(Max)
400 MHz
400 MHz
500 MHz
500 MHz
400 MHz
400 MHz
500 MHz
300 MHz
300 MHz
400 MHz
400 MHz
300 MHz
400 MHz
500 MHz
500 MHz
500 MHz
533 MHz
533 MHz
600 MHz
600 MHz
Operating Voltage (Nominal)
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.26 V internal, 2.5 V or 3.3 V I/O
1.26 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.26 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.26 V internal, 2.5 V or 3.3 V I/O
1.26 V internal, 2.5 V or 3.3 V I/O
1.26 V internal, 2.5 V or 3.3 V I/O
1.25 V internal, 3.3 V I/O
1.25 V internal, 3.3 V I/O
1.3 V internal, 3.3 V I/O
1.3 V internal, 3.3 V I/O
1
Package Description
182-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
208-Ball Sparse CSP_BGA
208-Ball Sparse CSP_BGA
208-Ball Sparse CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
208-Ball Sparse CSP_BGA
208-Ball Sparse CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
208-Ball Sparse CSP_BGA
182-Ball CSP_BGA
208-Ball Sparse CSP_BGA
182-Ball CSP_BGA
208-Ball Sparse CSP_BGA
Package
Option
BC-182
BC-182
BC-182
BC-182
BC-208-2
BC-208-2
BC-208-2
BC-182
BC-182
BC-182
BC-182
BC-208-2
BC-208-2
BC-182
BC-182
BC-208-2
BC-182
BC-208-2
BC-182
BC-208-2
Referenced temperature is ambient temperature.
Z = RoHS compliant part.
3
A similar part is available for use in specific automotive applications. Contact your local ADI sales office for ADBF534W automotive ordering information.
2
Rev. E |
Page 67 of 68 |
March 2008
ADSP-BF534/ADSP-BF536/ADSP-BF537
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05317-0-3/08(E)
Rev. E |
Page 68 of 68 |
March 2008