AD OP97

a
FEATURES
Low Supply Current: 600 ␮A Max
OP07 Type Performance
Offset Voltage: 20 ␮V Max
Offset Voltage Drift: 0.6 ␮V/ⴗC Max
Very Low Bias Current
25ⴗC: 100 pA Max
–55ⴗC to +125ⴗC: 250 pA Max
High Common-Mode Rejection: 114 dB Min
Extended Industrial Temperature Range: –40ⴗC to +85ⴗC
Available In Die Form
Low-Power, High-Precision
Operational Amplifier
OP97
PIN CONNECTIONS
Epoxy Mini-DIP (P Suffix)
8-Pin Cerdip
(Z Suffix)
8-Pin SO (S Suffix)
NULL 1
OP97
8 NULL
–IN 2
7 V+
+IN 3
6 OUT
V– 4
5 OVER
COMP
GENERAL DESCRIPTION
The OP97 is a low power alternative to the industry-standard
OP07 precision amplifier. The OP97 maintains the standards of
performance set by the OP07 while utilizing only 600 µA supply
current, less than 1/6 that of an OP07. Offset voltage is an
ultralow 25 µV, and drift over temperature is below 0.6 µV/°C.
External offset trimming is not required in the majority of circuits.
Improvements have been made over OP07 specifications in
several areas. Notable is bias current, which remains below
250 pA over the full military temperature range. The OP97 is
ideal for use in precision long-term integrators or sample-andhold circuits that must operate at elevated temperatures.
Common-mode rejection and power supply rejection are also
improved with the OP97, at 114 dB minimum over wider
ranges of common-mode or supply voltage. Outstanding
PSR, a supply range specified from ± 2.25 V to ± 20 V and the
OP97’s minimal power requirements combine to make the
OP97 a preferred device for portable and battery-powered
instruments.
The OP97 conforms to the OP07 pinout, with the null potentiometer connected between Pins 1 and 8 with the wiper to V+.
The OP97 will upgrade circuit designs using 725, OP05, OP07,
OP12, and 1012 type amplifiers. It may replace 741-type amplifiers in circuits without nulling or where the nulling circuitry has
been removed.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
OP97–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = ⴞ15 V, VCM = 0 V, TA = 25ⴗC, unless otherwise noted.)
Conditions
Min
OP97A/E
Typ
Parameter
Symbol
Input Offset Voltage
Long-Term Offset
Voltage Stability
Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise Voltage Density
VOS
10
∆VOS/Time
IOS
IB
en p-p
en
Input Noise Current Density
Large-Signal Voltage Gain
Common-Mode Rejection
Power-Supply Rejection
Input Voltage Range
Output Voltage Swing
Slew Rate
Differential Input Resistance
Closed-Loop Bandwidth
Supply Current
Supply Voltage
in
AVO
CMR
PSR
IVR
VO
SR
RIN
BW
ISY
VS
0.3
30
± 30
0.5
17
14
20
2000
132
132
± 14.0
± 14
0.2
0.1 Hz to 10 Hz
fO = 10 Hz2
fO = 1000 Hz3
fO = 10 Hz
VO = ± 10 V; RL = 2 kΩ
VCM = ± 13.5 V
VS = ± 2 V to ± 20 V
(Note 1)
RL = 10 kΩ
(Note 4)
AVCL = 1
300
114
114
± 13.5
± 13
0.1
30
0.4
±2
Operating Range
Max
OP97F
Typ
Min
25
0.9
380
± 15
100
± 100
30
22
200
110
110
± 13.5
± 13
0.1
30
0.4
600
± 20
±2
Max
Unit
30
75
µV
0.3
30
± 30
0.5
17
14
20
2000
132
132
± 14.0
± 14
0.2
µV/Month
150
pA
± 150 pA
µV p-p
30
nV/√Hz
22
nV/√Hz
fA/√Hz
V/mV
dB
dB
V
V
V/µs
MΩ
MHz
600
µA
± 20 V
0.9
380
± 15
NOTES
1
Guaranteed by CMR test.
2
10 Hz noise voltage density is sample tested. Devices 100% tested for noise are available on request.
3
Sample tested.
4
Guaranteed by design.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
(@ VS = ⴞ15 V, VCM = 0 V, –40ⴗC ≤ TA ≤ +85ⴗC for the OP97E/F and –55ⴗC ≤ TA ≤ +125ⴗC
for the OP97A, unless otherwise noted.)
OP97A/E
Typ
Max
25
0.2
60
0.6
IOS
TCIOS
60
0.4
IB
Parameter
Symbol
Conditions
Input Offset Voltage
Average Temperature
Coefficient of VOS
Input Offset Current
Average Temperature
Coefficient of IOS
Input Bias Current
Average Temperature
Coefficient of IB
Large Signal Voltage Gain
Common-Mode Rejection
Power Supply Rejection
Input Voltage Range
Output Voltage Swing
Slew Rate
Supply Current
Supply Voltage
VOS
TCVOS
S-Package
TCIB
AVO
CMR
PSR
IVR
VO
SR
ISY
VS
Min
VO = 10 V; RL = 2 kΩ
VCM = ± 13.5 V
VS = ± 2.5 V to ± 20 V
(Note 1)
RL = 10 kΩ
200
108
108
± 13.5
± 13
0.05
Operating Range
± 2.5
Min
OP97F
Typ
Max
Unit
200
2.0
µV
µV/°C
250
2.5
60
0.3
0.3
80
0.6
750
7.5
pA
pA/°C
± 60
± 250
± 80
± 750
pA
0.4
1000
128
126
± 14.0
± 14
0.15
400
± 15
2.5
0.6
1000
128
128
± 14.0
± 14
0.15
400
± 15
7.5
pA/°C
V/mV
dB
dB
V
V
V/µs
µA
V
150
108
108
± 13.5
± 13
0.05
800
± 20
± 2.5
800
± 20
NOTES
1
Guaranteed by CMR test.
Specifications subject to change without notice.
–2–
REV. D
OP97
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . ± 1 V
Differential Input Current3 . . . . . . . . . . . . . . . . . . . . ± 10 mA
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Operating Temperature Range
OP97A (Z) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP97E, F (P, Z, S) . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . 300°C
Package Type
␪JA4
␪JC
Unit
8-Lead Hermetic DIP (Z)
8-Lead Plastic DIP (P)
8-Lead SO (S)
148
103
158
16
43
43
°C/W
°C/W
°C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than ± 20 V, the absolute maximum input voltage is equal
to the supply voltage.
3
The OP97’s inputs are protected by back-to-back diodes. Current-limiting resistors are not used in order to achieve low noise. Differential input voltages greater
than 1 V will cause excessive current to flow through the input protection diodes
unless limiting resistance is used.
4
θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for TO, cerdip, and P-DIP packages; θJA is specified for device soldered
to printed circuit board for SO package.
Model
Temperature
Range
Package
Option1
OP97AZ3
OP97ARC/8832, 3
OP97EJ3
OP97EZ3
OP97EP
OP97FZ3
OP97FP
OP97FS
OP97FS-REEL
OP97FS-REEL7
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Cerdip
20-Contact LCC
TO-99
8-Lead Cerdip
8-Lead Plastic DIP
8-Lead Cerdip
8-Lead Plastic DIP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
NOTES
1
For outline information see Package Information section.
2
For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for /883 data sheet.
3
Not for new designs; obsolete April 2002.
For Military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
SMD Part Number
ADI Equivalent
59628954401PA
59628954401GA*
OP97AZMDA
OP97AJMDA
*Not
for new designs; obsolete April 2002.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP97 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. D
–3–
WARNING!
ESD SENSITIVE DEVICE
OP97–Typical Performance Characteristics
400
400
VS = 15V
TA = 25 C
VCM = 0V
1894 UNITS
VS = 15V
TA = 25 C
VCM = 0V
1894 UNITS
400
NUMBER OF UNITS
200
NUMBER OF UNITS
300
300
NUMBER OF UNITS
500
VS = 15V
TA = 25 C
VCM = 0V
1920 UNITS
200
300
200
100
100
100
0
–40
–20
0
20
INPUT OFFSET VOLTAGE – ␮V
0
–100
40
TPC 1. Typical Distribution of Input
Offset Voltage
0
–20
IOS
–40
0
IOS
–20
0
25
50
75
100
–60
–15
125
100
–55 C
TA
+125 C
TA = 25 C
3k
10k 30k 100k 300k 1M 3M 10M
SOURCE RESISTANCE – ⍀
TPC 7. Effective Offset Voltage vs.
Source Resistance
ⴞ3
ⴞ2
J PACKAGES
ⴞ1
Z, P PACKAGES
0
2
3
4
5
1
TIME AFTER POWER APPLIED – Minutes
TPC 6. Input Offset Voltage
Warm-Up Drift
20
100
BALANCED OR UNBALANCED
VS = 15V
VCM = 0V
10
1
0.1
1k
ⴞ4
15
TPC 5. Input Bias, Offset Current
vs. Common-Mode Voltage
EFFECTIVE OFFSET VOLTAGE DRIFT – ␮V/ C
BALANCED OR UNBALANCED
VS = 15V
VCM = 0V
TA = 25 C
VS = 15V
VCM = 0V
0
–10
–5
0
5
10
COMMON-MODE VOLTAGE – Volts
SHORT CIRCUIT CURRENT - mA
–50 –25
1000
EFFECTIVE OFFSET VOLTAGE – ␮V
IB+
–40
TPC 4. Input Bias, Offset Current
vs. Temperature
1
1k
IB–
20
TEMPERATURE – C
10
DEVIATION FROM FINAL VALUE – ␮V
40
INPUT CURRENT - pA
INPUT CURRENT - pA
IB+
60
ⴞ5
TA = 25 C
VS = 15V
IB–
–20
0
20
40
–40
INPUT OFFSET CURRENT – pA
TPC 3. Typical Distribution of Input
Offset Current
60
TA = 25 C
VCM = 0V
20
–60
–75
0
–60
100
TPC 2. Typical Distribution of Input
Bias Current
60
40
–50
0
50
INPUT BIAS CURRENT – pA
TA = –55 C
15
TA = +25 C
10
TA = +125 C
5
VS = 15V
OUTPUT SHORTED TO GROUND
0
–5
TA = +125 C
–10
TA = +25 C
–15
TA = –55 C
–20
10k
100k
1M
10M
SOURCE RESISTANCE – ⍀
100M
TPC 8. Effective TCVOS vs. Source
Resistance
–4–
0
1
2
3
TIME FROM OUTPUT SHORT – Minutes
TPC 9. Short Circuit Current vs.
Time, Temperature
REV. D
OP97
450
140
140
COMMON-MODE REJECTION – dB
375
TA = +25 C
350
TA = –55 C
325
300
ⴞ5
ⴞ10
ⴞ15
SUPPLY VOLTAGE – V
0
60
40
20
1
10
100
1k
10k
FREQUENCY – Hz
100k
1000
15V
10V
TA = –55 C
TA = +25 C
1000
TA = +125 C
2
5
10
LOAD RESISTANCE – k⍀
VOLTAGE NOISE
10
10
1/f CORNER
2.5Hz
1/f CORNER
120Hz
1
1k
20
TPC 13. Open-Loop Gain vs. Load
Resistance
DIFFERENTIAL INPUT VOLTAGE – 10␮V/DIV
100
CURRENT NOISE
100
1
20V
100
OUTPUT SWING – V p-p
TA = +125 C
TA = +25 C
25
80
+PSR
60
40
1
1M
100k
10
100 1k
10k
FREQUENCY – Hz
TA = 25 C
VS = 2V TO
20V
1kHz
10Hz
1
R
R
RS = 2R
0.1
10Hz
1kHz
RESISTOR NOISE
10k
100k
1M
FREQUENCY – Hz
10M
1
100M
0.01
102
104
105
106
107
103
SOURCE RESISTANCE – ⍀
108
TPC 15. Total Noise Density vs.
Source Resistance
35
35
30
–PSR
10
TPC 14. Noise Density vs.
Frequency
RL = 10k⍀
VS = 15V
VCM = 0V
100
TPC 12. Power-Supply Rejection
vs. Frequency
1000
TA = 25 C
VS = 2V TO
VOLTAGE NOISE DENSITY – nV/ Hz
VS =
VO =
TA = 25 C
VS = 15V
⌬VS = 10V p–p
120
20
0.1
1M
TPC 11. Common-Mode Rejection
vs. Frequency
10000
OPEN-LOOP GAIN – V/mV
80
0
ⴞ20
TPC 10. Supply Current vs. Supply
Voltage
100
TOTAL NOISE DENSITY – ␮V/ Hz
TA = +125 C
CURRENT NOISE DENSITY – fV/ Hz
400
120
TA = 25 C
VS = 15V
AVCL = +1
1% THD
fO = 1kHz
TA = 25 C
VS = 15V
AVCL = 1
1% THD
Rl = 10k⍀
30
OUTPUT SWING – V p-p
SUPPLY CURRENT – ␮A
425
POWER-SUPPLY REJECTION – dB
TA = 25 C
VS = 15V
VCM = 10V
NO LOAD
20
15
10
25
20
15
10
5
5
TA = –55 C
–15
–10
–5
0
5
10
OUTPUT VOLTAGE – V
15
Figure 16. Open-Loop Gain Linearity
REV. D
1
10
100
1k
LOAD RESISTANCE – ⍀
10k
TPC 17. Maximum Output Swing
vs. Load Resistance
–5–
1
100
10k
1k
FREQUENCY – Hz
100k
TPC 18. Maximum Output Swing
vs. Frequency
OP97
10
70
GAIN
TA = 25 C
VS = 15V
RL = 10k⍀
1% THD
VOUT = 3V RMS
90
135
20
TA = +125 C
TA = –55 C
0
–20
180
225
VS =
= 15V
15V
V
S
TA = –55 C
C
L=
= 20pF
20pF
CL
TA = +125 C
R
=
1M⍀
L = 1M⍀
RL
100pF
OVERCOMPENSATION
100pF OVERCOMPENSATION
–40
–60
100
1k
10k
100k
FREQUENCY – Hz
1M
1
THD + N – %
PHASE
40
PHASE SHIFT – Degrees
0.1
AVCL = 100
0.01
AVCL = 10
0.001
AVCL = 1
0.0001
10
10M
TPC 19. Open-Loop Gain, Phase vs.
Frequency (COC = 0 pF)
100
1k
FREQUENCY – Hz
225
–20
–60
100
VS = 15V
TA = +125 C
CL = 20pF
TA = –55 C
RL = 1M⍀
100pF OVERCOMPENSATION
1k
10k
100k
FREQUENCY – Hz
1M
1
1
135
TA = –55 C
TA = +125 C
180
225
–20
VS = 15V
CL = 20pF
RL = 1M⍀
100pF OVERCOMPENSATION
1k
10k
100k
FREQUENCY – Hz
OPEN-LOOP GAIN – dB
90
PHASE
GAIN
1000
10M
TPC 25. Open-Loop Gain, Phase vs.
Frequency (COC = 1000 pF)
100
PHASE
0
135
GAIN
180
TA = +125 C
TA = –55 C
–20
–40
1M
TA = 25 C
VS = 15V
90
40
20
–60
100
10
100
10000
1000
OVERCOMPENSATION CAPACITOR – pF
TPC 24. Gain Bandwidth Product vs.
Overcompensation
TA = +125 C
TA = +25 C
TA = +125 C
60
PHASE SHIFT – Degrees
OPEN-LOOP GAIN – dB
VS = 15V
CL = 20pF
RL = 1M⍀
AV = 100
80
40
–60
100
10
10
100
10000
1000
OVERCOMPENSATION CAPACITOR – pF
TPC 23. Slew Rate vs. Overcompensation
TA = –55 C
TA = +25 C
TA = +125 C
60
–40
0.01
1
80
0
TA = +125 C
100
0.001
TPC 22. Open-Loop Gain, Phase vs.
Frequency (COC = 100 pF)
20
TA = –55 C
0.1
10M
10000
100
1000
LOAD CAPACITANCE – pF
TA = –55 C
225
VS = 15V
CL = 20pF
RL = 1M⍀
100pF OVERCOMPENSATION
OUTPUT IMPEDANCE – ⍀
–40
20
TPC 21. Small Signal Overshoot vs.
Capacitive Load
GAIN-BANDWIDTH – kHz
180
SLEW RATE – V/␮s
0
TA = –55 C
TA = +125 C
PHASE SHIFT – Degrees
OPEN-LOOP GAIN – dB
135
20
30
Rl = 10k⍀
VS = 15V
CL = 100pF
TA = +125 C
90
–EDGE
1000
60
PHASE
+EDGE
40
0
10
10k
1
GAIN
40
50
10
TPC 20. Total Harmonic Distortion
Plus Noise vs. Frequency
80
TA = 25 C
VS = 15V
AVCL = +1
VOUT = 100mV p-p
COC = 0pF
60
PHASE SHIFT – Degrees
OPEN-LOOP GAIN – dB
60
OVERSHOOT – %
80
10
AVCL = 1000
1
AVCL = 1
0.1
0.01
0.001
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 26. Open-Loop Gain, Phase vs.
Frequency (COC = 10,000 pF)
–6–
1
10
100
1k
FREQUENCY – Hz
10k
100k
TPC 27. Closed-Loop Output Resistance vs. Frequency
REV. D
OP97
APPLICATIONS INFORMATION
The OP97 is a low power alternative to the industry standard
precision op amp, the OP07. The OP97 may be substituted
directly into OP07, OP77, 725, 112/312, and 1012 sockets with
improved performance and/or less power dissipation, and may
be inserted into sockets conforming to the 741 pinout if nulling
circuitry is not used. Generally, nulling circuitry used with earlier
generation amplifiers is rendered superfluous by the OP97’s
extremely low offset voltage, and may be removed without compromising circuit performance.
Extremely low bias current over the full military temperature
range makes the OP97 attractive for use in sample-and-hold
amplifiers, peak detectors, and log amplifiers that must operate
over a wide temperature range. Balancing input resistances is
not necessary with the OP97. Offset voltage and TCVOS are
degraded only minimally by high source resistance, even when
unbalanced.
The input pins of the OP97 are protected against large differential voltage by back-to-back diodes. Current-limiting resistors
are not used so that low noise performance is maintained. If
differential voltages above ± 1 V are expected at the inputs,
series resistors must be used to limit the current flow to a
maximum of 10 mA. Common-mode voltages at the inputs are
not restricted, and may vary over the full range of the supply
voltages used.
The OP97 requires very little operating headroom about the
supply rails, and is specified for operation with supplies as low
as ± 2 V. Typically, the common-mode range extends to within
one volt of either rail. The output typically swings to within one
volt of the rails when using a 10 kΩ load.
Offset nulling is achieved utilizing the same circuitry as an
OP07. A potentiometer between 5 kΩ and 100 kΩ is connected
between pins 1 and 8 with the wiper connected to the positive
supply. The trim range is between 300 µV and 850 µV, depending upon the internal trimming of the device.
AC PERFORMANCE
The OP97’s ac characteristics are highly stable over its full
operating temperature range. Unity-gain small-signal response
is shown in Figure 2. Extremely tolerant of capacitive loading
on the output, the OP97 displays excellent response even with
1000 pF loads (Figure 3). In large-signal applications, the
input protection diodes effectively short the input to the output
during the transients if the amplifier is connected in the usual
unity-gain configuration. The output enters short-circuit current
limit, with the flow going through the protection diodes. Improved
large-signal transient response is obtained by using a feedback
resistor between the output and the inverting input. Figure 4
shows the large-signal response of the OP97 in unity gain with a
10 kΩ feedback resistor. The unity gain follower circuit is shown
in Figure 5.
The overcompensation pin may be used to increase the phase
margin of the OP97, or to decrease gain-bandwidth product at
gains greater than 10.
+V
RPOT = 5k⍀ TO 100k⍀
OP97
COC
–V
Figure 1. Optional Input Offset Voltage Nulling
and Overcompensation Circuits
Figure 3. Small-Signal Transient Response
(CLOAD = 1000 pF, AVCL = 1)
Figure 2. Small-Signal Transient Response
(CLOAD = 100 pF, AVCL = 1)
REV. D
Figure 4. Large-Signal Transient Response (AVCL = 1)
–7–
OP97
10k⍀
30pF
RFB
IO
2
OP97
VIN
2
6
OP97
PM7548
6
VOUT
3
VOUT
IO
3
DIGITAL
INPUTS
Figure 5. Unity-Gain Follower
Figure 7. DAC Output Amplifier
R1
10k⍀
IL
V1
R2
10k⍀
R5
10k⍀
R3
10k⍀
RL
+15V
2
7
6
OP97
3
Figure 6. Small-Signal Transient Response with Overcompensation (CLOAD = 1000 pF, AVCL = 1, COC = 220 pF)
VOUT
4
R4
10k⍀
–15V
Figure 8. Current Monitor
GUARDING AND SHIELDING
To maintain the extremely high input impedances of the OP97,
care must be taken in circuit board layout and manufacturing.
Board surfaces must be kept scrupulously clean and free of moisture.
Conformal coating is recommended to provide a humidity barrier.
Even a clean PC board can have 100 pA of leakage currents between
adjacent traces, so that guard rings should be used around the
inputs. Guard traces are operated at a voltage close to that on the
inputs, so that leakage currents become minimal. In noninverting applications, the guard ring should be connected to the
common-mode voltage at the inverting input (Pin 2). In inverting
applications, both inputs remain at ground, so that the guard trace
should be grounded. Guard traces should be made on both sides
of the circuit board.
High impedance circuitry is extremely susceptible to RF pickup,
line frequency hum, and radiated noise from switching power
supplies. Enclosing sensitive analog sections within grounded
shields is generally necessary to prevent excessive noise pickup.
Twisted-pair cable will aid in rejection of line frequency hum.
The OP97 is an excellent choice as an output amplifier for higher
resolution CMOS DACs. Its tightly trimmed offset voltage and
minimal bias current result in virtually no degradation of linearity, even over wide temperature ranges.
Figure 8 shows a versatile monitor circuit that can typically
sense current at any point between the ± 15 V supplies. This
makes it ideal for sensing current in applications such as full
bridge drivers where bidirectional current is associated with large
common-mode voltage changes. The 114 dB CMRR of the OP97
makes the amplifier’s contribution to common-mode error
negligible, leaving only the error due to the resistor ratio
inequality. Ideally, R2/R4 = R3/R5. This is best trimmed via R4
UNITY-GAIN FOLLOWER
NONINVERTING AMPLIFIER
2
2
OP97
6
6
OP97
3
3
TO-99
BOTTOM VIEW
1
8
INVERTING AMPLIFIER
2
OP97
MINI-DIP
BOTTOM VIEW
8
1
6
3
Figure 9. Guard Ring Layout and Connections
–8–
REV. D
OP97
The digitally programmable gain amplifier shown in Figure 10
has 12-bit gain resolution with 10-bit gain linearity over the
range of –1 to –1024. The low bias current of the OP97 maintains this linearity, while C1 limits the noise voltage bandwidth
allowing accurate measurement down to microvolt levels.
R2
20k⍀
5pF
VIN
R1
2k⍀
1␮F
2
10k⍀
DIGITAL IN
GAIN (Av)
4095
2048
1024
512
256
128
64
32
16
8
4
2
1
0
–1.00024
–2
–4
–8
–16
–32
–64
–128
–256
–512
–1024
–2048
–4096
OPEN LOOP
10k⍀
18
VREF
Figure 12. Combination Amplifier Transient Response
.
17
2
3
IOUT 2
PM7541
C1
220pF
+15V
2
0.1␮F
OP97
6
VOUT
3
0.1␮F
–15V
Figure 10. Precision Programmable Gain Amplifier
REV. D
R2
R1
Figure 11. Combination High-Speed, Precision Amplifier
RFB
IOUT 1
AV =
5
0.1␮F
0.1␮F
16
6
OP97
3
+15V
VIN
VOUT
2
Many high-speed amplifiers suffer from less-than-perfect lowfrequency performance. A combination amplifier consisting of a
high precision, slow device like the OP97 and a faster device
such as the OP44 results in uniformly accurate performance
from dc to the high frequency limit of the OP44, which has a
gain-bandwidth product of 23 MHz. The circuit shown in Figure 11
accomplishes this, with the OP44 providing high frequency
amplification and the OP97 operating on low frequency signals
and providing offset correction. Offset voltage and drift of the
circuit are controlled by the OP97.
ⴞ2.5mV TO ⴞ10V
RANGE DEPENDING
ON GAIN SETTING
1
6
OP44
3
–9–
OP97
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8-Pin Hermetic DIP
(Q-8)
0.430 (10.92)
0.348 (8.84)
8
0.005 (0.13)
MIN
8
5
0.280 (7.11)
0.240 (6.10)
1
5
0.310 (7.87)
0.220 (5.59)
PIN 1
4
1
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
4
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.195 (4.95)
0.115 (2.93)
0.200 (5.08)
MAX
0.130
(3.30)
MIN
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
0.055 (1.4)
MAX
0.200 (5.08)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
0.023 (0.58) 0.070 (1.78) PLANE
0.014 (0.36) 0.030 (0.76)
15°
0°
0.015 (0.38)
0.008 (0.20)
8-Pin SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
8ⴗ
0.0500 (1.27)
0.0098 (0.25) 0ⴗ
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
–10–
REV. D
OP97
Revision History
Location
Page
Data Sheet changed from REV. C to REV. D.
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
REV. D
–11–
–12–
PRINTED IN U.S.A.
C00299–0–1/02(D)