NTTD1P02R2 Product Preview Power MOSFET -1.45 Amps, -20 Volts P–Channel Enhancement Mode Dual Micro8 Package http://onsemi.com Features • • • • • • Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual Micro8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided –1.45 AMPERES –20 VOLTS 160 m @ VGS = –4.5 Applications Dual P–Channel • Power Management in Portable and Battery–Powered Products, i.e.: D Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol G Value Unit Drain–to–Source Voltage VDSS –20 V Gate–to–Source Voltage – Continuous VGS 8.0 V Thermal Resistance – Junction–to–Ambient (Note 1.) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 70°C Pulsed Drain Current (Note 3.) RθJA PD ID ID IDM 250 0.50 –1.45 –1.15 –10 °C/W W A A A Thermal Resistance – Junction–to–Ambient (Note 2.) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 70°C Pulsed Drain Current (Note 3.) RθJA PD ID ID IDM 125 1.0 –2.04 –1.64 –16 °C/W W A A A TJ, Tstg –55 to +150 °C Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C (VDD = –20 Vdc, VGS = –4.5 Vdc, Peak IL = –3.5 Apk, L = 5.6 mH, RG = 25 Ω) EAS 35 mJ Maximum Lead Temperature for Soldering Purposes for 10 seconds TL 260 °C Operating and Storage Temperature Range This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. November, 2000 – Rev. 0 8 1 Micro8 CASE 846A STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENT Source 1 Gate 1 Source 2 Gate 2 1 8 2 YWW 7 3 6 BC 4 5 Drain 1 Drain 1 Drain 2 Drain 2 (Top View) 1. Minimum FR–4 or G–10 PCB, Steady State. 2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), Steady State. 3. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%. Semiconductor Components Industries, LLC, 2000 S 1 Y = Year WW = Work Week BC = Device Code ORDERING INFORMATION Device Package Shipping NTTD1P02R2 Micro8 4000/Tape & Reel Publication Order Number: NTTD1P02R2/D NTTD1P02R2 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) * Symbol Characteristic Min Typ Max Unit –20 – – –12 – – – – – – –1.0 –10 – – –100 – – 100 –0.7 – –0.95 2.3 –1.4 – – – – 0.130 0.175 0.190 0.160 0.250 – gFS – 2.5 – Mhos Ciss – 265 – pF Coss – 100 – Crss – 60 – td(on) – 10 – tr – 25 – td(off) – 30 – tf – 25 – td(on) – 10 – tr – 20 – td(off) – 30 – tf – 20 – Qtot – 5.0 10 Qgs – 1.5 – Qgd – 2.0 – VSD – – –0.91 –0.72 –1.1 – Vdc trr – 25 – ns ta – 13 – tb – 12 – QRR – 0.015 – OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = –250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = –20 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = –20 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = –8 Vdc, VDS = 0 Vdc) IGSS Gate–Body Leakage Current (VGS = +8 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C µAdc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = –250 µAdc) Temperature Coefficient (Negative) VGS(th) Static Drain–to–Source On–State Resistance (VGS = –4.5 Vdc, ID = –1.45 Adc) (VGS = –2.7 Vdc, ID = –0.7 Adc) (VGS = –2.5 Vdc, ID = –0.7 Adc) RDS(on) Forward Transconductance (VDS = –10 Vdc, ID = –0.7 Adc) Vdc Ω DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = –16 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 4. and 5.) Turn–On Delay Time Rise Time Turn–Off Delay Time (VDD = –16 16 Vdc, ID = –1.45 1.45 Adc, VGS = –4.5 Vdc, RG = 6.0 Ω) Fall Time Turn–On Delay Time Rise Time Turn–Off Delay Time (VDD = –16 16 Vdc, ID = –0.7 0.7 Adc, VGS = –4.5 Vdc, RG = 6.0 Ω) Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge (VDS = –16 Vdc, VGS = –4.5 Vdc, ID = –1.45 1 45 Adc) Ad ) ns ns nC BODY–DRAIN DIODE RATINGS (Note 4.) Diode Forward On–Voltage (IS = –1.45 Adc, VGS = 0 Vdc) (IS = –1.45 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = –1.45 1 45 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/µs) Reverse Recovery Stored Charge 4. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%. 5. Switching characteristics are independent of operating junction temperature. * Handling precautions to protect against electrostatic discharge is mandatory. http://onsemi.com 2 µC NTTD1P02R2 3 –2.5 V –2.3 V –ID, DRAIN CURRENT (AMPS) –ID, DRAIN CURRENT (AMPS) 3 –2.7 V –2.9 V –3.1 V –3.3 V –3.7 V –4.5 V 2 TJ = 25°C –2.1 V –8 V –1.9 V 1 –1.7 V VGS = –1.5 V 0 0.25 0.5 0.75 1 1.25 1.5 TJ = –55°C 1 1.75 TJ = 100°C TJ = 25°C 1 2 1.5 2.5 3 Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics ID = –1.45 A TJ = 25°C 0.3 0.2 0.1 0 2 4 6 8 10 12 3.5 0.3 TJ = 25°C VGS = –2.5 V 0.2 VGS = –2.7 V VGS = –4.5 V 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) –ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Gate–to–Source Voltage Figure 4. On–Resistance versus Drain Current and Gate Voltage 1.6 100 VGS = 0 V ID = –1.45 A VGS = –4.5 V –IDSS, LEAKAGE (nA) 1.4 0.5 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 0.4 0 0 –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN–TO–SOURCE RESISTANCE () RDS(on), DRAIN–TO–SOURCE RESISTANCE () 2 0 0 RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) VDS ≥ –10 V 1.2 1 TJ = 125°C TJ = 100°C 10 0.8 0.6 –50 1 –25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 4 Figure 5. On–Resistance Variation with Temperature 8 12 16 –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 6. Drain–to–Source Leakage Current versus Voltage http://onsemi.com 3 20 VDS = 0 V Ciss VGS = 0 V C, CAPACITANCE (pF) TJ = 25°C 600 Crss 400 Ciss 200 Coss Crss 0 5 10 0 –VGS –VDS 5 10 15 20 5 20 QT 18 16 4 14 –VGS 3 Q1 12 10 Q2 8 2 6 1 ID = –1.45 A TJ = 25°C –VDS 4 2 0 0 0 1 2 3 4 5 6 Qg, TOTAL GATE CHARGE (nC) GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 800 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) NTTD1P02R2 Figure 8. Gate–to–Source and Drain–to–Source Voltage versus Total Charge Figure 7. Capacitance Variation 100 –IS, SOURCE CURRENT (AMPS) t, TIME (ns) VDD = –16 V ID = –1.45 A VGS = –4.5 V tr td (off) tf 10 td (on) 1.2 0.8 0.4 0 1 10 1 100 ID , DRAIN CURRENT (AMPS) VGS = 0 V TJ = 25°C 1.6 100 0.4 0.5 0.6 0.7 0.8 1 –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current VGS = 8 V SINGLE PULSE TC = 25°C di/dt IS 10 100 s trr 1 ms ta 1 tb TIME 10 ms 0.25 IS tp 0.1 0.01 0.9 RG, GATE RESISTANCE (OHMS) IS RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 dc 10 100 Figure 12. Diode Reverse Recovery Waveform VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 NTTD1P02R2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (°C/W) 1000 100 10 D = 0.5 0.2 0.1 0.05 P(pk) 0.02 0.01 t1 1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RθJC(t) 0.1 1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 t, TIME (s) Figure 13. Thermal Response INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self–align when subjected to a solder reflow process. 0.041 1.04 0.208 5.28 0.126 3.20 0.015 0.38 0.0256 0.65 inches mm http://onsemi.com 5 NTTD1P02R2 SOLDERING PRECAUTIONS • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 RAMP" 200°C 150°C STEP 2 STEP 3 VENT HEATING SOAK" ZONES 2 & 5 RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 SPIKE" SOAK" 170°C 150°C 100°C 140°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile. http://onsemi.com 6 STEP 7 COOLING 205° TO 219°C PEAK AT SOLDER JOINT 160°C 100°C 50°C STEP 6 VENT NTTD1P02R2 TAPE & REEL INFORMATION Micro8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A–A 5.40 (.212) 5.20 (.205) SECTION B–B NOTES: 1. CONFORMS TO EIA–481–1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. 14.4 (.57) 12.4 (.49) NOTE 4 NOTES: 1. CONFORMS TO EIA–481–1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 7 NTTD1P02R2 PACKAGE DIMENSIONS Micro8 CASE 846A–02 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. –A– –B– K PIN 1 ID G D 8 PL 0.08 (0.003) –T– M T B S A S SEATING PLANE 0.038 (0.0015) C H L J DIM A B C D G H J K L STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 --1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 --0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. 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