PHB95N03LTA TrenchMOS™ logic level FET Rev. 01 — 27 August 2002 Product data M3D166 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS™ technology. Product availability: PHB95N03LTA in SOT404 (D2-PAK). 2. Features ■ Low on-state resistance ■ Fast switching. 3. Applications ■ High frequency computer motherboard DC to DC converters. 4. Pinning information Table 1: Pinning - SOT404 simplified outline and symbol Pin Description 1 gate (g) 2 drain (d) 3 source (s) mb mounting base, connected to drain (d) Simplified outline Symbol mb [1] d g 2 1 MBB076 3 MBK116 SOT404 (D2-PAK) [1] It is not possible to make connection to pin 2 of the SOT404 package. s PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 5. Quick reference data Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit VDS drain-source voltage (DC) 25 ≤ Tj ≤ 175 °C - 25 V ID drain current (DC) Tmb = 25 °C; VGS = 5 V - 75 A Ptot total power dissipation Tmb = 25 °C - 125 W Tj junction temperature - 175 °C RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 25 °C 4.8 6 mΩ VGS = 5 V; ID = 25 A; Tj = 25 °C 7.5 9 mΩ Min Max Unit 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDS drain-source voltage (DC) 25 ≤ Tj ≤ 175 °C - 25 V VDGR drain-gate voltage (DC) 25 ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 25 V ID drain current (DC) Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 - 75 A Tmb = 100 °C; VGS = 5 V; Figure 2 - 61 A VGS gate-source voltage - ±20 V IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 240 A Ptot total power dissipation Tmb = 25 °C; Figure 1 - 125 W Tstg storage temperature −55 +175 °C Tj junction temperature −55 +175 °C Source-drain diode IS source (diode forward) current (DC) Tmb = 25 °C - 75 A ISM peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs - 240 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy unclamped inductive load; ID = 75 A; tAL = 0.1 ms; VDD = 15 V; RGS = 50 Ω; VGS = 5V; starting Tj = 25 °C; - 120 mJ IDS(AL)S unclamped inductive load; VDD = 15 V; RGS = 50 Ω; VGS = 5V; starting Tj = 25 °C - 75 A non-repetitive drain-source avalanche current © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Product data Rev. 01 — 27 August 2002 2 of 12 PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 03aa16 120 03ad94 120 Pder Ider (%) (%) 80 80 40 40 0 0 50 100 0 150 200 Tmb (°C) 0 P tot P der = ---------------------- × 100% P ° 50 100 150 200 Tmb (°C) ID I der = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 03ad77 103 ID (A) Limit RDSon = VDS / ID tp = 10 µs 100 µs 102 1 ms DC 10 ms 10 100 ms 1 1 102 10 VDS (V) Tmb = 25 °C; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Product data Rev. 01 — 27 August 2002 3 of 12 PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 7. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Figure 4 - - 1.2 K/W Rth(j-a) thermal resistance from junction to ambient - 50 - K/W minimum footprint; mounted on a PCB 7.1 Transient thermal impedance 03ad76 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 10-1 0.1 0.05 0.02 δ= P 10-2 tp T single pulse t tp T 10-3 10-5 10-4 10-3 10-2 10-1 1 10 tp (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Product data Rev. 01 — 27 August 2002 4 of 12 PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 8. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tj = 25 °C 25 - - V Tj = −55 °C 22 - - V Tj = 25 °C 1 1.5 2 V Tj = 175 °C 0.5 - - V Tj = −55 °C - - 2.3 V - 0.05 10 µA Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) IDSS gate-source threshold voltage drain-source leakage current ID = 0.25 mA; VGS = 0 V ID = 1 mA; VDS = VGS; Figure 9 VDS = 25 V; VGS = 0 V Tj = 25 °C Tj = 175 °C - - 500 µA - 10 100 nA Tj = 25 °C - 7.5 9 mΩ Tj = 175 °C - 13 15.5 mΩ - 4.8 6 mΩ - 43 - nC - 12 - nC - 16 - nC - 2200 - pF IGSS gate-source leakage current VGS = ±5 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 5 V; ID = 25 A; Figure 7 and 8 VGS = 10 V; ID = 25 A; Tj = 25 °C Dynamic characteristics Qg(tot) total gate charge Qgs gate-source charge Qgd gate-drain (Miller) charge Ciss input capacitance ID = 50 A; VDD = 12 V; VGS = 4.5 V; Figure 13 VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 Coss output capacitance - 770 - pF Crss reverse transfer capacitance - 500 - pF td(on) turn-on delay time - 10 20 ns tr rise time - 30 50 ns td(off) turn-off delay time - 110 140 ns tf fall time - 80 100 ns - 0.85 1.2 V - 0.9 - V VDD = 15 V; ID = 15 A; VGS = 10 V; RG = 6 Ω; resistive load Source-drain diode VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12 IS = 40 A; VGS = 0 V © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Product data Rev. 01 — 27 August 2002 5 of 12 PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 03ad78 80 10 V 5 V ID (A) 3.5 V 03ad80 80 Tj = 25 °C VDS > ID x RDSon ID (A) 60 60 40 40 3V 20 20 175 °C Tj = 25 °C VGS = 2.5 V 0 0 0 0.5 1 1.5 VDS (V) 2 Tj = 25 °C 0 2 3 VGS (V) 4 Tj = 25 °C and 175 °C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 03ad79 0.05 2.5 V RDSon 1 Tj = 25 °C VGS = 3 V 03ad57 2 a (Ω) 0.04 1.5 0.03 1 0.02 3.5 V 0.5 0.01 5V 10 V 0 0 0 20 40 60 ID (A) 80 Tj = 25 °C -60 60 120 Tj (°C) 180 R DSon a = --------------------------R DSon ( 25 °C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Product data 0 Rev. 01 — 27 August 2002 6 of 12 PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 03aa33 2.5 max ID (A) 10-2 typ 10-3 VGS(th) (V) 2 1.5 03aa36 10-1 min min 1 10-5 0 10-6 0 60 max 10-4 0.5 -60 typ 120 Tj (°C) 180 0 1 2 VGS (V) 3 Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 03ad83 104 C (pF) Ciss 103 Coss Crss 102 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Product data Rev. 01 — 27 August 2002 7 of 12 PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 03ad82 80 IS (A) 03ad84 10 VGS = 0 V VGS Tj = 25 °C (V) 8 ID = 50 A 60 VDD = 6 V 12 V 6 24 V 40 4 20 175 °C 2 Tj = 25 °C 0 0 0 0.3 0.6 0.9 1.2 VSD (V) Tj = 25 °C and 175 °C; VGS = 0 V 0 60 QG (nC) 90 ID = 50 A; VDD = 6 V, 12 V and 24 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Product data 30 Rev. 01 — 27 August 2002 8 of 12 PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 9. Package outline Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-06-25 01-02-12 SOT404 Fig 14. SOT404 (D2-PAK) © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Product data Rev. 01 — 27 August 2002 9 of 12 PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 10. Revision history Table 6: Revision history Rev Date 01 20020827 CPCN - Description Product specification; initial version © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Product data Rev. 01 — 27 August 2002 10 of 12 PHB95N03LTA Philips Semiconductors TrenchMOS™ logic level FET 11. Data sheet status Data sheet status[1] Product status[2] Definition Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 12. Definitions 13. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 14. Trademarks TrenchMOS - is a trademark of Koninklijke Philips Electronics N.V. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10027 Rev. 01 — 27 August 2002 11 of 12 Philips Semiconductors PHB95N03LTA TrenchMOS™ logic level FET Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 27 August 2002 Document order number: 9397 750 10027