PI74AVC+16823 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs Product Features Product Description • PI74AVC+16823 is designed for low voltage operation, VCC = 1.65V to 3.6V Pericom Semiconductor’s PI74AVC+ series of logic circuits are produced using the Company’s advanced submicron CMOS technology, achieving industry leading speed. The 18-bit PI74AVC+16823 bus-interface flip-flop is designed for 1.65V to 3.6V VCC operation. It features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. • True ±24mA Balanced Drive @ 3.3V • IOFF supports partial power-down operation • 3.6V I/O Tolerant Inputs and Outputs • All outputs contain a patented DDC (Dynamic DriveControl) circuit that reduces noise without degrading propagation delay. The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the Clock Enable (CLKEN) input LOW, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN HIGH disables the clock buffer, thus latching the outputs. Taking the Clear (CLR) input LOW causes the Q outputs to go LOW independently of the clock. • Industrial operation at –40°C to +85°C • Available Packages: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 173 mil wide plastic TVSOP (K) Logic Block Diagram 1OE 1CLR 2 1 55 CE R C1 1CLK 56 V 1CLKEN A buffered Output Enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load n or drive the bus lines significantly. The highimpedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. 1D1 54 1D 3 The Output Enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 1Q1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 8 2OE 2CLR 28 30 CE R C1 2CLK 29 V 2CLKEN 27 2D1 42 1D 15 2Q1 8 1 PS8489 07/24/00 PI74AVC+16823 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1) Product Pin Description Pin Name OE CLR CLKEN CLK Dx Qx GND VCC Description Output Enable Input (Active LOW) Clear Input (Active LOW) Clock Enable Input (Active LOW) Clock Input (Active HIGH) Data Inputs 3-State Outputs Ground Power GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2OE 2CLR 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 56-Pin 46 12 A, K 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 22 23 24 25 26 27 28 36 35 34 33 32 31 30 29 CLR L L L L L H L H H H H X X L L L H X Note: 1. H = L = X = Z = ↑ = Product Pin Configuration 1CLR 1OE 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 OE Inputs CLKEN CLK D Output Q X ↑ ↑ L X X X H L X X X L H L Q0 Q0 Z High Signal Level Low Signal Level Irrelevant High Impedance LOW-to-HIGH Transition 1CLK 1CLKEN 1D1 GND 1D2 1D3 VCC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8 GND 2D9 2CLKEN 2CLK 2 PS8489 07/24/00 PI74AVC+16823 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC .................................................................. –0.5V to +4.6V Input voltage range, VI ........................................................................... –0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ..................................... –0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ............................................................. –0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ........................................................... –50mA Output clamp current, IOK (VO <0) ..................................................... –50mA Continuous output current, IO ............................................................................. ±50mA Continuous current through each VCC or GND ................................. ±100mA Package thermal impedance, θ JA(3): package A .................................. 64°C/W package K ................................... 48°C/W Storage Temperature range, Tstg ........................................ –65°C to 150°C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions(1) VCC Supply Voltage M in. M ax. Operating 1.65 3.6 Data retention only 1.2 VCC = 1.2V VIH High- level Input Voltage VCC VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V 0.65 x VCC 1.7 2 VCC = 1.2V Input Voltage VO Output Voltage IOH High- level output current Low- level output current ∆t∆v Input transition rise or fall rate TA 0.35 x VCC Low- level Input Voltage VI IOL V Gnd VCC = 1.65V to 1.95V VIL Units VCC = 2.3V to 2.7V 0.7 VCC = 3V to 3.6V 0.8 0 3.6 Active State 0 VCC 3- State 0 3.6 VCC = 1.65V to 1.95V –6 VCC = 2.3V to 2.7V – 12 VCC = 3V to 3.6V – 24 mA VCC = 1.65V to 1.95V 6 VCC = 2.3V to 2.7V 12 VCC = 3V to 3.6V 24 VCC = 1.65V to 3.6V 5 ns/V 85 °C Operating free- air temperature –40 Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation. 3 PS8489 07/24/00 PI74AVC+16823 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = –40°C +85°C) Parame te rs VO H VO L II Control Inputs IO F F IO Z IC C Te s t Conditions (1) IO H = –100µA VIH = 1.07V IO H = –6mA IO H = –12mA VIH = 1.7V IO H = –24mA VIH = 2V IO L = 100µA IO L = 6mA VIH = 0.57V VIH = 0.7V IO L = 12mA VIH = 0.8V IO L = 24mA VI = VC C or GND VI or VO = 3.6V VI = VC C or GND VO = VC C or GND IO = 0 Control Inputs CI VI = VC C or GND Data Inputs CO Outputs VO = VC C or GND VCC M in. 1.65V to 3.6V 1.65V 2.3V 3V 1.65V to 3.6V 1.65V 2.3V 3V 3.6V 0 3.6V 3.6V 2.5V 3.3V 2.5V 3.3V 2.5V 3.3V VC C –0.2V 1.2 1.75 2.0 Typ. M a x. Units V 0.2 0.45 0.55 0.8 ±2.5 ±10 ±10 40 µA 4 4 6 6 8 8 pF Note: Typical values are measured at TA = 25°C. 4 PS8489 07/24/00 PI74AVC+16823 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted, see Figures 1 thru 4) VCC = 1.2V VCC = 1.5V ±0.1V VCC = 1.8V ±0.15V VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V M in M in M in M in M ax M in M ax 180 18 0 M ax M ax M ax fclock Clock Fre que ncy tw Pulse duration tsu Setup time th Hold time 150 CLR Low 3.4 3.0 3.0 CLK high or low 3.4 3.0 3.0 CLR Low 0.8 0.1 0.6 Data Low 0.8 1.0 1. 2 Data High 1. 2 1.0 0.8 CLKEΝ Low 2.0 1.6 1.2 Data Low 0.4 0.4 0.4 Data High 0.6 0.6 0.6 CLKEN Low 0.4 0.4 0.4 Units MHz ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted, see Figures 1 thru 4) Parame te r From (Input) To (Output) VCC = 1.2V VCC = 1.5V ±0.1V VCC = 1.8V ±0.15V VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V M in M in M in M in M in M ax M ax 150 fmax CLK tpd M ax CLR Q ten M ax 180 Units M ax 180 MHz 4.0 2.7 2.3 3.7 2.8 2.4 3.9 2.7 2.3 3.5 2.5 2.7 ns OE tdis Operating Characteristics, TA= 25°C Parame te rs Cpd Power Dissipation Capacitance Te s t Conditions Outputs Enabled Outputs Disabled CL = 0pF, f = 10 MHz 5 VCC = 1.8V ±0.15V VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V Typical Typical Typical 25 30 37 10 12 18 Units pF PS8489 07/24/00 PI74AVC+16823 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 1.2V AND 1.5V ± 0.1V S1 2Ω From Output Under Test CL = 15pF 2xVCC Open GND 2Ω (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V VOL tPHZ VCC/2 VOH –0.1V VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 6 PS8489 07/24/00 PI74AVC+16823 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 1.8V ±0.15V S1 12ΩkΩ From Output Under Test CL = 30 15pF 2xVCC Open GND 2Ω 1 kΩ (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V 0.15V VOL tPHZ VCC/2 VOH –0.1V 0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 2. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 7 PS8489 07/24/00 PI74AVC+16823 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 2.5V ± 0.2V S1 500Ω 2Ω From Output Under Test CL =30 15pF 2xVCC Open GND 500Ω 2Ω (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.15V VOL tPHZ VCC/2 VOH –0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 3. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 8 PS8489 07/24/00 PI74AVC+16823 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 3.3V ± 0.3V S1 500Ω 2Ω From Output Under Test CL = 30 15pF 2xVCC Open GND 500Ω 2Ω (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V 0.3V VOL tPHZ VCC/2 VOH –0.1V 0.3V VOH 0V Voltage Waveforms Enable and Disable Times Figure 4. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 9 PS8489 07/24/00 PI74AVC+16823 2.5V 18-Bit Bus Interface Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical - 56-pin TSSOP (A-package) 56 .236 6.0 .244 6.2 1 .547 13.9 .555 14.1 1.20 SEATING PLANE .047 Max. .004 0.09 .008 0.20 .0197 BSC 0.50 .007 .011 0.17 0.27 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 0.45 .018 0.75 .030 .002 .006 0.05 0.15 .319 BSC 8.1 Packaging Mechanical - 56-pin TVSOP (K-package) 56 4.30 4.50 .169 .177 0.09 0.20 .0035 .008 1 .441 .449 .031 .041 0.80 1.05 11.20 11.40 0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE .016 BSC 0.40 X.XX X.XX .005 .009 0.13 0.23 .002 .006 0.05 0.15 .047 1.20 Max. DENOTES DIMENSIONS IN MILLIMETERS Orde ring Info. De s cription PI74AVC+16823A 56- pin, 240- mil wide plastic TSSOP PI74AVC+16823K 56- pin, 173- mil wide plastic TSSOP Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 10 PS8489 07/24/00