PI74SSTV16859 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 13-Bit to 26-Bit Registered Buffer Product Features Product Description • PI74 SSTV16859 is designed for low-voltage operation, VDD = VDDQ = 2.3V to 2.7V • Supports SSTL_2 Class II specifications on outputs • All Inputs are SSTL_2 Compatible, except RESET which is LVCMOS. • Designed for DDR Memory • Flow-Through Architecture • Packages (Lead-free packages are available): – 64-pin, 240-mil wide plastic TSSOP (A) – 56-contact, Plastic Very Thin Fine Pitch Quad Flat No Lead QFN (ZB) Pericom Semiconductor’s PI74SSTV16859 logic circuit is produced using the Company’s advanced 0.35 micron CMOS technology, achieving industry leading speed. All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. The device operates from a differential clock (CLK and CLK). Data registered at the crossing of CLK going HIGH, and CLK going LOW. The PI74SSTV16859 supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. Logic Block Diagram - TSSOP RESET D1 VREF 48 49 16 51 R V CLK CLK 35 45 CLK D To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power up. Q1A 32 In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of RESET, the register will become active quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock is stable, during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. Q1B TO 12 OTHER CHANNELS Logic Block Diagram - QFN RESET D1 VREF 35 36 7 38 R V CLK CLK 24 32 CLK D Q1A 22 Q1B Pericom’s PI74SSTV16859 is characterized for operation from 0°C to 70°C. Truth Table(1) TO 12 OTHER CHANNELS Inputs Product Pin Description Pin Name De s cription Outputs RESET CLK CLK D Q RESET Reset (Active Low) LVCMOS L Clock Input, Positive Differential Input X or Floating X or Floating L CLK X or Floating CLK Clock Input, Negative Differential Input H ↑ ↓ H H D Data Input, D1- D13 Η ↑ ↓ L L Q Data Output, Q1- Q13 H L or H L or H X Q o( 2 ) GND Ground VDD Core Supply Voltage, 2.5V Nominal VDDQ Output Supply Voltage, 2.5V Nominal VREF Input Reference Voltage, 1.25V Nominal Notes: 1. H L ↑ ↓ X 1 = High Signal Level 2. Output level before the = Low Signal Level indicated steady state = Transition LOW-to-HIGH input conditions were = Transition HIGH-to-LOW established. = Irrelevant or floating PS8508D 05/01/03 PI74SSTV16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 VDDQ GND VDDQ Q13A Q12A Q11A Q10A VDDQ Product Pin Configurations 62 D13 Q10A 4 61 D12 Q7A 1 42 D10 Q9A 5 60 VDD Q6A 2 41 D9 VDDQ 6 59 VDDQ Q5A 3 40 D8 GND 7 58 GND Q4A 4 39 D7 Q8A 8 57 D11 Q3A 5 38 RESET Q7A 9 56 D10 Q2A 6 37 GND Q6A 10 55 D9 Q1A 7 36 CLK Q5A 11 54 GND Q13B 8 35 CLK Q4A 12 53 D8 VDDQ 9 34 VDDQ Q3A 13 52 D7 Q12B 10 33 VDD Q2A 14 51 RESET Q11B 11 32 VREF 12 31 D6 64-Pin A D11 3 VDD GND Q11A D12 VDDQ 63 D13 64 2 Q9A 1 Q12A Q8A Q13A 56 55 54 53 52 51 50 49 48 47 46 45 44 43 56-Pin ZB D4 VDDQ 18 47 VDDQ Q12B 19 46 VDD Q11B 20 45 VREF Q10B 21 44 D6 Q9B 22 43 GND Q8B 23 42 D5 Q7B 41 40 D4 Q6B 24 25 GND 26 39 GND VDDQ Q5B 27 38 VDDQ 28 37 VDD Q4B 29 36 D2 Q3B 30 35 D1 Q2B 31 34 GND Q1B 32 33 VDDQ D3 14 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VDDQ Q8B VDD CLK D2 48 D1 17 VDDQ D5 Q13B Q1B 30 Q2B 13 Q3B Q9B Q4B CLK Q5B GND 49 VDDQ 50 16 Q6B 15 Q1A Q7B GND Q10B Maximum Ratings (Above which the useful life may be D3 impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 3.6V Maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 Ite m Symbol/ Conditions Ratings Units Storage temperature Tstg –65 to 150 °C Supply voltage VDD or VDDQ –0.5 to 3.6 Input voltage(1,2) VI –0.5 to VDD +0.5 Output voltage(1,2) VO –0.5 to VDDQ +0.5 Input clamp current IIK, VI <0 or VI >VDD ± 50 Output clamp current IOK, VO <0 or VO >VDDQ ± 50 Continuous output current IO, VO = 0 to VDDQ ± 50 VDD, VDDQ or GND current/pin IDD, IDDQ or IGND ±100 Package Thermal Impedance(3) θJA 55 V mA °C/W PS8508D 05/01/03 PI74SSTV16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Recommended Operating Conditions(4) Parame te rs M in. Nom. M ax. Supply Voltage 2.3 2.5 2.7 VDDQ I/O Supply Voltage 2.3 2.5 2.7 VREF Reference Voltage VREF = 0.5X VDDQ 1.15 1.25 1.35 VTT Termination Voltage VREF –0.04 VREF VREF +0.04 VDD VI De s cription Input Voltage 0 Units VDD VIH AC High - Level Input Voltage VREF +310mV VIL AC Low - Level Input Voltage VIH DC High - Level Input Voltage VIL DC Low - Level Input Voltage VIH High - Level Input Voltage VIL Low - Level Input Voltage VICR Common- mode input range VID Differential Input Voltage IOH High- Level Output Current –2 0 IOL Low- Level Output Current 20 TA Operating Free- Air Temperature VREF – 310mV Data Inputs V VREF +150mV VREF –150mV 1.7 RESET 0.7 0.97 1.53 CLK, CLK 360 0 mA 70 ºC Note: 4. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW. 3 PS8508D 05/01/03 PI74SSTV16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = 0°C to +70°C, VDD = 2.5V ± 200mV, VDDQ = 2.5V ± 200mV) Pa ra me te rs Te s t Co nditio ns VIK II = – 1 8 mA VOH IOH = – 1 0 0 µA VOL VDD M in. Ty p. 2.3V M ax. Units – 1.2 V 2 . 3 V- 2 . 7 V VDD– 0 . 2 IOH = – 1 6 mA 2.3V 1.95 IOL = 1 0 0 µA 2 . 3 V- 2 . 7 V 0.2 IOH = 1 6 mA 2.3V 0.35 II All Inp uts VI = VDD o r GN D 2.7V ±5 IDD S tand b y (S tatic) RES ET = GN D 2.7V 10 O p erating (S tatic) RES ET = VDD VI = VIH(AC) o r VIL(AC) Dynamic O p erating clo ck o nly RES ET = VDD VI = VIH(AC) o r VIL(AC) C LK and C LK switching 5 0 % d uty cycle 30 µA/ clo ck MHz Dynamic O p erating per each d ata inp ut RES ET = VDD VI = VIH(AC) o r VIL(AC) C LK and C LK switching 5 0 % d uty cycle. O ne d ata inp ut switching at half clo ck freq uency, 5 0 % d uty cycle 10 µA/ clo ck MHz d a ta inp ut rOH O utp ut High IO = – 2 0 mA rOL O utp ut Lo w IO = 2 0 mA rO( ) rOH- rOLeach sep erate b it IO = 2 0 mA, TA = 2 5 º C CI Data Inp uts VI = VREF± 3 5 0 mV C LK and C LK VICR= 1 . 2 5 V, VI(PP) = 3 6 0 mV RES ET VI = VDDo r GN D IDDD ∆ 40 2 . 3 to 2 . 7 V 7 20 2.5V µA mA o hm 6 2.5 3 3.5 pF 3 4 PS8508D 05/01/03 PI74SSTV16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) VDD = 2.5V ±0.2V M in. Clock frequency fclock 200 tW Pulse Duration, CLK, CLK high or low tact Differential Inputs active time, data inputs must be low after RESET high. tinact Differential Inputs inactive time, data and clock inputs must be held at valid levels (not floating) after RESET Low. Setup time, fast slew rate(5,7) tsu Setup time, slow slew rate(6,7) Hold time, fast slew rate(5,7) th Hold time, slow slew rate(6,7) Units M a x. MHz 2.5 22 ns 0.75 Data before CLK↑, CLK↓ 0.9 0.75 Data after CLK↑, CLK↓ 0.9 Notes: 5. For data signal input slew rate ≥1V/ns. 6. For data signal input slew rate ≥0.5V/ns and <1V/ns. 7. CLK, CLK signals input slew rates are ≥1V/ns. Switching characteristics Over recommended operating free-air temperature range, unless otherwise noted. (See test circuits and switching waveforms). VDD = 2.5V ±0.2V Parame te r From (Input) M in. To (Output) Typ. M ax. 200 fmax tpd CLK, CLK Q tphl RESET Q 1.1 Units MHz 2.8 ns 5.0 5 PS8508D 05/01/03 PI74SSTV16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Circuit and Switching Waveforms VTT LVCMOS RESET Input VDD VDD/2 RL = 50Ω From Output Under Test 0V t inact tact IDD(9) TEST POINT CL = 30pF(8) IDDH 90% 10% Load Circuit IDDL Voltage and Current Waveforms Input Active and Inactive Times Timing Input VICR tw VIH Input VREF VREF Output VIL VICR tsu VREF t PLH t PHL VTT VTT VOH Voltage Waveforms - Propagation Delay Times LVCMOS RESET Input VI(PP) VIH VDD/2 VIL t PHL th VIH Input VI(PP) VOL Voltage Waveforms - Pulse Duration Timing Input VICR Output VREF VOH VTT VIL VOL Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Setup and Hold Times Parameter Measurement Information (VDD = 2.5V ±0.2V) Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 10. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 ohms. Input slew rate = 1V/ns ±20% (unless otherwise specified). 11. The outputs are measured one at a time with one transition per measurement. 12. VTT = VREF = VDDQ/2 13. VIH = VREF + 350mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input. 14. VIL = VREF + 350mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input. 15. tPLH and tPHL are the same as tpd. 6 PS8508D 05/01/03 PI74SSTV16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 64-Pin TSSOP (A) Package 64 .236 .244 1 .665 .673 6.0 6.2 16.9 17.1 0.45 .018 0.75 .030 SEATING PLANE 1.20 .047 Max. .004 .008 0.09 0.20 .319 BSC 8.1 .004 0.10 .0197 BSC 0.50 .002 .006 .007 0.17 .011 0.27 0.05 0.15 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS .311 .319 7.90 8.10 0.25 C A 56-Contact QFN (ZB) Package .033 MAX 0.84 .012 .019 0.30 0.50 .007 .012 0.18 0.30 .019 BSE 0.50 .008 REF 0.20 0 .0015 0.00 0.04 O 0.10 M C A B R 0.25 x 3 .311 .319 7.90 8.10 .199 .211 5.05 5.35 0.25 Chamfer .171 .183 4.35 4.65 0.08 C 0.25 C B X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Notes: 1. Controlling dimensions in millimeters 2. Ref: JEDEC MO-220 variation VLLD-2 7 PS8508D 05/01/03 PI74SSTV16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Ordering Information Orde ring Code Package Type Te mpe rature Range PI74SSTV16859A 64- Pin TSSOP PI74SSTV16859AE Pb- free, 64- Pin TSSOP PI74SSTV16859ZB 56- contact QFN PI74SSTV16859ZBE Pb- free, 56- contact QFN 0°C to 70°C Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 8 PS8508D 05/01/03