PI7C7100 3-Port PCI Bridge Pericom Semiconductor Corporation The Complete Interface Solution 2380 Bering Drive, San Jose, California 95131 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: (408) 435-1100, E-mail: [email protected] Internet: http://www.pericom.com © 2000 Pericom Semiconductor Corporation 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 LIFE SUPPORT POLICY Pericom Semiconductor Corporations products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1.Life support devices or systems are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. ii 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 Table of Contents 1. 2. 3. 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 4. 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.8 4.8.1 4.8.2 4.8.3 4.8.4 Introduction/Product Features ............................................................................................................................... 1 PI7C7100 Block Diagram ...................................................................................................................................... 3 Signal Definitions ................................................................................................................................................... 4 Signal Types ............................................................................................................................................................ 4 Signals ...................................................................................................................................................................... 4 Primary Bus Interface Signals .................................................................................................................................. 4 Secondary Bus Interface Signals ............................................................................................................................. 6 Clock Signals ............................................................................................................................................................ 8 Miscellaneous Signals ............................................................................................................................................. 8 JTAG Boundary Scan Signals .................................................................................................................................. 9 Power and Ground .................................................................................................................................................... 9 PCI Bus Operation ................................................................................................................................................ 10 Types of Transactions ........................................................................................................................................... 10 Single Address Phase ............................................................................................................................................ 11 Device Select (DEVSEL#) Generation .................................................................................................................... 11 Data Phase ............................................................................................................................................................. 11 Write Transactions ................................................................................................................................................ 11 Posted Write Transactions .................................................................................................................................... 11 Memory Write and Invalidate Transactions .......................................................................................................... 12 Delayed Write Transactions .................................................................................................................................. 12 Write Transaction Address Boundaries ................................................................................................................ 13 Buffering Multiple Write Transactions .................................................................................................................. 13 Fast Back-to-Back Write Transactions .................................................................................................................. 13 Read Transactions ................................................................................................................................................. 14 Prefetchable Read Transactions ............................................................................................................................ 14 Non-prefetchable Read Transactions .................................................................................................................... 14 Read Pre-fetch Address Boundaries ...................................................................................................................... 14 Delayed Read Requests ......................................................................................................................................... 15 Delayed Read Completion with Target .................................................................................................................. 15 Delayed Read Completion on Initiator Bus ........................................................................................................... 15 Configuration Transactions ................................................................................................................................... 16 Type 0 Access to PI7C7100 ................................................................................................................................... 16 Type 1 to Type 0 Conversion ................................................................................................................................ 17 Type 1 to Type 1 Forwarding ................................................................................................................................ 18 Special Cycles ........................................................................................................................................................ 19 Transaction Termination ........................................................................................................................................ 19 Master Termination Initiated by PI7C7100 ............................................................................................................ 20 Master Abort Received by PI7C7100 ..................................................................................................................... 20 Target Termination Received by PI7C7100 ............................................................................................................ 21 Target Termination Initiated by PI7C7100 ............................................................................................................. 23 iii 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 5. 5.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.4 5.4.1 5.4.2 6. 6.1 6.2 6.3 6.4 7. 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.4 8. 8.1 8.2 8.3 9. 9.1 9.2 9.2.1 9.2.2 9.2.3 10. 10.1 10.2 11. 11.1 11.2 11.3 12. 12.1 12.2 13. 13.1 13.2 Address Decoding .................................................................................................................................................. 25 Address Ranges ..................................................................................................................................................... 25 I/O Address Decoding ........................................................................................................................................... 25 I/O Base and Limit Address Registers ................................................................................................................... 25 ISA Mode ............................................................................................................................................................... 26 Memory Address Decoding ................................................................................................................................... 26 Memory-Mapped I/O Base and Limit Address Registers ...................................................................................... 26 Prefetchable Memory Base and Limit Address Registers ...................................................................................... 27 VGA Support .......................................................................................................................................................... 28 VGA Mode ............................................................................................................................................................. 28 VGA Snoop Mode .................................................................................................................................................. 28 Transaction Ordering ........................................................................................................................................... 29 Transactions Governed by Ordering Rules ........................................................................................................... 29 General Ordering Guidelines .................................................................................................................................. 29 Ordering Rules ....................................................................................................................................................... 30 Data Synchronization ............................................................................................................................................. 31 Error Handling ...................................................................................................................................................... 32 Address Parity Errors ............................................................................................................................................. 32 Data Parity Errors ................................................................................................................................................... 32 Configuration Write Transactions to Configuration Space ................................................................................... 32 Read Transactions ................................................................................................................................................. 33 Delayed Write Transactions .................................................................................................................................. 33 Posted Write Transactions .................................................................................................................................... 35 Data Parity Error Reporting Summary .................................................................................................................... 36 System Error (SERR#) Reporting ........................................................................................................................... 42 Exclusive Access ................................................................................................................................................... 43 Concurrent Locks ................................................................................................................................................... 43 Acquiring Exclusive Access across PI7C7100 ....................................................................................................... 43 Ending Exclusive Access ....................................................................................................................................... 44 PCI Bus Arbitration .............................................................................................................................................. 45 Primary PCI Bus Arbitration ................................................................................................................................... 45 Secondary PCI Bus Arbitration ............................................................................................................................. 45 Secondary Bus Arbitration Using the Internal Arbiter .......................................................................................... 45 Secondary Bus Arbitration Using an External Arbiter ........................................................................................... 46 Bus Parking ............................................................................................................................................................ 46 Clocks .................................................................................................................................................................... 47 Primary Clock Inputs .............................................................................................................................................. 47 Secondary Clock Outputs ...................................................................................................................................... 47 Reset ...................................................................................................................................................................... 48 Primary Interface Reset .......................................................................................................................................... 48 Secondary Interface Reset ..................................................................................................................................... 48 Chip Reset .............................................................................................................................................................. 48 Supported Commands ............................................................................................................................................ 49 Primary Interface .................................................................................................................................................... 49 Secondary Interface ............................................................................................................................................... 51 Configuration Registers ....................................................................................................................................... 52 Config Register 1 .................................................................................................................................................... 52 Config Register 2 .................................................................................................................................................... 53 iv 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.2.6 13.2.7 13.2.8 13.2.9 13.2.10 13.2.11 13.2.12 13.2.13 13.2.14 13.2.15 13.2.16 13.2.17 13.2.18 13.2.19 13.2.20 13.2.21 13.2.22 13.2.23 13.2.24 13.2.25 13.2.26 13.2.27 13.2.28 13.2.29 13.2.30 13.2.31 13.2.32 13.2.33 13.2.34 13.2.35 13.2.36 13.2.37 13.2.38 13.2.39 13.2.40 13.2.41 13.2.42 13.2.43 13.2.44 13.2.45 13.2.46 13.2.47 13.2.48 13.2.49 13.2.50 Config Register 1 or 2:Vendor ID Register (read only, bit 15-0; offset 00h) .......................................................... 54 Config Register 1: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 54 Config Register 2: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 54 Config Register 1: Command Register (bit 15-0; offset 04h) .................................................................................. 54 Config Register 2: Command Register (bit 15-0; offset 04h) .................................................................................. 55 Config Register 1 or 2: Status Register (for primary bus, bit 31-16; offset 04h) ..................................................... 56 Config Register 1 or 2: Revision ID Register (read only, bit 7-0; offset 08h) ......................................................... 57 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h) ........................................................ 57 Config Register 1 or 2: Cache Line Size Register (read/write, bit 7-0; offset 0Ch) ................................................. 57 Config Register 1: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) ............................................ 57 Config Register 2: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) ............................................ 57 Config Register 1: Header Type Register (read only, bit 23-16; offset 0Ch) .......................................................... 57 Config Register 2: Header Type Register (read only, bit 23-16; offset 0Ch) .......................................................... 57 Config Register 1: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 57 Config Register 2: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 57 Config Register 1 or 2: Secondary Bus Number Register (read/write, bit 15-8; offset 18h) ................................... 57 Config Register 1 or 2: Subordinate Bus Number Register (read/write, bit 23-16; offset 18h) ............................... 57 Config Register 1 or 2: Secondary Latency Timer (read/write, bit 31-24; offset 18h) ............................................ 57 Config Register 1 or 2: I/O Base Register (read/write, bit 7-0; offset 1Ch) ............................................................ 57 Config Register 1 or 2: I/O Limit Register (read/write, bit 15-8; offset 1Ch) ........................................................... 57 Config Register 1 or 2: Secondary Status Register (bit 31-16; offset 1Ch) ............................................................ 58 Config Register 1 or 2: Memory Base Register (read/write, bit 15-0; offset 20h) ................................................... 59 Config Register 1 or 2: Memory Limit Register (read/write, bit 31:16; offset 20h) ................................................. 59 Config Register 1 or 2: Prefetchable Memory Base Register (read/write, bit 15-0;offset 24h) ............................... 59 Config Register 1 or 2: Prefetchable Memory Limit Register (read/write, bit 31-16; offset 24h) ............................ 59 Config Register 1 or 2: I/O Base Address Upper 16 Bits Register (read/write, bit 15-0; offset 30h) ...................... 59 Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register (read/write, bit 31-16; offset 30h) .................... 59 Config Register 1 or 2: Subsystem Vendor ID (read/write, bit 15-0; offset 34h) .................................................... 59 Config Register 1 or 2: Subsystem ID (read/write, bit 31-16; offset 34h) ............................................................... 59 Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch) ..................................................... 59 Config Register 1 or 2: Bridge Control Register (bit 31-16; offset 3Ch) ................................................................. 60 Config Register 1 or 2: Diagnostic/Chip Control Register (bit 15-0; offset 40h) .................................................... 61 Config Register 1 or 2: Arbiter Control Register (bit 31-16; offset 40h) ................................................................. 61 Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 62 Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 62 Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) .................... 62 Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) .................... 62 Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h) ...................................................... 62 Config Register 1: Secondary Clock Control Register (bit 15-0; offset 68h) .......................................................... 63 Config Register 2: Secondary Clock Control Register (bit 15-0; offset 68h) .......................................................... 63 Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h) .............................. 64 Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h) ............................. 64 Config Register 1: Port Option Register (bit 15-0; offset 74h) ............................................................................... 64 Config Register 2: Port Option Register (bit 15-0; offset 74h) ............................................................................... 65 Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h) ................................ 66 Config Register 1 or 2: Retry Counter Register (read/write, bit 31-0; offset 78h) .................................................. 66 Config Register 1 or 2: Sampling Timer Register (read/write, bit 31-0; offset 7Ch) ................................................ 66 Config Register 1 or 2: Successful I/O Read Count Register (read/write, bit 31-0; offset 80h) ............................. 66 Config Register 1 or 2: Successful I/O Write Count Register (read/write, bit 31-0; offset 84h) ............................. 66 Config Register 1 or 2: Successful Memory Read Count Register (read/write, bit 31-0; offset 88h) ..................... 66 v 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 13.2.51 13.2.52 13.2.53 13.2.54 13.2.55 14. 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 15. 15.1 15.1.1 15.1.2 15.2 15.3 15.4 15.5 15.6 16. 16.1 16.2 16.3 16.4 17. 17.1 Config Register 1 or 2: Successful Memory Write Count Register (read/write, bit 31-0; offset 8Ch) .................... 66 Config Register 1: Primary Successful I/O Read Count Register (read/write, bit 31-0; offset 90h) ....................... 66 Config Register 1: Primary Successful I/O Write Count Register (read/write, bit 31-0; offset 94h) ....................... 66 Config Register 1: Primary Successful Memory Read Count Register (read/write, bit 31-0; offset 98h) ............... 66 Config Register 1: Primary Successful Memory Write Count Register (read/write, bit 31-0; offset 9Ch) .............. 66 Bridge Behavior .................................................................................................................................................... 67 Bridge Actions for Various Cycle Types ............................................................................................................... 67 Transaction Ordering ............................................................................................................................................. 67 Abnormal Termination (Initiated by Bridge Master) ............................................................................................. 68 Master Abort ......................................................................................................................................................... 68 Parity and Error Reporting ..................................................................................................................................... 68 Reporting Parity Errors ........................................................................................................................................... 68 Secondary IDSEL mapping .................................................................................................................................... 68 IEEE 1149.1 Compatible JTAG Controller ........................................................................................................... 69 Boundary Scan Architecture ................................................................................................................................. 69 TAP Pins ................................................................................................................................................................ 69 Instruction Register ............................................................................................................................................... 69 Boundary Scan Instruction Set .............................................................................................................................. 70 TAP Test Data Registers ....................................................................................................................................... 70 Bypass Register ..................................................................................................................................................... 71 Boundary-Scan Register ......................................................................................................................................... 71 TAP Controller ....................................................................................................................................................... 71 Electrical and Timing Specifications .................................................................................................................... 76 Maximum Ratings ................................................................................................................................................... 76 3.3V DC Specifications ........................................................................................................................................... 76 3.3V AC Specifications ........................................................................................................................................... 77 Primary and Secondary buses at 33 MHz clock timing .......................................................................................... 77 256-Pin PBGA Package ........................................................................................................................................... 78 Part Number Ordering Information ........................................................................................................................ 78 vi 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 List of Figures 1-1. 1-2. 1-3. 2-1. 9-1. 15-1. 17-1. PI7C7100 on the System Board .................................................................................................................................... 2 PI7C7100 in Redundant Applications .......................................................................................................................... 2 PI7C7100 on Network Switching Hub .......................................................................................................................... 2 PI7C7100 Block Diagram .............................................................................................................................................. 3 Secondary Arbiter Example ....................................................................................................................................... 45 Test Access Port Block Diagram ............................................................................................................................... 69 256-Pin PBGA Package Drawing ................................................................................................................................ 74 List of Tables 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 4-9. 6-1. 7-1. 7-2. 7-3. 7-4. 7-5. 7-6. 7-7. 15-1. 15-2. PCI Transaction ......................................................................................................................................................... 10 Write Transaction Forwarding .................................................................................................................................. 11 Write Transaction Disconnect Address Boundaries ................................................................................................ 13 Read Pre-fetch Address Boundaries ......................................................................................................................... 14 Read Transaction Pre-fetching .................................................................................................................................. 15 Device Number to IDSEL S1_AD or S2_AD Pin Mapping ....................................................................................... 18 Posted Write Target Termination Response ............................................................................................................. 21 Responses to Posted Write Target Termination ....................................................................................................... 22 Responses to Delayed Read Target Termination ...................................................................................................... 22 Summary of Tranaction Ordering .............................................................................................................................. 30 Setting the Primary Interface Detected Parity Error Bit ............................................................................................. 36 Setting the Secondary Interface Detected Parity Error Bit ........................................................................................ 37 Setting the Primary Interface Data Parity Detected Bit .............................................................................................. 37 Setting the Secondary InterfaceData Parity Detected Bit ......................................................................................... 38 Assertion of P_PERR# ............................................................................................................................................... 39 Assertion of S_PERR# ............................................................................................................................................... 40 Assertion of P_SERR# for Data Parity Errors ........................................................................................................... 41 TAP Pins .................................................................................................................................................................... 70 JTAG Boundary Register Order ................................................................................................................................ 72 vii 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Appendix A - Timing Diagrams 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. Configuration Read Transaction ................................................................................................................................. A-3 Configuration Write Transaction ................................................................................................................................A-3 Type 1 to Type 0 Configuration Read Transaction (P → S) ......................................................................................A-3 Type 1 to Type 0 Configuration Write Transaction (P → S) .....................................................................................A-4 Upstream Type 1 to Special Cycle Transaction (S → P) ............................................................................................. A-4 Downstream Type 1 to Special Cycle Transaction (P → S) ........................................................................................ A-5 Downstream Type 1 to Type 1 Configuration Read Transaction (P → S) ..................................................................A-5 Downstream Type 1 to Type 1 Configuration Write Transaction (P → S) .................................................................A-6 Upstream Delayed Burst Memory Read Transaction (S → P) ...................................................................................A-6 Downstream Delayed Burst Memory Read Transaction (P → S) ..............................................................................A-7 Downstream Delayed Memory Read Transaction (P/33MHz → S/33MHz) ............................................................... A-7 Downstream Delayed Memory Read Transaction (S2/33MHz → S1/33MHz) ...........................................................A-8 Downstream Delayed Memory Read Transaction (S1/33MHz → S2/33MHz) ...........................................................A-8 Upstream Delayed Memory Read Transaction (S/33MHz → P/33MHz) ...................................................................A-9 Downstream Posted Memory Write Transaction (P/33MHz → S/33MHz) ................................................................ A-9 Downstream Posted Memory Write Transaction (S2/33MHz → S1/33MHz) ........................................................... A-10 Downstream Posted Memory Write Transaction (S1/33MHz → S2/33MHz) ........................................................... A-10 Upstream Posted Memory Write Transaction (S/33MHz → P/33MHz) ................................................................... A-11 Downstream Flow-Through Posted Memory Write Transaction (P/33MHz →S/33MHz) ........................................ A-11 Downstream Flow-Through Posted Memory Write Transaction (S2/33MHz →S1/33MHz) .................................... A-12 Downstream Flow-Through Posted Memory Write Transaction (S1/33MHz →S2/33MHz) .................................... A-12 Upstream Flow-Through Posted Memory Write Transaction (S/33MHz →P/33MHz) ............................................ A-13 Downstream Delayed I/O Read Transaction (P → S) ............................................................................................... A-13 Downstream Delayed I/O Read Transaction (S2/33MHz → S1/33MHz) .................................................................. A-14 Downstream Delayed I/O Read Transaction (S1/33MHz → S2/33MHz) .................................................................. A-14 Downstream Delayed I/O Read Transaction (S/33MHz → P/33MHz) ...................................................................... A-15 Downstream Delayed I/O Write Transaction (P → S) .............................................................................................. A-15 Downstream Delayed I/O Write Transaction (S2/33MHz → S1/33MHz) ................................................................. A-16 Downstream Delayed I/O Write Transaction (S1/33MHz → S2/33MHz) ................................................................. A-16 Upstream Delayed I/O Write Transaction (S → P) ................................................................................................... A-17 Appendix B - Evaluation Board User's Manual General Information ........................................................................................................................................................... B-3 Frequently Asked Questions ............................................................................................................................................ B-5 Appendix C - Three-Port PCI Bridge Evaluation Board Schematics PCI Chip ............................................................................................................................................................................. C-3 PCI Edge Connector .......................................................................................................................................................... C-4 Secondary 1 PCI Bus ......................................................................................................................................................... C-5 Secondary 2 PCI Bus ......................................................................................................................................................... C-6 Top View ............................................................................................................................................................................ C-7 viii 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 1. Introduction Product Description PI7C7100 is the first triple port PCI-to-PCI Bridge device designed to be fully compliant with the 32-bit, 33MHz implementation of the PCI Local Bus Specification, Revision 2.1. PI7C7100 supports only synchronous bus transactions between devices on the primary 33 MHz bus and the secondary buses operating at 33 MHz. The primary and the secondary buses can also operate in concurrent mode, resulting in added increase in system performance. Concurrent bus operation off-loads and isolates unnecessary traffic from the primary bus; thereby enabling a master and a target device on the same secondary PCI bus to communicate even while the primary bus is busy. Product Features 32-bit Primary & two Secondary Ports run up to 33 MHz All three ports compliant with the PCI Local Bus Specification, Revision 2.1 Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.0. - All I/O and memory commands - Type 1 to Type 0 configuration conversion - Type 1 to Type 1 configuration forwarding - Type 1 configuration-write to special cycle conversion Concurrent primary to secondary bus operation and independent intra-secondary port channel to reduce traffic on the primary port Provides internal arbitration for two sets of eight secondary bus masters - Programmable 2-level priority arbiter - Disable control for use of external arbiter Supports posted write buffers on all directions Three 128 byte FIFOs Enhanced address decoding - 32-bit I/O address range - 32-bit memory-mapped I/O address range - VGA addressing and VGA palette snooping - ISA-aware mode for legacy support in the first 64KB of I/O address range Interrupt Handling - PCI interrupts are routed through an external interrupt concentrator Supports system transaction ordering rules Hot-plug support on secondary buses - 3-State control of output buffers IEEE 1149.1 JTAG interface support 3.3V core; 3.3V PCI I/O interface with 5V I/O Tolerant 256-pin plastic BGA package 1 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 CPU System Memory S1 PCI Bus NB PI7C7100 Slot Slot PCI Device PCI Device S2 PCI Bus Figure 1-1. PI7C7100 on the System Board Master Controller Redundant Controller System Primary PCI Bus System Primary PCI Bus PI7C7100 PI7C7100 S2 S1 S1 S2 S1 PCI Bus S2 PCI Bus Figure 1-2. PI7C7100 in Redundant Application Core Logic CPU PCI Bus 32/33 Fast Ethernet Internal Slot L2 Cache PCI Bus 32/33 PI7C7100 PI7C7100 PI7C7100 I/O Daughter Board to Isolate Traffic Figure 1-3. PI7C7100 on Network Switching Hub 2 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 2. PI7C7100 Block Diagram Configuration Register #1 Transaction Queue #1 Primary PCI Bus Primary Interface Arbiter Secondary Interface A Secondary PCI Bus A Transaction Queue #2 Transaction Queue #3 Configuration Register #2 Secondary Interface B Secondary PCI Bus B Arbiter Figure 2-1. PI7C7100 Block Diagram 3 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 3. Signal Definitions 3.1 Signal Types PTS - PCI 3-state Output POD - PCI Output which either drives LOW (active state) or 3-stated CI - CMOS Input CIU - CMOS Input with weak pull-up CID - CMOS Input with weak pull-down CTO CMOS 3-state Output Note: All I/Os can operate off at 3.3V PI - PCI Input (3.3V, 5V tolerant) PIU - PCI Input (3.3V, 5V tolerant) with weak pull-up PB - PCI 3-state bidirectional (3.3V, 5V tolerant) PO - PCI Output (3.3V) PSTS - PCI Sustained 3-state bidirectional (Active LOW signal which must be driven inactive for one cycle before being 3-stated to ensure HIGH performance on a shared signal line) 3.2 Signals (Note: Signal name that ends with character # is active LOW.) 3.2.1 Primary Bus Interface Signals N ame Pin # Ty pe D escription P_AD [31:0] Y7, W7, Y8, W8, V8, U8, Y9, W9, W10, V10, Y11, V11, U11, Y12, W12, V12, V16, W16, Y16, W17, Y17, U18, W18, Y18, U19, W19, Y19, U20, V20, Y20, T17, R17 PB Primary Address/D ata. Multi plexed address and data bus. Address i s i ndi cated by P_FRAME# asserti on. Wri te data i s stable and vali d when P_IRD Y# i s asserted and read data i s stable and vali d when P_TRD Y# i s asserted. D ata i s transferred on ri si ng clock edges when both P_IRD Y# and P_TRD Y# are asserted. D uri ng bus i dle, PI7C 7100 dri ves P_AD to a vali d logi c level when P_GNT# i s asserted. P_C BE[3:0] V9, U12, U16, V19 PB Primary C ommand/B y te Enables. Multi plexed command fi eld and byte enable fi eld. D uri ng address phase, the i ni ti ator dri ves the transacti on type on these pi ns. After that the i ni ti ator dri ves the byte enables duri ng data phases. D uri ng bus i dle, PI7C 7100 dri ves P_C BE[3:0] to a vali d logi c level when P_GNT# i s asserted. P_PAR U15 PB Primary Parity. Pari ty i s even across P_AD [31:0], P_C BE[3:0], and P_PAR (i .e. an even number of '1's). P_PAR i s an i nput and i s vali d and stable one cycle after the address phase (i ndi cated by asserti on of P_FRAME#) for address pari ty. For wri te data phases, P_PAR i s an i nput and i s vali d one clock after P_IRD Y# i s asserted. For read data phase, P_PAR i s an output and i s vali d one clock after P_TRD Y# i s asserted. Si gnal P_PAR i s tri -stated one cycle after the PAD li nes are 3-stated. D uri ng bus i dle, PI7C 7100 dri ves PPAR to a vali d logi c level when P_GNT# i s asserted. P_FRAME# W13 PSTS Primary FR AME (Activ e LOW). D ri ven by the i ni ti ator of a transacti on to i ndi cate the begi nni ng and durati on of an access. The de-asserti on of P_FRAME# i ndi cates the fi nal data phase requested by the i ni ti ator. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. P_IRD Y# V 13 PSTS Primary IR D Y (Activ e LOW). D ri ven by the i ni ti ator of a transacti on to i ndi cate i ts abi li ty to complete current data phase on the pri mary si de. Once asserted i n a data phase, i t i s not de-asserted unti l end of data phase. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. P_TRD Y# U13 PSTS Primary TR D Y (Activ e LOW). D ri ven by the target of a transacti on to i ndi cate i ts abi li ty to complete current data phase on the pri mary si de. Once asserted i n a data phase, i t i s not de-asserted unti l end of data phase. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. 4 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 3.2.1 Primary Bus Interface Signals (continued) N ame Pin # Ty pe D escription P _D E V S E L# Y14 PSTS Primary D ev ice Select (Activ e LOW). Asserted by the target i ndi cati ng that the devi ce i s accepti ng the transacti on. As a master, PI7C 7100 wai ts for the asserti on of thi s si gnal wi thi n 5 cycles of P_FRAME# asserti on; otherwi se, termi nate wi th master abort. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. P_STOP# W14 PSTS Primary STOP (Activ e LOW). Asserted by the target i ndi cati ng that the target i s requesti ng the i ni ti ator to stop the current transacti on. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. P_LOC K# V 14 PSTS Primary LOC K (Activ e LOW). Asserted by master for multi ple transacti ons to complete. P_ID SEL Y10 PI Primary ID Select. Used as chi p select li ne for Type 0 confi gurati on access to PI7C 7100 confi gurati on space. P_PERR# Y15 PSTS Primary Parity Error (Activ e LOW). Asserted when a data pari ty error i s detected for data recei ved on the pri mary i nterface. Before bei ng 3-stated, i t i s dri ven to a deasserted state for one cycle. P_SERR# W15 POD Primary Sy stem Error (Activ e LOW). C an be dri ven LOW by any devi ce to i ndi cate a system error condi ti on, PI7C 7100 dri ves thi s pi n on: Address pari ty error Posted wri te data pari ty error on target bus Secondary S1_SERR# or S2_SERR# asserted Master abort duri ng posted wri te transacti on Target abort duri ng posted wri te transacti on Posted wri te transacti on di scarded D elayed wri te request di scarded D elayed read request di scarded D elayed transacti on master ti meout Thi s si gnal requi res an external pull-up resi stor for proper operati on. P_REQ# W6 PTS Primary R equest (Activ e LOW). Thi s i s asserted by PI7C 7100 to i ndi cate that i t wants to start a transacti on on the pri mary bus. PI7C 7100 de-asserts thi s pi n for at least 2 PC I clock cycles before asserti ng i t agai n. P_GNT# U7 PI Primary Grant (Activ e LOW). When asserted, PI7C 7100 can access the pri mary bus. D uri ng i dle and P_GNT# asserted, PI7C 7100 wi ll dri ve P_AD , P_C BE and P_PAR to vali d logi c levels. P_RESET# Y5 PI Primary R ESET (Activ e LOW). When P_RESET# i s acti ve, all PC I si gnals should be asynchronously 3-stated. P_FLUSH# W5 PI Primary FIFO FLU SH (Activ e LOW). When P_FLUSH# i s acti ve, all the pri mary FIFO(s) are cleared (i nvali date all pri mary transacti ons). Thi s si gnal should be pulled to a stati c "hi gh." P_M66EN V 18 R eserv ed for Future U se. Must be ti ed to ground. 5 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 3.2.2 Secondary Bus Interface Signals N ame S1_AD [31:0], S2_AD [31:0] Pin # B 20, B 19, C 20, C 19, C 18, D 20, D 19, D 17, E 19, E 18, E 17, F 20, F19, F17, G20, G19, L20, L19, L18, M20, M19, M17, N20, N19, N18, N17, P17, R20, R19, R18, T20, T19 J4, H1, H2, H3, H4, G1, G3, G4, F2, F3, F4, E1, E 4, D 1, C 1, B 1, C 5, B 5, D 6, C 6, B 6, A 6, C 7, B 7, D 8, C 8, D 9, C 9, B 9, A 9, D 10, C 10 Ty pe PB PB D escription Secondary Address/D ata. Multi plexed address and data bus. Address i s i ndi cated by S1_FRAME# or S2_FRAME# asserti on. Wri te data i s stable and vali d when S1_IRD Y# or S2_IRD Y# i s asserted and read data i s stable and vali d when S1_TRD Y# or S2_TRD Y# i s asserted. D ata i s transferred on ri si ng clock edges when both S1_IRD Y# and S1_TRD Y# or S2_IRD Y# and S2_TRD Y# are asserted. D uri ng bus i dle, PI7C 7100 dri ves S1_AD or S2_AD to a vali d logi c level when the S1_GNT# or S2_GNT# i s asserted respecti vely. S1_C BE[3:0], S2_C BE[3:0] E20, G18, K17, P20 F 1, A 1, A 4, A 7 Secondary C ommand/B y te Enables. Multi plexed command fi eld and byte enable fi eld. D uri ng the address phase, the i ni ti ator dri ves the transacti on type on these pi ns. After that the i ni ti ator dri ves the byte enables duri ng data phases. D uri ng bus i dle, PI7C 7100 dri ves S1_C BE[3:0] or S2_C BE[3:0] to a vali d logi c level when the i nternal grant i s asserted. S1_PAR, S2_PAR K 18, B4 PB Secondary Parity. Pari ty i s even across S1_AD [31:0], S1_C BE[3:0], and S1_PAR or S2_AD [31:0], S2_C BE[3:0], and S2_PAR (i .e. an even number of '1's). S1_PAR or S2_PAR i s an i nput and i s vali d and stable one cycle after the address phase (i ndi cated by asserti on of S1_FRAME# or S2_FRAME#) for address pari ty. For wri te data phases, S1_PAR or S2_PAR i s an i nput and i s vali d one clock after S1_IRD Y# or S2_IRD Y# i s asserted. For read data phase, S1_PAR or S2_PAR i s an output and i s vali d one clock after S1_TRD Y# or S2_TRD Y# i s asserted. Si gnal S1_PAR or S2_PAR i s 3-stated one cycle after the S1_AD or S2_AD li nes are tri -stated. D uri ng bus i dle, PI7C 7100 dri ves S1_PAR or S2_PAR to a vali d logi c level when the i nternal grant i s asserted. S1_FRAME#, S2_FRAME# H20, D2 PSTS Secondary FR AME (Activ e LOW). D ri ven by the i ni ti ator of a transacti on to i ndi cate the begi nni ng and durati on of an access. D e-asserti on of S1_FRAME# or S2_FRAME# i ndi cates the fi nal data phase requested by i ni ti ator. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. S1_IRD Y#, S2_IRD Y# H19, B2 PSTS Secondary IR D Y (Activ e LOW). D ri ven by the i ni ti ator of a transacti on to i ndi cate i ts abi li ty to complete the current data phase on the pri mary si de. Once asserted i n a data phase, i t i s not de-asserted unti l end of the data phase. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. S1_TRD Y#, S2_TRD Y# H18, A2 PSTS Secondary TR D Y (Activ e LOW). D ri ven by the target of a transacti on to i ndi cate i ts abi li ty to complete the current data phase on the pri mary si de. Once asserted i n a data phase, i t i s not de-asserted unti l end of the data phase. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. S 1_D E V S E L#, S 2_D E V S E L# J2 0 , D3 PSTS Secondary D ev ice Select (Activ e LOW). Asserted by the target i ndi cati ng that the devi ce i s accepti ng the transacti on. As a master, PI7C 7100 wai ts for the asserti on of thi s si gnal wi thi n 5 cycles of S1_FRAME# or S2_FRAME# asserti on; otherwi se, termi nate wi th master abort. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. 6 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 3.2.2 Secondary Bus Interface Signals (continued) N ame Pin # Ty pe D escription S1_STOP#, S2_STOP# J1 9 , C3 PSTS Secondary STOP (Activ e LOW). Asserted by the target i ndi cati ng that the target i s requesti ng the i ni ti ator to stop the current transacti on. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. S1_LOC K#, S2_LOC K# J1 8 , B3 PSTS Secondary LOC K (Activ e LOW). Asserted by master for multi ple transacti ons to complete. S1_PERR#, S2_PERR# J1 7 , D4 PSTS Secondary Parity Error (Activ e LOW). Asserted when a data pari ty error i s detected for data recei ved on the secondary i nterface. Before bei ng 3-stated, i t i s dri ven to a de-asserted state for one cycle. S1_SERR#, S2_SERR# K 20, C4 PI Secondary Sy stem Error (Activ e LOW). C an be dri ven LOW by any devi ce to i ndi cate a system error condi ti on. S1_REQ#[7:0], B11, A12, D 13, C 13, C 15, A 16, C 17, B 17 T2, R3, P2, P1, M2, M1, K 1, K 3 PIU Secondary R equest (Activ e LOW). Thi s i s asserted by an external devi ce to i ndi cate that i t wants to start a transacti on on the Secondary bus. The i nput i s externally pulled up through a resi stor to VD D . C 11, B12, B 13, A 14, D 14, B 16, D 16, B 18 U1, P4, R1, N4, M3, L4, L1, K 2 PO Secondary Grant (Activ e LOW). PI7C 7100 asserts thi s pi n to access the secondary bus. PI7C 7100 de-asserts thi s pi n for at least 2 PC I clock cycles before asserti ng i t agai n. D uri ng i dle and S1_GNT# or S2_GNT# asserted, PI7C 7100 wi ll dri ve S1_AD , S1_C BE and S1_PAR or S2_AD , S2_C BE and S2_PAR to vali d logi c levels. S1_RESET#, S2_RESET# B 10, T4 PO Secondary R ESET (Activ e LOW). Asserted when any of the followi ng condi ti ons are met: 1. Si gnal P_RESET# i s asserted. 2. Secondary reset bi t i n bri dge control regi ster i n confi gurati on space i s set. When asserted, all control si gnals are 3-stated and zeros are dri ven on S1_AD , S1_C BE, and S1_PAR or S2_AD , S2_C BE, and S2_PAR. S1_EN, S 2_E N W3, W4 PIU Secondary Enable (Activ e H IGH ). When S1_EN or S2_EN i s i nacti ve, secondary PC I S1 or S2 bus wi ll be asynchronously 3-stated. S_M66EN D7 R eserv ed for Future U se. Must be ti ed to ground. S_C FN# Y2 C IU Secondary B us C entral Function C ontrol Pin. When ti ed LOW, i t enables the i nternal arbi ter. When ti ed HIGH, an external arbi ter must be used. S1_REQ0# or S2_REQ0# i s reconfi gured to be the secondary bus grant i nput, and S1_GNT0# or S2_GNT0# i s reconfi gured to be the secondary bus request output. S2_REQ#[7:0] S1_GNT#[7:0], S2_GNT#[7:0] 7 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 3.2.3 Clock Signals N ame P _C LK Pin # V6 Ty pe D escription PI Primary C lock Input. Provi des ti mi ng for all transacti on on pri mary i nterface. S_C LKOUT T3, T1, P3, PTS [15:0] N3,M4, L3, L2, J1,A11, C 12, A 13, B 14, B 15, C 16, A 18, A 19 Secondary C lock Output. Provi des secondary clocks phase synchronous wi th the P_C LK. 3.2.4 Miscellaneous Signals N ame Pin # Ty pe D escription BYPASS Y4 R eserv ed for Future U se. Must be ti ed HIGH. PLL_TM Y3 R eserv ed for Future U se. Must be ti ed LOW. S_C LKIN V5 PI Secondary Test C lock Input. It should be ti ed to LOW i n normal mode. It also may be a secondary clock i nput for the secondary buses i f both SC AN_TM# and SC AN_EN are connected to logi c "1". SC AN_TM# V4 CI Full-scan Test Mode enable (Activ e LOW). When SC AN_TM# i s acti ve, the twelve scan chai ns wi ll be enabled. The scan clock i s P_C LK. The scan i nputs and outputs are as follows: S1_REQ[7], S1_REQ[6], S1_REQ[5], S1_REQ[4], S1_REQ[3], S1_REQ[2], S2_REQ[7], S2_REQ[6], S2_REQ[5], S2_REQ[4], S2_REQ[3], S2_REQ[2] and S1_GNT[7], S1_GNT[6], S1_GNT[5], S1_GNT[4], S1_GNT[3], S1_GNT[2], S2_GNT[7], S2_GNT[6], S2_GNT[5], S2_GNT[4], S2_GNT[3], S2_GNT[2] respecti vely SC AN_EN U5 C IU Full-scan Enable C ontrol. When SC AN_EN i s LOW, full-scan i s i n shi ft operati on i f SC AN_TM# i s acti ve. When SC AN_EN i s HIGH, full-scan i s i n parallel operati on i f SC AN_TM# i s acti ve. SC AN_EN should be ti ed LOW i n normal mode. If SC AN_TM# and SC AN_EN are connected to logi c "1", S_C LKIN i s the clock source for the i nternal secondary clock. If SC AN_TM# i s connected to logi c "1" and SC AN_EN i s connected to logi c "0", P_C LK i s the clock source for the i nternal secondary clock. N ote: D uri ng power-up, SC AN_EN i s the reset si gnal for the on-chi p PLL. C MPO1 U6 R eserv ed for Future U se. Reserved R4 R eserv ed 8 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 3.2.5 JTAG Boundary Scan Signals N ame Pin # Ty pe D escription TC K V2 C IU Test C lock. Used to clock state i nformati on and data i nto and out of the PI7C 7100 duri ng boundary scan. TMS W1 C IU Test Mode Select. Used to control the state of the Test Access Port controller. TD O V3 C TO Test D ata Output. When SC ANEN i s HIGH i t i s used (i n conjuncti on wi th TC K) to shi ft data out of the Test Access Port (TAP) i n a seri al bi t stream. TD I W2 C IU Test D ata Input. When SC ANEN i s HIGH i t i s used (i n conjuncti on wi th TC K) to shi ft data and i nstructi ons i nto the Test Access Port (TAP) a seri al bi t stream. TRST# U3 C IU Test R eset. Acti ve LOW si gnal to reset the Test Access Port (TAP) controller i nto an i ni ti ali zed state. 3.2.6 Power and Ground N ame VD D Pin # Ty pe D escription B8, C 14, D 5, D 11, D 15, E2, F18, J3, L17, N2, P19, U10, V1, V7, V15, W20 +3.3V D igital Power VSS A 3, A 5, A 8, A 10, A 15, A 17, A 20, C 2, D 12, D 18, E3, G2, G17, H17, J2, K4, K19, M18, N1, P18, R2, T18, U2, U9, U14, U17 V17 W11 Y6 Y13 D igital Ground AVC C Y1 Analog 3.3V for PLL AGND U4 Analog Ground for PLL 9 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 4. PCI Bus Operation This chapter offers information about PCI transactions, transaction forwarding across PI7C7100, and transaction termination. The PI7C7100 has three 128-byte buffers for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables and are used for both read and write transactions. 4.1 Types of Transactions This section provides a summary of PCI transactions performed by PI7C7100. Table 41 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C7100 initiates transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when PI7C7100 responds to transactions as a target, on the primary (P) and secondary (S1, S2) buses. Table 4-1. PCI Transactions Ty pe of Transactions Initiates as Master R esponds as Target Primary Secondary Primary Secondary 0000 Interrupt acknowledge N N N N 0001 Speci al cycle Y Y N N 0010 I/O read Y Y Y Y 0011 I/O wri te Y Y Y Y 0100 Reserved N N N N 0101 Reserved N N N N 0110 Memory read Y Y Y Y 0111 Memory wri te Y Y Y Y 1000 Reserved N N N N 1001 Reserved N N N N 1010 C onfi gurati on read N Y Y N 1011 C onfi gurati on wri te Y (Type 1 only) Y Y Y (Type 1 only) 1100 Memory read multi ple Y Y Y Y 1101 D ual address cycle N N N N 1110 Memory read li ne Y Y Y Y 1111 Memory wri te and i nvali date N N Y Y As indicated in Table 41, the following PCI commands are not supported by PI7C7100: PI7C7100 never initiates a PCI transaction with a reserved command code and, as a target, PI7C7100 ignores reserved command codes. PI7C7100 does not generate interrupt acknowledge transactions. PI7C7100 ignores interrupt acknowledge transactions as a target. PI7C7100 does not respond to special cycle transactions. PI7C7100 cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. To generate special cycle transactions on other PCI buses, either upstream or downstream, Type 1 configuration write must be used. PI7C7100 neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary PCI buses. PI7C7100 does not support DAC (Dual Address Cycle) transactions. 10 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 4.2 Single Address Phase A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus command is driven on P_CBE[3:0]. PI7C7100 supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, PI7C7100 automatically disconnects the transaction after the first data transfer. 4.3 Device Select (DEVSEL#) Generation PI7C7100 always performs positive address decoding (medium decode) when accepting transactions on either the primary or secondary buses. PI7C7100 never does subtractive decode. 4.4 Data Phase The address phase of a PCI transaction is followed by one or more data phases. A data phase is completed when IRDY# and either TRDY# or STOP# are asserted. A transfer of data occurs only when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are asserted. See Section 4.8 for further discussion of transaction termination. Depending on the command type, PI7C7100 can support multiple data phase PCI transactions. For a detailed description of how PI7C7100 imposes disconnect boundaries, see Section 4.5.4 for write address boundaries and Section 4.6.3 read address boundaries. 4.5 Write Transactions Write transactions are treated as either posted write or delayed write transactions. Table 42 shows the method of forwarding used for each type of write operation. Table 4-2. Write Transaction Forwarding Ty pe of Transaction Ty pe of Forwarding Memory wri te Posted Memory wri te and i nvali date Posted I/O wri te D elayed Type 1 confi gurati on wri te D elayed For timing diagrams, see Figures 15-22 and 27-30 in Appendix A 4.5.1 Posted Write Transactions Posted write forwarding is used for Memory Write and Memory Write and Invalidate transactions. When PI7C7100 determines that a memory write transaction is to be forwarded across the bridge, PI7C7100 asserts DEVSEL# with medium timing and TRDY# in the same cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one DWORD of data. Under this condition, PI7C7100 accepts write data without obtaining access to the target bus. The PI7C7100 can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target. The PI7C7100 continues to accept write data until one of the following events occurs: The initiator terminates the transaction by de-asserting FRAME# and IRDY#. An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending on the transaction type. The posted write data buffer fills up. 11 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 When one of the last two events occurs, the PI7C7100 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves to the head of the posted data queue, PI7C7100 asserts its request on the target bus. This can occur while PI7C7100 is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, PI7C7100 asserts FRAME# and drives the stored write address out on the target bus. On the following cycle, PI7C7100 drives the first DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, PI7C7100 can drive one DWORD of write data each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through PI7C7100 and the initiator stalls, PI7C7100 may have to insert wait states on the target bus if the queue empties. PI7C7100 ends the transaction on the target bus when one of the following conditions is met: All posted write data has been delivered to the target. The target returns a target disconnect or target retry (PI7C7100 starts another transaction to deliver the rest of write data). The target returns a target abort (PI7C7100 discards remaining write data). The master latency timer expires, and PI7C7100 no longer has the target bus grant (PI7C7100 starts another transaction to deliver remaining write data). Section 4.8.3.2 provides detailed information about how PI7C7100 responds to target termination during posted write transactions. 4.5.2 Memory Write and Invalidate Transactions Posted write forwarding is used for Memory Write and Invalidate transactions. PI7C7100 always converts Memory Write and Invalidate transactions to Memory Write transactions. The PI7C7100 disconnects Memory Write and Invalidate commands at aligned cache line boundaries. The cache line size value in the cache line size register gives the number of DWORD in a cache line. If the value in the cache line size register does meet the memory write and invalidate conditions, the PI7C7100 returns a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. When the Memory Write and Invalidate transaction is disconnected before a cache line boundary is reached, typically because the posted write buffer fills, the transaction is converted to Memory Write transaction. 4.5.3 Delayed Write Transactions Delayed write forwarding is used for I/O write transactions and Type 1 configuration write transactions. A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a single DWORD data transfer. When a write transaction is first detected on the initiator bus, and PI7C7100 forwards it as a delayed transaction, PI7C7100 claims the access by asserting DEVSEL# and returns a target retry to the initiator. During the address phase, PI7C7100 samples the bus command, address, and address parity one cycle later. After IRDY# is asserted, PI7C7100 also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C7100 initiates the transaction on the target bus. PI7C7100 transfers the write data to the target. If PI7C7100 receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. If PI7C7100 is unable to deliver write data after 224(default) or 232(maximum) attempts, PI7C7100 ceases further write attempts and returns a target abort to the initiator. The delayed transaction is removed from the delayed transaction queue. PI7C7100 also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of P_SERR#. When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the PI7C7100 12 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C7100 also asserts STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH), the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to the target, PI7C7100 returns a target retry to the initiator. PI7C7100 continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C7100 does not make a new entry into the delayed transaction queue. Section 4.8.3.1 provides detailed information about how PI7C7100 responds to target termination during delayed write transactions. PI7C7100 implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction queue. The initial value of this timer can be set to one of two values, selectable through both the primary and secondary master timeout bits in the bridge control register. If the initiator does not repeat the delayed write transaction before the discard timer expires, PI7C7100 discards the delayed write transaction from the delayed transaction queue. PI7C7100 also conditionally asserts P_SERR# (see Section 7.4). 4.5.4 Write Transaction Address Boundaries PI7C7100 imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C7100 from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C7100 returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table 43. Table 4-3. Write Transaction Disconnect Address Boundaries Ty pe of Transaction C ondition Aligned Address B oundary D elayed wri te All D i sconnects after one data transfer Posted memory wri te Memory wri te di sconnect control bi t = 0 Posted memory wri te Memory wri te di sconnect control bi t = 1 (1) D i sconnects at cache li ne boundary Posted memory wri te and i nvali date C ache li ne si ze not equal to 1, 2, 4, 8, 16 4KB ali gned address boundary Posted memory wri te and i nvali date C ache li ne si ze = 1, 2, 4, 8 nth cache li ne boundary, where a cache li ne boundary i s reached and less than ei ght free D WORD of posted wri te buffer space remai ns Posted memory wri te and i nvali date C ache li ne si ze = 16 16-D WORD ali gned address boundary (1) 4KB ali gned address boundary Note 1. Memory-write-disconnect-control bit is bit 1 of the chip control register at offset 40h in configuration space. 4.5.5 Buffering Multiple Write Transactions PI7C7100 continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C7100 returns a target disconnect to the initiator. Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered. 4.5.6 Fast Back-to-Back Write Transactions PI7C7100 can recognize and post fast back-to-back write transactions. When PI7C7100 cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. 13 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 4.6 Read Transactions Delayed read forwarding is used for all read transactions crossing PI7C7100. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 4-4 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation. For Timing diagrams, see Figures 11-14 and 23-26 in Appendix A 4.6.1 Prefetchable Read Transactions A prefetchable read transaction is a read transaction where PI7C7100 performs speculative DWORD reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist of multiple data transfers. However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C7100 forces all byte enable bits to be turned on for all data phases. Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. The amount of data that is pre-fetched depends on the type of transaction. The amount of pre-fetching may also be affected by the amount of free buffer space available in PI7C7100, and by any read address boundaries encountered. Pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, FIFOs, and so on. The target devices base address register or registers indicate if a memory address region is prefetchable. 4.6.2 Non-prefetchable Read Transactions A non-prefetchable read transaction is a read transaction where PI7C7100 requests one and only one DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions, PI7C7100 forwards the read byte enable information for the data phase. Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory read transactions that fall into non-prefetchable memory space. If extra read transactions could have side effects, for example, when accessing a FIFO, use non-prefetchable read transactions to those locations. Accordingly, if it is important to retain the value of the byte enable bits during the data phase, use non-prefetchable read transactions. If these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior. 4.6.3 Read Pre-fetch Address Boundaries PI7C7100 imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the PI7C7100 stops pre-fetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. When PI7C7100 finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is discarded. Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address boundary, or until the initiator de-asserts FRAME#. Section 4.6.6 describes flow-through mode during read operations. Table 4-5 shows the read pre-fetch address boundaries for read transactions during non-flow-through mode. Table 4-4. Read Pre-fetch Address Boundaries Ty pe of Transaction Address Space C ache Line Siz e (C LS) Pre-fetch Aligned Address B oundary C onfi g read - - One D WORD (no pre-fetch) I/O read - - One D WORD (no pre-fetch) Memory read Non-prefetchable - One D WORD (no pre-fetch) Memory read Prefetchable C LS not equal to 1, 2, 4, 8 16-D WORD ali gned address boundary Memory read Prefetchable C LS = 1, 2, 4, 8 C ache li ne address boundary Memory read li ne - C LS not equal to 1, 2, 4, 8 16-D WORD ali gned address boundary Memory read li ne - C LS = 1, 2, 4, 8 C ache li ne boundary Memory read multi ple - C LS not equal to 1, 2, 4, 8 32-D WORD ali gned address boundary Memory read multi ple - C LS = 1, 2, 4, 8 2 ti mes of cache li ne boundary 14 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 Table 4-5. Read Transaction Pre-Fetching Ty pe of Transaction R ead B ehav ior I/O read Pre-fetchi ng never done C onfi gurati on read Pre-fetchi ng never done Memory read D ownstream: pre-fetchi ng used i f address i n prefetchable space Upstream: pre-fetchi ng used i f pre-fetch di sable i s off (default) Memory read li ne Pre-fetchi ng always used Memory read multi ple Pre-fetchi ng always used See Section 5.3 for detailed information about prefetchable and non-prefetchable address spaces. 4.6.4 Delayed Read Requests PI7C7100 treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the read data queue directed toward the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction. When PI7C7100 accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY# is asserted, PI7C7100 then samples the byte enable bits for the first data phase. This information is entered into the delayed transaction queue. PI7C7100 terminates the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response (target abort or master abort) other than a target retry is received. 4.6.5 Delayed Read Completion with Target When delayed read request reaches the head of the delayed transaction queue, PI7C7100 arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. PI7C7100 uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate the read transaction. If the read transaction is a non-prefetchable read, PI7C7100 drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C7100 receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. If the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, PI7C7100 does not initiate any further attempts to read more data. If PI7C7100 is unable to obtain read data from the target after 224(default) or 232(maximum) attempts, PI7C7100 ceases further read attempts and returns a target abort to the initiator. The delayed transaction is removed from the delayed transaction queue. The number of attempts is programmable. PI7C7100 also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of P_SERR#. Once PI7C7100 receives DEVSEL# and TRDY# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite interface, before terminating the transaction. For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The PI7C7100 can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of DWORD transferred during a delayed read transaction depends on the conditions given in Table 45 (assuming no disconnect is received from the target). 4.6.6 Delayed Read Completion on Initiator Bus When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C7100 transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C7100 aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C7100 returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C7100 initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. 15 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C7100 reflects the stalled condition to the initiator by de-asserting TRDY# until more read data is available; otherwise, PI7C7100 does not insert any target wait states. When the initiator terminates the transaction, PI7C7100 de-assertion of FRAME# on the initiator bus is forwarded to the target bus. Any remaining read data is discarded. PI7C7100 implements a discard timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the discard timer expires, PI7C7100 discards the read transaction and read data from its queues. PI7C7100 also conditionally asserts P_SERR# (see Section 7.4). PI7C7100 has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. See Section 6 for a discussion of how delayed read transactions are ordered when crossing PI7C7100. 4.7 Configuration Transactions Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C7100 also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted. For timing diagrams, see Figures 1-8 in Appendix A. 4.7.1 Type 0 Access to PI7C7100 The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C7100 responds to a Type 0 configuration transaction by asserting P_DEVSEL# when the following conditions are met during the address phase: The bus command is a configuration read or configuration write transaction. Lowest two address bits P_AD[1:0] must be 00b. Signal P_IDSEL must be asserted. Function code is either 0 for configuration space of S1, or 1 for configuration space of S2 as PI7C7100 is a multi-function device. PI7C7100 limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits. 16 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C7100 ignores all Type 0 transactions initiated on the secondary interface. 4.7.2 Type 1 to Type 0 Conversion Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCIto-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. PI7C7100 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C7100 must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is, PI7C7100 generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PI7C7100 responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase: The lowest two address bits on P_AD[1:0] are 01b. The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. The bus command on P_CBE[3:0] is a configuration read or configuration write transaction. When PI7C7100 translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: Sets the lowest two address bits on S1_AD[1:0] or S2_AD[1:0] to 00b. Decodes the device number and drives the bit pattern specified in Table 46 on S1_AD[31:16] or S2_AD[31:16] for the purpose of asserting the devices IDSEL signal. Sets S1_AD[15:11] or S2_AD[15:11] to 0. Leaves unchanged the function number and register number fields. PI7C7100 asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits P_AD[15:11]. Table 46 presents the mapping that PI7C7100 uses 17 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Table 46. Device Number to IDSEL S1_AD or S2_AD Pin Mapping D ev ice N umber P_AD <15: 11> Secondary ID SEL S1_AD [31: 16] or S2_AD [31: 16] S1_AD or S2_AD B it 0h 00000 0000 0000 0000 0001 16 1h 00001 0000 0000 0000 0010 17 2h 00010 0000 0000 0000 0100 18 3h 00011 0000 0000 0000 1000 19 4h 00100 0000 0000 0001 0000 20 5h 00101 0000 0000 0010 0000 21 6h 0110 0000 0000 0100 0000 22 7h 00111 0000 0000 1000 0000 23 8h 01000 0000 0001 0000 0000 24 9h 01001 0000 0010 0000 0000 25 Ah 01010 0000 0100 0000 0000 26 Bh 01011 0000 1000 0000 0000 27 Ch 01100 0001 0000 0000 0000 28 Dh 01101 0010 0000 0000 0000 29 Eh 01110 0100 0000 0000 0000 30 Fh 01111 1000 0000 0000 0000 31 10h-1Eh 10000-11110 0000 0000 0000 0000 - 1F h 11111 Generate speci al cycle (P_AD [7:2] = 00h) 0000 0000 0000 0000 (P_AD [7:2] = 00h) - PI7C7100 can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of elec3cal loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a master abort. PI7C7100 forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer. 4.7.3 Type 1 to Type 1 Forwarding Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCIto-PCI bridges are used. When PI7C7100 detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, PI7C7100 forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase: The lowest two address bits are equal to 01b. The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The bus command is a configuration read or write transaction. 18 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 PI7C7100 also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met: The lowest two address bits are equal to 01b. The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The bus command is a configuration write transaction. The PI7C7100 forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer. 4.7.4 Special Cycles The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the downstream direction. PI7C7100 initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: The lowest two address bits on AD[1:0] are equal to 01b. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The register number in address bits AD[7:2] is equal to 000000b. The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding. The bus command on CBE# is a configuration write command. When PI7C7100 initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are forwarded unchanged. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). Once the transaction is completed on the target bus, through detection of the master abort condition, PI7C7100 responds with TRDY# to the next attempt of the configuration transaction from the initiator. If more than one data transfer is requested, PI7C7100 responds with a target disconnect operation during the first data phase. 4.8 Transaction Termination This section describes how PI7C7100 returns transaction termination conditions back to the initiator. The initiator can terminate transactions with one of the following types of termination: Normal termination Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data phase, and deasserts IRDY# at the end of the last data phase in conjunction with either TRDY# or STOP# assertion from the target. Master abort A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates the transaction with a master abort. If FRAME# is still asserted, the initiator de-asserts FRAME# on the next cycle, and then de-asserts IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# de-asserts. If FRAME# is already de-asserted, IRDY# can be de-asserted on the next clock cycle following detection of the master abort condition. 19 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 The target can terminate transactions with one of the following types of termination: Normal terminationTRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY# asserted. Target retrySTOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase. No data transfers occur during the transaction. This transaction must be repeated. Target disconnect with data transferSTOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the transaction. Target disconnect without data transferSTOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been made. Indicates that no more data transfers will be made during this transaction. Target abortSTOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction before the target abort is signaled. 4.8.1 Master Termination Initiated by PI7C7100 PI7C7100, as an initiator, uses normal termination if DEVSEL# is returned by target within five clock cycles of PI7C7100s assertion of FRAME# on the target bus. As an initiator, PI7C7100 terminates a transaction when the following conditions are met: During a delayed write transaction, a single DWORD is delivered. During a non-prefetchable read transaction, a single DWORD is transferred from the target. During a prefetchable read transaction, a pre-fetch boundary is reached. For a posted write transaction, all write data for the transaction is transferred from data buffers to the target. For burst transfer, with the exception of Memory Write and Invalidate transactions, the master latency timer expires and the PI7C7100s bus grant is de-asserted. The target terminates the transaction with a retry, disconnect, or target abort. If PI7C7100 is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. The address of the transaction is updated to reflect the address of the current DWORD to be delivered. If PI7C7100 is pre-fetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data. 4.8.2 Master Abort Received by PI7C7100 If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by the target within five clock cycles of the assertion of FRAME#, PI7C7100 terminates the transaction with a master abort. This sets the receivedmaster-abort bit in the status register corresponding to the target bus. For delayed read and write transactions, PI7C7100 is able to reflect the master abort condition back to the initiator. When PI7C7100 detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, PI7C7100 does not respond to the transaction with DEVSEL# which induces the master abort condition back to the initiator. The transaction is then removed from the delayed transaction queue. When a master abort is received in response to a posted write transaction, PI7C7100 discards the posted write data and makes no more attempt to deliver the data. PI7C7100 sets the received-master-abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface. When master abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of bridge control register) and the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) are set, PI7C7100 asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h). Note: When PI7C7100 performs a Type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. In this case, the master abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase. 20 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 4.8.3 Target Termination Received by PI7C7100 When PI7C7100 initiates a transaction on the target bus and the target responds with DEVSEL#, the target can end the transaction with one of the following types of termination: Normal termination (upon de-assertion of FRAME#) Target retry Target disconnect Target abort PI7C7100 handles these terminations in different ways, depending on the type of transaction being performed. 4.8.3.1 Delayed Write Target Termination Response When PI7C7100 initiates a delayed write transaction, the type of target termination received from the target can be passed back to the initiator. Table 47 shows the response to each type of target termination that occurs during a delayed write transaction. PI7C7100 repeats a delayed write transaction until one of the following conditions is met: PI7C7100 completes at least one data transfer. PI7C7100 receives a master abort. PI7C7100 receives a target abort. PI7C7100 makes 224(default) or 232(maximum) write attempts resulting in a response of target retry. Table 4-7. Posted Write Target Termination Response Target Termination R esp o n se Normal Returni ng di sconnect to i ni ti ator wi th fi rst data transfer only i f multi ple data phases requested. Target retry Returni ng target retry to i ni ti ator. C onti nue wri te attempts to target. Target di sconnect Returni ng di sconnect to i ni ti ator wi th fi rst data transfer only i f multi ple data phases requested. Target abort Returni ng target abort to i ni ti ator.Set recei ved target abort bi t i n target i nterface status regi ster.Set si gnaled target abort bi t i n i ni ti ator i nterface status regi ster. After the PI7C7100 makes 224(default) attempts of the same delayed write transaction on the target bus, PI7C7100 asserts P_SERR# if the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) is set and the delayed-writenon-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C7100 stops initiating transaction in response to that delayed write transaction. The delayed write request is discarded. Upon a subsequent write transaction attempt by the initiator, PI7C7100 returns a target abort. See Section 7.4 for a description of system error conditions. 4.8.3.2 Posted Write Target Termination Response When PI7C7100 initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 48 shows the response to each type of target termination that occurs during a posted write transaction. 21 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Table 4-8. Responses to Posted Write Target Termination Target Termination R esp o n se Normal No addi ti onal acti on. Target retry Repeati ng wri te transacti on to target. Target di sconnect Ini ti ate wri te transacti on for deli veri ng remai ni ng posted wri te data. Target abort Set recei ved-target-abort bi t i n the target i nterface status regi ster. Assert P_SERR# i f enabled, and set the si gnaled-system-error bi t i n pri mary status regi ster. Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, PI7C7100 initiates another write transaction to attempt to deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for the initial write transaction attempt. If a target disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect the address of the current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, PI7C7100 will use the memory write command to deliver the rest of the write data. It is because an incomplete cache line will be transferred in the subsequent write transaction attempt. After the PI7C7100 makes 224(default) write transaction attempts and fails to deliver all posted write data associated with that transaction, PI7C7100 asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of P_SERR# event disable register (offset 64h). The write data is discarded. See Section 7.4 for a discussion of system error conditions. 4.8.3.3 Delayed Read Target Termination Response When PI7C7100 initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator. Other target responses depend on how much data the initiator requests. Table 49 shows the response to each type of target termination that occurs during a delayed read transaction. PI7C7100 repeats a delayed read transaction until one of the following conditions is met: PI7C7100 completes at least one data transfer. PI7C7100 receives a master abort. PI7C7100 receives a target abort. PI7C7100 makes 224(default) read attempts resulting in a response of target retry. Table 4-9. Responses to Delayed Read Target Termination Target Termination R esp o n se Normal If prefetchable, target di sconnect only i f i ni ti ator requests more data than read from target. If non-prefetchable, target di sconnect on fi rst data phase. Target retry Rei ni ti ate read transacti on to target. Target di sconnect If i ni ti ator requests more data than read from target, return target di sconnect to i ni ti ator. Target abort Return target abort to i ni ti ator. Set recei ved target abort bi t i n the target i nterface status regi ster. Set si gnaled target abort bi t i n the i ni ti ator i nterface status regi ster. 22 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 After PI7C7100 makes 224(default) attempts of the same delayed read transaction on the target bus, PI7C7100 asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and the delayedwrite-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C7100 stops initiating transactions in response to that delayed read transaction. The delayed read request is discarded. Upon a subsequent read transaction attempt by the initiator, PI7C7100 returns a target abort. See Section 7.4 for a description of system error conditions. 4.8.4 Target Termination Initiated by PI7C7100 PI7C7100 can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface. 4.8.4.1 Target Retry PI7C7100 returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. PI7C7100 returns a target retry to an initiator when any of the following conditions is met: For delayed write transactions: The transaction is being entered into the delayed transaction queue. Transaction has already been entered into delayed transaction queue, but target response has not yet been received. Target response has been received but has not progressed to the head of the return queue. The delayed transaction queue is full, and the transaction cannot be queued. A transaction with the same address and command has been queued. A locked sequence is being propagated across PI7C7100, and the write transaction is not a locked transaction. The target bus is locked and the write transaction is a locked transaction. Use more than 16 clocks to accept this transaction. For delayed read transactions: The transaction is being entered into the delayed transaction queue. The read request has already been queued, but read data is not yet available. Data has been read from target, but it is not yet at head of the read data queue, or a posted write transaction precedes it. The delayed transaction queue is full, and the transaction cannot be queued. A delayed read request with the same address and bus command has already been queued. A locked sequence is being propagated across PI7C7100, and the read transaction is not a locked transaction. PI7C7100 is currently discarding previously pre-fetched read data. The target bus is locked and the write transaction is a locked transaction. Use more than 16 clocks to accept this transaction. For posted write transactions: The posted write data buffer does not have enough space for address and at least one DWORD of write data. A locked sequence is being propagated across PI7C7100, and the write transaction is not a locked transaction. When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. Otherwise, the transaction is discarded from the buffers. 23 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 4.8.4.2 Target Disconnect PI7C7100 returns a target disconnect to an initiator when one of the following conditions is met: PI7C7100 hits an internal address boundary. PI7C7100 cannot accept any more write data. PI7C7100 has no more read data to deliver. See Section 4.5.4 for a description of write address boundaries, and Section 4.6.3 for a description of read address boundaries. 4.8.4.3 Target Abort PI7C7100 returns a target abort to an initiator when one of the following conditions is met: PI7C7100 is returning a target abort from the intended target. PI7C7100 is unable to obtain delayed read data from the target or to deliver delayed write data to the target after 224 (default) attempts. When PI7C7100 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface. 24 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 5. Address Decoding PI7C7100 uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support. 5.1 Address Ranges PI7C7100 uses the following address ranges that determine which I/O and memory transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus: Two 32-bit I/O address ranges Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges Two 32-bit prefetchable memory address ranges Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the two secondary PCI buses. Transactions falling outside these ranges are forwarded upstream from the two secondary PCI buses to the primary PCI bus. No address translation is required in PI7C7100. The addresses that are not marked for downstream are always forwarded upstream. However, if an address of a transaction initiated from S1 bus is located in the marked address range for downstream in S2 bus and not in the marked address range for downstream in S1 bus, the transaction will be forwarded to S2 bus instead of primary bus. By the same token, if an address of a transaction initiated from S2 bus is located in the marked address range for downstream in S1 bus and not in the marked address range for downstream in S2 bus, the transaction will be forwarded to S1 bus instead of primary bus. 5.2 I/O Address Decoding PI7C7100 uses the following mechanisms that are defined in the configuration space to specify the I/O address space for downstream and upstream forwarding: I/O base and limit address registers The ISA enable bit The VGA mode bit The VGA snoop bit This section provides information on the I/O address registers and ISA mode. Section 5.4 provides information on the VGA modes. To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in configuration space. All I/O transactions initiated on the primary bus will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the masterenable bit is not set, PI7C7100 ignores all I/O and memory transactions initiated on the secondary bus. The masterenable bit also allows upstream forwarding of memory transactions if it is set. CAUTION If any configuration state affecting I/O transaction forwarding is changed by a configuration write operation on the primary bus at the same time that I/O transactions are ongoing on the secondary bus, PI7C7100 response to the secondary bus I/O transactions is not predictable. Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle. 5.2.1 I/O Base and Limit Address Registers PI7C7100 implements one set of I/O base and limit address registers in configuration space that define an I/O address range per port downstream forwarding. PI7C7100 supports 32-bit I/O addressing, which allows I/O addresses downstream of PI7C7100 to be mapped anywhere in a 4GB I/O address space. 25 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with addresses that fall outside this range are forwarded upstream from the secondary PCI bus to the primary PCI bus. The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O limit address. When the I/O range is turned off, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded downstream. The I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O range is 4GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom 4 bits read only as 1h to indicate that PI7C7100 supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O base address is initialized to 0000 0000h. The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration offset 32h define AD[31:16] of the I/O limit address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O limit address is reset to 0000 0FFFh. Note: The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 0000h to 0000 0FFFh, which is the bottom 4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable bit or the master enable bit in the command register in configuration space. 5.2.2 ISA Mode PI7C7100 supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode modifies the response of PI7C7100 inside the I/O address range in order to support mapping of I/O space in the presence of an ISA bus in the system. This bit only affects the response of PI7C7100 when the transaction falls inside the address range defined by the I/O base and limit address registers, and only when this address also falls inside the first 64KB of I/O space (address bits [31:16] are 0000h). When the ISA enable bit is set, PI7C7100 does not forward downstream any I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded as defined by the address range defined by the I/O base and limit registers. Accordingly, if the ISA enable bit is set, PI7C7100 forwards upstream those I/O transactions addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register must also be set to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of PI7C7100 can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary. 5.3 Memory Address Decoding PI7C7100 has three mechanisms for defining memory address ranges for forwarding of memory transactions: Memory-mapped I/O base and limit address registers Prefetchable memory base and limit address registers VGA mode This section describes the first two mechanisms. Section 5.4.1 describes VGA mode. To enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register in configuration space. To enable upstream forwarding of memory transactions, the master-enable bit must be set in the command register. The master-enable bit also allows upstream forwarding of I/O transactions if it is set. 26 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 CAUTION If any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. Configure the memory-mapped I/ O base and limit address registers, prefetchable memory base and limit address registers, and VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle. 5.3.1 Memory-Mapped I/O Base and Limit Address Registers Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot automatically be prefetched but that can be conditionally pre-fetched based on command type should be mapped into this space. Read transactions to non-prefetchable space may exhibit side effects; this space may have non-memory-like behavior. PI7C7100 pre-fetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer. The memory-mapped I/O base address and memory-mapped I/O limit address registers define an address range that PI7C7100 uses to determine when to forward memory commands. PI7C7100 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped I/O address range. PI7C7100 ignores memory transactions initiated on the secondary interface that fall into this address range. Any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstream by the VGA mechanism). The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The memory-mapped I/O address range has a granularity and alignment of 1MB. The maximum memory-mapped I/O address range is 4GB. The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base address register at configuration offset 20h and by a 16-bit memory-mapped I/O limit address register at offset 22h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The low 4 bits are hardwired to 0. The lowest 20 bits of the memorymapped I/O base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the memory-mapped I/O limit address are assumed to be F FFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the memory-mapped I/O base address register is 0000 0000h. The initial state of the memorymapped I/O limit address register is 000F FFFFh. Note that the initial states of these registers define a memory-mapped I/O range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register. 5.3.2 Prefetchable Memory Base and Limit Address Registers Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. PI7C7100 pre-fetches for all types of memory read commands in this address space. The prefetchable memory base address and prefetchable memory limit address registers define an address range that PI7C7100 uses to determine when to forward memory commands. PI7C7100 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the prefetchable memory address range. PI7C7100 ignores memory transactions initiated on the secondary interface that fall into this address range. PI7C7100 does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O range or are not forwarded by the VGA mechanism). The prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits register. For address comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. This upper 27 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register. The prefetchable memory base address upper 32 bits register must be 0 to pass any single address cycle transactions downstream. Prefetchable memory address range has a granularity and alignment of 1MB. Maximum memory address range is 4GB when 32-bit addressing is being used. Prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register at offset 26h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the prefetchable memory limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of these registers define a prefetchable memory range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. The entire base value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register. Otherwise, the upper 32-bit base must be greater than the upper 32-bit limit. 5.4 VGA Support PI7C7100 provides two modes for VGA support: VGA mode, supporting VGA-compatible addressing VGA snoop mode, supporting VGA palette forwarding 5.4.1 VGA Mode When a VGA-compatible device exists downstream from PI7C7100, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When PI7C7100 is operating in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the base and limit address registers. PI7C7100 ignores transactions initiated on the secondary interface addressing these locations. The VGA frame buffer consists of the following memory address range: 000A 0000h000B FFFFh Read transactions to frame buffer memory are treated as non-prefetchable. PI7C7100 requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. The VGA I/O addresses are in the range of 3B0h3BBh and 3C0h3DFh I/O. These I/O addresses are aliases every 1KB throughout the first 64KB of I/O space. This means that address bits <15:10> are not decoded and can be any value, while address bits [31:16] must be all 0s. VGA BIOS addresses starting at C0000h are not decoded in VGA mode. 5.4.2 VGA Snoop Mode PI7C7100 provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode is used when a graphics device downstream from PI7C7100 needs to snoop or respond to VGA palette write transactions. To enable the mode, set the VGA snoop bit in the command register in configuration space. Note that PI7C7100 claims VGA palette write transactions by asserting DEVSEL# in VGA snoop mode. When VGA snoop bit is set, PI7C7100 forwards downstream transactions within the 3C6h, 3C8h and 3C9h I/O addresses space. Note that these addresses are also forwarded as part of the VGA compatibility mode previously described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliases every 1KB throughout the first 64KB of I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C7100 behaves in the same way as if only the VGA mode bit were set. 28 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 6. Transaction Ordering To maintain data coherency and consistency, PI7C7100 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across PI7C7100. 6.1 Transactions Governed by Ordering Rules Ordering relationships are established for the following classes of transactions crossing PI7C7100: Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target. Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus. Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus. Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions. Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from the target bus to the initiator bus. PI7C7100 does not combine or merge write transactions: PI7C7100 does not combine separate write transactions into a single write transactionthis optimization is best implemented in the originating master. PI7C7100 does not merge bytes on separate masked write transactions to the same DWORD addressthis optimization is also best implemented in the originating master. PI7C7100 does not collapse sequential write transactions to the same address into a single write transactionthe PCI Local Bus Specification does not permit this combining of transactions. 6.2 General Ordering Guidelines Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C7100. The following general ordering guidelines govern transactions crossing PI7C7100: The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur. 29 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C7100 can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C7100 and must also be true for other bus agents. Otherwise, a deadlock can occur. PI7C7100 accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C7100. 6.3 Ordering Rules Table 61 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Table 6-1. Summary of Transaction Ordering Posted Write D elay ed R ead R eq u est D elay ed Write R eq u est D elay ed R ead C ompletion D elay ed Write C ompletion Posted wri te N1 Y5 Y5 Y5 Y5 D elayed read request N2 N N Y Y D elayed wri te request N4 N N Y Y D elayed read completi on N3 Y Y N N D elayed wri te completi on Y Y Y N N P ass Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. The entries without superscripts reflect the PI7C7100s implementation choices. The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules are referred to by number in Table 61. These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C7100 in the same direction. Note that delayed completion transactions cross PI7C7100 in the direction opposite that of the corresponding delayed requests. 1. Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction; if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data. 2. A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. 3. A delayed read completion must pull ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C7100 as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. 4. Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data. 30 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 5. Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue. 6.4 Data Synchronization Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus Specification, Revision 2.1, provides the following alternative methods for synchronizing data and interrupts: The device signaling the interrupt performs a read of the data just written (software). The device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software). System hardware guarantees that write buffers are flushed before interrupts are forwarded. PI7C7100 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers. 31 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 7. Error Handling PI7C7100 checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C7100 always 3es to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C100 always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. To support error reporting on the PCI bus, PI7C7100 implements the following: PERR# and SERR# signals on both the primary and secondary interfaces Primary status and secondary status registers The device-specific P_SERR# event disable register This chapter provides detailed information about how PI7C7100 handles errors. It also describes error status reporting and error operation disabling. 7.1 Address Parity Errors PI7C7100 checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C7100 detects an address parity error on the primary interface, the following events occur: If the parity error response bit is set in the command register, PI7C7100 does not claim the transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7100 proceeds normally and accepts the transaction if it is directed to or across PI7C7100. PI7C7100 sets the detected parity error bit in the status register. PI7C7100 asserts P_SERR# and sets signaled system error bit in the status register, if both the following conditions are met: - The SERR# enable bit is set in the command register. - The parity error response bit is set in the command register. When PI7C7100 detects an address parity error on the secondary interface, the following events occur: If the parity error response bit is set in the bridge control register, PI7C7100 does not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7100 proceeds normally and accepts transaction if it is directed to or across PI7C7100. PI7C7100 sets the detected parity error bit in the secondary status register. PI7C7100 asserts P_SERR# and sets signaled system error bit in status register, if both of the following conditions are met: - The SERR# enable bit is set in the command register. - The parity error response bit is set in the bridge control register. 7.2 Data Parity Errors When forwarding transactions, PI7C7100 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across PI7C7100. 7.2.1 Configuration Write Transactions to Configuration Space When PI7C7100 detects a data parity error during a Type 0 configuration write transaction to PI7C7100 configuration space, the following events occur: If the parity error response bit is set in the command register, PI7C7100 asserts P_TRDY# and writes the data to the configuration register. PI7C7100 also asserts P_PERR#. If the parity error response bit is not set, PI7C7100 does not assert P_PERR#. PI7C7100 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit. 32 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 7.2.2 Read Transactions When PI7C7100 detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts PERR#. For downstream transactions, when PI7C7100 detects a read data parity error on the secondary bus, the following events occur: PI7C7100 asserts S_PERR# two cycles following the data transfer, if the secondary interface parity error response bit is set in the bridge control register. PI7C7100 sets the detected parity error bit in the secondary status register. PI7C7100 sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. PI7C7100 forwards the bad parity with the data back to the initiator on the primary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C7100 completes the transaction normally. For upstream transactions, when PI7C7100 detects a read data parity error on the primary bus, the following events occur: PI7C7100 asserts P_PERR# two cycles following the data transfer, if the primary interface parity error response bit is set in the command register. PI7C7100 sets the detected parity error bit in the primary status register. PI7C7100 sets the data parity detected bit in the primary status register, if the primary interface parity-errorresponse bit is set in the command register. PI7C7100 forwards the bad parity with the data back to the initiator on the secondary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C7100 completes the transaction normally. PI7C7100 returns to the initiator the data and parity that was received from the target. When the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition; therefore, when PI7C7100 detects PERR# asserted while returning read data to the initiator, PI7C7100 does not take any further action and completes the transaction normally. 7.2.3 Delayed Write Transactions When PI7C7100 detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity and conditionally asserts PERR#. For delayed write transactions, a parity error can occur at the following times: During the original delayed write request transaction When the initiator repeats the delayed write request transaction When PI7C7100 completes the delayed write transaction to the target When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When PI7C7100 detects a parity error on the write data for the initial delayed write request transaction, the following events occur: If the parity-error-response bit corresponding to the initiator bus is set, PI7C7100 asserts TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer, PI7C7100 also asserts PERR#. If the parity-error-response bit is not set, PI7C7100 returns a target retry. It queues the transaction as usual. PI7C7100 does not assert PERR#. In this case, the initiator repeats the transaction. PI7C7100 sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless of the state of the parity-error-response bit. 33 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus, it is possible that the initiators re-attempts of the write transaction may not match the original queued delayed write information contained in the delayed transaction queue. In this case, a master timeout condition may occur, possibly resulting in a system error (P_SERR# assertion). For downstream transactions, when PI7C7100 is delivering data to the target on the secondary bus and S_PERR# is asserted by the target, the following events occur: PI7C7100 sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. PI7C7100 captures the parity error condition to forward it back to the initiator on the primary bus. Similarly, for upstream transactions, when PI7C7100 is delivering data to the target on the primary bus and P_PERR# is asserted by the target, the following events occur: PI7C7100 sets the primary interface data-parity-detected bit in the status register, if the primary parity-errorresponse bit is set in the command register. PI7C7100 captures the parity error condition to forward it back to the initiator on the secondary bus. A delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. Note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. Two cases must be considered: When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not detected on the target bus When parity error is forwarded back from the target bus For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7100 has write status to return, the following events occur: PI7C7100 first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary interface parityerror-response bit is set in the command register. PI7C7100 sets the primary interface parity-error-detected bit in the status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7100 has write status to return, the following events occur: PI7C7100 first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two cycles later, if the secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch). PI7C7100 sets the secondary interface parity-error-detected bit in the secondary status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. For downstream transactions, where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: PI7C7100 asserts P_PERR# two cycles after the data transfer, if the following are both true: - The parity-error-response bit is set in the command register of the primary interface. - The parity-error-response bit is set in the bridge control register of the secondary interface. PI7C7100 completes the transaction normally. 34 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: PI7C7100 asserts S_PERR# two cycles after the data transfer, if the following are both true: - The parity error response bit is set in the command register of the primary interface. - The parity error response bit is set in the bridge control register of the secondary interface. PI7C7100 completes the transaction normally. 7.2.4 Posted Write Transactions During downstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error on the initiator (primary) bus, the following events occur: PI7C7100 asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set in the command register of primary interface. PI7C7100 sets the parity error detected bit in the status register of the primary interface. PI7C7100 captures and forwards the bad parity condition to the secondary bus. PI7C7100 completes the transaction normally. Similarly, during upstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error on the initiator (secondary) bus, the following events occur: PI7C7100 asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set in the bridge control register of the secondary interface. PI7C7100 sets the parity error detected bit in the status register of the secondary interface. PI7C7100 captures and forwards the bad parity condition to the primary bus. PI7C7100 completes the transaction normally. During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the targets assertion of S_PERR#, the following events occur: PI7C7100 sets the data parity detected bit in the status register of secondary interface, if the parity error response bit is set in the bridge control register of the secondary interface. PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following conditions are met: - The SERR# enable bit is set in the command register. - The posted write parity error bit of P_SERR# event disable register is not set. - The parity error response bit is set in the bridge control register of the secondary interface. - The parity error response bit is set in the command register of the primary interface. - PI7C7100 has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus. During upstream write transactions, when a data parity error is reported on the target (primary) bus by the targets assertion of P_PERR#, the following events occur: PI7C7100 sets the data parity detected bit in the status register, if the parity error response bit is set in the command register of the primary interface. PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following conditions are met: - The SERR# enable bit is set in the command register. - The parity error response bit is set in the bridge control register of the secondary interface. - The parity error response bit is set in the command register of the primary interface. - PI7C7100 has not detected the parity error on the secondary (initiator) bus which the parity error is not forwarded from the secondary bus to the primary bus. Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know that the error occurred. 35 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. If the parity error has forwarded from the initiating bus to the target bus, P_SERR# will not be asserted. 7.3 Data Parity Error Reporting Summary In the previous sections, the responses of PI7C7100 to data parity errors are presented according to the type of transaction in progress. This section organizes the responses of PI7C7100 to data parity errors according to the status bits that PI7C7100 sets and the signals that it asserts. Table 71 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This bit is set when PI7C7100 detects a parity error on the primary interface. Table 71 Setting the Primary Interface Detected Parity Error Bit Primary detected parity error bit 1 Transaction Ty pe B us where error was detected D irection 0 Read D ownstream Pri mary x/x1 0 Read D ownstream Secondary x/x 1 Read Upstream Pri mary x/x 0 Read Upstream Secondary x/x 1 Posted wri te D ownstream Pri mary x/x 0 Posted wri te D ownstream Secondary x/x 0 Posted wri te Upstream Pri mary x/x 0 Posted wri te Upstream Secondary x/x 1 D elayed wri te D ownstream Pri mary x/x 0 D elayed wri te D ownstream Secondary x/x 0 D elayed wri te Upstream Pri mary x/x 0 D elayed wri te Upstream Secondary x/x x =dont care 36 1 Primary /Secondary parity error response bits 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 Table 72 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C7100 detects a parity error on the secondary interface. Table 72. Setting Secondary Interface Detected Parity Error Bit Secondary detected parity error bit Transaction Ty pe B us where error was detected D irection Primary /Secondary parity error response bits 0 Read D ownstream Pri mary x/x1 1 Read D ownstream Secondary x/x 0 Read Upstream Pri mary x/x 0 Read Upstream Secondary x/x 0 Posted wri te D ownstream Pri mary x/x 0 Posted wri te D ownstream Secondary x/x 0 Posted wri te Upstream Pri mary x/x 1 Posted wri te Upstream Secondary x/x 0 D elayed wri te D ownstream Pri mary x/x 0 D elayed wri te D ownstream Secondary x/x 0 D elayed wri te Upstream Pri mary x/x 1 D elayed wri te Upstream Secondary x/x Table 73 shows setting data parity detected bit in the primary interfaces status register. This bit is set under the following conditions: PI7C7100 must be a master on the primary bus. The parity error response bit in the command register, corresponding to the primary interface, must be set. The P_PERR# signal is detected asserted or a parity error is detected on the primary bus. Table 73. Setting Primary Interface Data Parity Detected Bit Primary data parity bit Transaction Ty pe B us where error was detected D irection Primary /Secondary parity error response bits 0 Read D ownstream Pri mary x/x1 0 Read D ownstream Secondary x/x 1 Read Upstream Pri mary 1/x 0 Read Upstream Secondary x/x 0 Posted wri te D ownstream Pri mary x/x 0 Posted wri te D ownstream Secondary x/x 1 Posted wri te Upstream Pri mary 1/x 0 Posted wri te Upstream Secondary x/x 0 D elayed wri te D ownstream Pri mary x/x 0 D elayed wri te D ownstream Secondary x/x 1 D elayed wri te Upstream Pri mary 1/x 0 D elayed wri te Secondary x/x Upstream x =dont care 1 37 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Table 74 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: The PI7C7100 must be a master on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus. Table 74. Setting Secondary Interface Data Parity Detected Bit Secondary data parity detected bit 1 Transaction Ty pe B us where error was detected D irection Primary /Secondary parity error response bits 0 Read D ownstream Pri mary x/x1 1 Read D ownstream Secondary x/1 0 Read Upstream Pri mary x/x 0 Read Upstream Secondary x/x 0 Posted wri te D ownstream Pri mary x/x 1 Posted wri te D ownstream Secondary x/1 0 Posted wri te Upstream Pri mary x/x 0 Posted wri te Upstream Secondary x/x 0 D elayed wri te D ownstream Pri mary x/x 1 D elayed wri te D ownstream Secondary x/1 0 D elayed wri te Upstream Pri mary x/x 0 D elayed wri te Upstream Secondary x/x x =dont care 38 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 Table 75 shows assertion of P_PERR#. This signal is set under the following conditions: PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the primary bus. The parity-error-response bit must be set in the command register of primary interface. PI7C7100 detects a data parity error on the primary bus or detects S_PERR# asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus. Table 75. Assertion of P_PERR# P _P E R R # Transaction Ty pe B us where error was detected D irection Primary /Secondary parity error response bits 1 (de-asserted) Read D ownstream Pri mary x/x1 1 Read D ownstream Secondary x/x 0 (asserted) Read Upstream Pri mary 1/x 1 Read Upstream Secondary x/x 0 Posted wri te D ownstream Pri mary 1/x 1 Posted wri te D ownstream Secondary x/x 1 Posted wri te Upstream Pri mary x/x 1 Posted wri te Upstream Secondary x/x 0 D elayed wri te D ownstream Pri mary 1/x 02 D elayed wri te D ownstream Secondary 1/1 1 D elayed wri te Upstream Pri mary x/x 1 D elayed wri te Upstream Secondary x/x x =dont care The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 1 2 39 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Table 76 shows assertion of S_PERR# that is set under the following conditions: PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. PI7C7100 detects a data parity error on the secondary bus or detects P_PERR# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus. Table 76. Assertion of S_PERR# S _P E R R # 1 2 Transaction Ty pe B us where error was detected D irection Primary /Secondary parity error response bits 1 (de-asserted) Read D ownstream Pri mary x/x1 0 (asserted) Read D ownstream Secondary x/1 1 Read Upstream Pri mary x/x 1 Read Upstream Secondary x/x 1 Posted wri te D ownstream Pri mary x/x 1 Posted wri te D ownstream Secondary x/x 1 Posted wri te Upstream Pri mary x/x 0 Posted wri te Upstream Secondary x/1 1 D elayed wri te D ownstream Pri mary x/x 1 D elayed wri te D ownstream Secondary x/x 02 D elayed wri te Upstream Pri mary 1/1 0 D elayed wri te Upstream Secondary x/1 x =dont care The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 40 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 Table 77 shows assertion of P_SERR#. This signal is set under the following conditions: PI7C7100 has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted on a downstream posted write transaction. PI7C7100 did not detect the parity error as a target of the posted write transaction. The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. The SERR# enable bit must be set in the command register. Table 77. Assertion of P_SERR# for Data Parity Errors P _S E R R # Transaction Ty pe B us where error was detected D irection Primary /Secondary parity error response bits 1 (de-asserted) Read D ownstream Pri mary x/x1 1 Read D ownstream Secondary x/x 1 Read Upstream Pri mary x/x 1 Read Upstream Secondary x/x 1 Posted wri te D ownstream Pri mary x/x Posted wri te D ownstream Secondary 1/1 03 Posted wri te Upstream Pri mary 1/1 1 Posted wri te Upstream Secondary x/x 1 D elayed wri te D ownstream Pri mary x/x 1 D elayed wri te D ownstream Secondary x/x 1 D elayed wri te Upstream Pri mary x/x 1 D elayed wri te Upstream Secondary x/x 02 (asserted) x =dont care The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus. 1 2 41 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 7.4 System Error (SERR#) Reporting PI7C7100 uses the P_SERR# signal to report conditionally a number of system error conditions in addition to the special case parity error conditions described in Section 7.2.3. Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following conditions apply: For PI7C7100 to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register. Whenever PI7C7100 asserts P_SERR#, PI7C7100 must also set the signaled system error bit in the status register. In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7100 asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit is set in the bridge control register. In addition, PI7C7100 also sets the received system error bit in the secondary status register. PI7C7100 also conditionally asserts P_SERR# for any of the following reasons: Target abort detected during posted write transaction Master abort detected during posted write transaction Posted write data discarded after 224(default) attempts to deliver (224 target re3es received) Parity error reported on target bus during posted write transaction (see previous section) Delayed write data discarded after 224(default) attempts to deliver (224 target re3es received) Delayed read data cannot be transferred from target after 224(default) attempts (224 target re3es received) Master timeout on delayed transaction The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most of these events have additional device-specific disable bits in the P_SERR# event disable register that make it possible to mask out P_SERR# assertion for specific events. The master timeout condition has a SERR# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit. 42 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 8. Exclusive Access This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross PI7C7100. 8.1 Concurrent Locks The primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses PI7C7100. A primary master can lock a primary target without affecting the status of the lock on the secondary bus, and vice versa. This means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target. 8.2 Acquiring Exclusive Access across PI7C7100 For any PCI bus, before acquiring access to the LOCK# signal and starting a series of locked transactions, the initiator must first check that both of the following conditions are met: The PCI bus must be idle. The LOCK# signal must be de-asserted. The initiator leaves the LOCK# signal de-asserted during the address phase and asserts LOCK# one clock cycle later. Once a data transfer is completed from the target, the target lock has been achieved. Locked transactions can cross PI7C7100 in the downstream and upstream directions, from the primary bus to the secondary bus and vice versa. When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the targets bus. When PI7C7100 detects on the primary bus, an initial locked transaction intended for a target on the secondary bus, PI7C7100 samples the address, transaction type, byte enable bits, and parity, as described in Section 4.6.4. It also samples the lock signal. If there is a lock established between 2 ports or the target bus is already locked by another master, then the current lock cycle is re3ed without forward. Because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. The first locked transaction must be a read transaction. Subsequent locked transactions can be read or write transactions. Posted memory write transactions that are a part of the locked transaction sequence are still posted. Memory read transactions that are a part of the locked transaction sequence are not pre-fetched. When the locked delayed read request is queued, PI7C7100 does not queue any more transactions until the locked sequence is finished. PI7C7100 signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the other side of PI7C7100. PI7C7100 allows any transactions queued before the locked transaction to complete before initiating the locked transaction. When the locked delayed read request transaction moves to the head of the delayed transaction queue, PI7C7100 initiates the transaction as a locked read transaction by de-asserting LOCK# on the target bus during the first address phase, and by asserting LOCK# one cycle later. If LOCK# is already asserted (used by another initiator), PI7C7100 waits to request access to the secondary bus until LOCK# is de-asserted when the target bus is idle. Note that the existing lock on the target bus could not have crossed PI7C7100. Otherwise, the pending queued locked transaction would not have been queued. When PI7C7100 is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, PI7C7100 transfers the read data back to the initiator, and the lock is then also established on the primary bus. For PI7C7100 to recognize and respond to the initiator, the initiators subsequent attempts of the read transaction must use the locked transaction sequence (de-assert LOCK# during address phase, and assert LOCK# one cycle later). If the LOCK# sequence is not used in subsequent attempts, a master timeout condition may result. When a master timeout condition occurs, SERR# is conditionally asserted (see Section 7.4), the read data and queued read transaction are discarded, and the LOCK# signal is de-asserted on the target bus. 43 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are forwarded by PI7C7100 are driven as locked transactions on the target bus. When PI7C7100 receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target or the initiator bus. PI7C7100 resumes forwarding unlocked transactions in both directions. 8.3 Ending Exclusive Access After the lock has been acquired on both initiator and target buses, PI7C7100 must maintain the lock on the target bus for any subsequent locked transactions until the initiator relinquishes the lock. The only time a target-retry causes the lock to be relinquished is on the first transaction of a locked sequence. On subsequent transactions in the sequence, the target retry has no effect on the status of the lock signal. An established target lock is maintained until the initiator relinquishes the lock. PI7C7100 does not know whether the current transaction is the last one in a sequence of locked transactions until the initiator de-asserts the LOCK# signal at end of the transaction. When the last locked transaction is a delayed transaction, PI7C7100 has already completed the transaction on the secondary bus. In this example, as soon as PI7C7100 detects that the initiator has relinquished the LOCK# signal by sampling it in the de-asserted state while FRAME# is de-asserted, PI7C7100 de-asserts the LOCK# signal on the target bus as soon as possible. Because of this behavior, LOCK# may not be de-asserted until several cycles after the last locked transaction has been completed on the target bus. As soon as PI7C7100 has de-asserted LOCK# to indicate the end of a sequence of locked transactions, it resumes forwarding unlocked transactions. When the last locked transaction is a posted write transaction, PI7C7100 de-asserts LOCK# on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus. When PI7C7100 receives a target abort or a master abort in response to a locked delayed transaction, PI7C7100 returns a target abort or a master abort when the initiator repeats the locked transaction. The initiator must then de-assert LOCK# at the end of the transaction. PI7C7100 sets the appropriate status bits, flagging the abnormal target termination condition (see Section 4.8). Normal forwarding of unlocked posted and delayed transactions is resumed. When PI7C7100 receives a target abort or a master abort in response to a locked posted write transaction, PI7C7100 cannot pass back that status to the initiator. PI7C7100 asserts SERR# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register. Signal SERR# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see Section 7.4). 44 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 9. PCI Bus Arbitration PI7C7100 must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to PI7C7100, typically on the motherboard. For the secondary PCI bus, PI7C7100 implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus arbitration. 9.1 Primary PCI Bus Arbitration PI7C7100 implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary PCI bus arbitration. PI7C7100 asserts P_REQ# when forwarding transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed transaction requests, PI7C7100 keeps P_REQ# asserted. However, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by PI7C7100 on the primary PCI bus, PI7C7100 de-asserts P_REQ# for two PCI clock cycles. For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been completely queued. When P_GNT# is asserted LOW by the primary bus arbiter after PI7C7100 has asserted P_REQ#, PI7C7100 initiates a transaction on the primary bus during the next PCI clock cycle. When P_GNT# is asserted to PI7C7100 when P_REQ# is not asserted, PI7C7100 parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is parked at PI7C7100 and PI7C7100 has a transaction to initiate on the primary bus, PI7C7100 starts the transaction if P_GNT# was asserted during the previous cycle. 9.2 Secondary PCI Bus Arbitration PI7C7100 implements an internal secondary PCI bus arbiter. This arbiter supports two sets of eight external masters in addition to PI7C7100. The internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus arbitration. 9.2.1 Secondary Bus Arbitration Using the Internal Arbiter To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied LOW. PI7C7100 has two sets of eight secondary bus request input pins, S1_REQ#[7:0], S2_REQ#[7:0], and two sets of eight secondary bus output grant pins, S1_GNT#[7:0], S2_GNT#[7:0], to support external secondary bus masters. The secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when S_CFN# is HIGH. The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 8 requests/ grants. Each set of masters can be assigned to a high priority group and a low priority group. The low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the highest priority is assigned to the low priority group. Priority rotates evenly among the low priority group. Therefore, members of the high priority group can be serviced n transactions out of n+1, while one member of the low priority group is serviced once every n+1 transactions. Figure 91 shows an example of an internal arbiter where four masters, including PI7C7100, are in the high priority group, and five masters are in the low priority group. Using this example, if all requests are always asserted, the highest priority rotates among the masters in the following fashion (high priority members are given in italics, low priority members, in boldface type): B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7 and so on. m2 m1 lpg m4 m3 m0 B m5 m7 m6 Figure 9-1. Secondary Arbiter Example 45 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Each bus master, including PI7C7100, can be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the arbiter-control register. The arbiter-control register is located at offset 40h. Each master has a corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If the bit is set to 0, the master is assigned to the low priority group. If all the masters are assigned to one group, the algorithm defaults to a straight rotating priority among all the masters. After reset, all external masters are assigned to the low priority group, and PI7C7100 is assigned to the high priority group. PI7C7100 receives highest priority on the target bus every other transaction, and priority rotates evenly among the other masters. Priorities are re-evaluated every time S1_FRAME# or S2_FRAME# is asserted at the start of each new transaction on the secondary PCI bus. From this point until the time that the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. If a grant for a particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant corresponding to the new higher priority request on the next PCI clock cycle. When priorities are re-evaluated, the highest priority is assigned to the next highest priority master relative to the master that initiated the previous transaction. The master that initiated the last transaction now has the lowest priority in its group. If PI7C7100 detects that an initiator has failed to assert S1_FRAME# or S2_FRAME# after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant. That master does not receive any more grants until it de-asserts its request for at least one PCI clock cycle. To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is, either S1_FRAME# (S2_FRAME#) or S1_IRDY# (S2_IRDY#) is asserted, the arbiter can de-assert one grant and assert another grant during the same PCI clock cycle. 9.2.2 Secondary Bus Arbitration Using an External Arbiter The internal arbiter is disabled when the secondary bus central function control pin, S_CFN#, is tied high. An external arbiter must then be used. When S_CFN# is tied high, PI7C7100 reconfigures four pins (two per port) to be external request and grant pins. The S1_GNT#[0] and S2_GNT#[0] pins are reconfigured to be the external request pins because they are output. The S1_REQ#[0] and S2_REQ#[0] pins are reconfigured to be the external grant pins because they are input. When an external arbiter is used, PI7C7100 uses the S1_GNT#[0] or S2_GNT#[0] pin to request the secondary bus. When the reconfigured S1_REQ#[0] or S2_REQ#[0] pin is asserted low after PI7C7100 has asserted S1_GNT#[0] or S2_GNT#[0]. PI7C7100 initiates a transaction on the secondary bus one cycle later. If grant is asserted and PI7C7100 has not asserted the request, PI7C7100 parks AD, CBE and PAR pins by driving them to valid logic levels. The unused secondary bus grant outputs, S1_GNT#[7:1] and S2_GNT#[7:1] are driven high. The unused secondary bus request inputs, S1_REQ#[7:1] and S2_REQ#[7:1], should be pulled high. 9.2.3 Bus Parking Bus parking refers to driving the AD[31:0], CBE[3:0]#, and PAR lines to a known value while the bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted, and the devices request is not asserted. The AD and CBE signals should be driven first, with the PAR signal driven one cycle later. PI7C7100 parks the primary bus only when P_GNT# is asserted, P_REQ# is de-asserted, and the primary PCI bus is idle. When P_GNT# is de-asserted, PI7C7100 3-states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C7100 is parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C7100 can start the transaction on the next PCI clock cycle by asserting P_FRAME# if P_GNT# is still asserted. If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, PI7C7100 keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. After reset, PI7C7100 parks the secondary bus at itself until transactions start occurring on the secondary bus. If the internal arbiter is disabled, PI7C7100 parks the secondary bus only when the reconfigured grant signal, S_REQ#<0>, is asserted and the secondary bus is idle. 46 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 10. Clocks This chapter provides information about the clocks. 10.1 Primary Clock Inputs PI7C7100 implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the secondary clock. The secondary clock is derived internally from the primary clock, P_CLK, through an internal PLL. PI7C7100 operates at a maximum frequency of 33 MHz. 10.2 Secondary Clock Outputs PI7C7100 has 16 secondary clock outputs, S_CLKOUT[15:0] that can be used as clock inputs for up to sixteen external secondary bus devices. The S_CLKOUT[15:0] outputs are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of 0ns. This is the rule for using secondary clocks: Each secondary clock output is limited to no more than one load. 47 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 11. Reset This chapter describes the primary interface, secondary interface, and chip reset mechanisms. 11.1 Primary Interface Reset PI7C7100 has a reset input, P_RESET#. When P_RESET# is asserted, the following events occur: PI7C7100 immediately 3-states all primary and secondary PCI interface signals. PI7C7100 performs a chip reset. Registers that have default values are reset. P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLK. 11.2 Secondary Interface Reset PI7C7100 is responsible for driving the secondary bus reset signals, S1_RESET# and S2_RESET#. PI7C7100 asserts S1_RESET# or S2_RESET# when any of the following conditions is met: Signal P_RESET# is asserted. Signal S1_RESET# or S2_RESET# remains asserted as long as P_RESET# is asserted and does not de-assert until P_RESET# is de-asserted. The secondary reset bit in the bridge control register is set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit. S1_RESET# or S2_RESET# pin is asserted. When S1_RESET# or S2_RESET# is asserted, the following events occur: PI7C7100 immediately 3-states all the secondary PCI interface signals associated with the Secondary S1 or S2 port. The S1_RESET# or S2_RESET# in asserting and de-asserting edges can be asynchronous to P_CLK. The chip reset bit in the diagnostic control register is set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit and the secondary clock serial mask has been shifted in. When S1_RESET# or S2_RESET# is asserted, all secondary PCI interface control signals, including the secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S1_PAR (S2_AD, S2_CBE[3:0]#, S2_PAR) are driven low for the duration of S1_RESET# (S2_RESET#) assertion. All posted write and delayed transaction data buffers are reset. Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. When S1_RESET# or S2_RESET# is asserted by means of the secondary reset bit, PI7C7100 remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface. 11.3 Chip Reset The chip reset bit in the diagnostic control register can be used to reset PI7C7100 and the secondary buses. All registers, and chip state machines are reset and all signals are 3-stated when the chip reset is set. In addition, S1_RESET# or S2_RESET# is asserted, and the secondary reset bit is automatically set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit. As soon as chip reset completes, within 20 PCI clock cycles after completion of the configuration write operation that sets the chip reset bit, the chip reset bit automatically clears and the chip is ready for configuration. During chip reset, PI7C7100 is inaccessible. 48 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 12. Supported Commands The PCI command set is given below for the primary and secondary interfaces. 12.1 Primary Interface P_C B E[3: 0]# C ommand Action 0000 Interrupt Acknowledge Ignore. 0001 Speci al C ycle D o not clai m. Ignore. 0010 I/O Read 1. If address i s wi thi n pass through I/O range: clai m and pass through. 2. If address poi nts to I/O mapped bri dge i nternal regi ster: clai m and permi t access to regi ster, do not pass through. 3. Otherwi se, do not pass through and do not clai m for i nternal access. 0011 I/O Wri te Same as I/O read. 0100 Reserved ----- 0101 Reserved ----- 0110 Memory Read 1. If address i s wi thi n pass through memory range: clai m and pass through. 2. If address i s wi thi n pass through memory mapped I/O range: clai m and pass through. 3. If address poi nts to memory mapped bri dge i nternal regi ster: clai m and permi t access to regi ster, do not pass through. 4. Otherwi se, do not pass through and do not clai m for i nternal access. 0111 Memory Wri te Same as Memory Read 1000 Reserved ----- 1001 Reserved ----- 1010 C onfi gurati on Read I. Ty pe 0 configuration read: If the bri dge's ID SEL li ne i s asserted, perform functi on decode and clai m i f target functi on i s i mplemented, otherwi se, i gnore. If clai med, permi t access to target functi on's confi gurati on regi sters. D o not pass through under any ci rcumstances. II. Ty pe 1 configuration read: 1. If the target bus i s the bri dge's secondary bus: clai m and pass through as a type 0 confi gurati on read. 2. If the target bus i s a subordi nate bus that exi sts behi nd the bri dge (but not equal to the secondary bus): clai m and pass through as a type 1 confi gurati on read. 3. Otherwi se, i gnore. 49 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12.1 Primary Interface P_C B E[3: 0]# C ommand Action 1011 C onfi gurati on Wri te I. Ty pe 0 configuration write: same as configuration read. II. Ty pe 1 configuration write(not special cy cle request): 1. If the target bus i s the bri dge's secondary bus: clai m and pass through as a type 0 confi gurati on wri te 2. If the target bus i s a subordi nate bus that exi sts behi nd the bri dge (but not equal to the secondary bus): clai m and pass through unchanged as a type 1 confi gurati on wri te. 3. Otherwi se, i gnore. III. C onfiguration write as special cy cle request (dev ice = 1Fh, function = 7h): 1. If the target bus i s the bri dge's secondary bus: clai m and pass through as a speci al cycle 2. If the target bus i s a subordi nate bus that exi sts behi nd the bri dge (but not equal to the secondary bus): clai m and pass through unchanged as a type 1 confi gurati on wri te. 3. Otherwi se, i gnore 1100 Memory Read Multi ple Same as Memory Read 1101 D ual Address C ycle Not Supported 1110 Memory Read Li ne Same as Memory Read 1111 Memory Wri te & Invali date Same as Memory Read 50 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 12.2 Secondary Interface S1_C B E[3: 0]# S2_C B E[3: 0]# C ommand Action 0000 Interrupt Acknowledge Ignore. 0001 Speci al C ycle D o not clai m. Ignore. 0010 I/O Read Same as pri mary i nterface. 0011 I/O Wri te Same as I/O read. 0100 Reserved ----- 0101 Reserved ----- 0110 Memory Read Same as pri mary i nterface. 0111 Memory Wri te Same as Memory Read. 1000 Reserved ----- 1001 Reserved ----- 1010 C onfi gurati on Read Ignore. 1011 C onfi gurati on Wri te I. Ty pe 0 configuration write: Ignore. II. Ty pe 1 configuration write (not special cy cle request): Ignore. III. C onfiguration write as special cy cle request (dev ice = 1Fh, function = 7h): 1. If the target bus i s the bri dge's pri mary bus: clai m and pass through as a speci al cycle. 2. If the target bus i s nei ther the pri mary bus nor i s i t i n range of buses defi ned by the bri dge's secondary and subordi nate bus regi sters: clai m and pass through unchanged as a type 1 confi gurati on wri te. 3. If the target bus i s not the bri dge's pri mary bus: but i s i n range of buses defi ned by the bri dge's secondary and subordi nate bus regi sters: Ignore. 1100 Memory Read Multi ple Same as Memory Read 1101 D ual Address C ycle Not Supported 1110 Memory Read Li ne Same as Memory Read 1111 Memory Wri te & Invali date Same as Memory Read 51 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 13. Configuration Registers As PI7C7100 supports two secondary interfaces, it has two sets of configuration registers which are almost identical and accessed through different function numbers. The description below is for one set only. PCI configuration defines a 64-byte space (configuration header) to define various at3butes of the PCI-to-PCI Bridge as shown below. All of the registers in bold type are required by the PCI specification and are implemented in this bridge. The others are available for use as control registers for the device. There are two configuration registers: Configuration Register 1 and Configuration Register 2 corresponding to Secondary bus 1 and Secondary bus 2 interfaces respectively. Also, the configuration for the primary interface is implemented through the Configuration Register 1. 13.1 Configuration Register 1 31-24 23-16 15-8 7-0 D ev ice ID Vendor ID Status 00h C ommand 04h C lass C ode Reserved H eader Ty pe Secondary Latency Timer Subordinate B us N umber Address R ev ision ID 08h C ache Line Siz e 0C h Secondary B us N umber Primary B us N umber 18h I/O Limit I/O B ase 1C h Primary Latency Timer Reserved 10h-14h Secondary Status Memory Limit Memory B ase 20h Prefetchable Memory Li mi t Prefetchable Memory Base 24h I/O Li mi t Upper 16 Bi ts I/O Base Upper 16 Bi ts 30h Subsystem ID Subsystem Vendor ID 34h Reserved 28h-2C h Reserved 38h B ridge C ontrol Interrupt Pi n Reserved 3C h Arbi ter C ontrol D i agnosti c C ontrol C hi p C ontrol 40h Pri mary Prefetchable Memory Li mi t Pri mary Prefetchable Memory Base Reserved 48h-60h Reserved Reserved 44h P_SERR# Event D i sable Reserved 64h Secondary C lock C ontrol 68h Non-Posted Memory Base 70h Port Opti on 74h Reserved 6C h Non-Posted Memory Li mi t Master Ti meout C ounter Retry C ounter 78h Sampli ng Ti mer 7C h Secondary Successful I/O read count 80h Secondary Successful I/O wri te count 84h Secondary Successful memory read count 88h Secondary Successful memory wri te count 8C h Pri mary Successful I/O read count 90h Pri mary Successful I/O wri te count 94h Pri mary Successful memory read count 98h Pri mary Successful memory wri te count 9C h Reserved A0h-FFh 52 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 13.2 Configuration Register 2 31-24 23-16 15-8 7-0 Address D ev ice ID Vendor ID 00h Status C ommand 04h C lass C ode H eader Ty pe Reserved Primary Latency Timer R ev ision ID 08h C ache Line Siz e 0C h Reserved Secondary Latency Timer Subordinate B us N umber 10h-14h Secondary B us N umber Primary B us N umber 18h I/O Limit I/O B ase 1C h Secondary Status Memory Limit Memory B ase 20h Prefetchable Memory Li mi t Prefetchable Memory Base 24h Reserved 28h-2C h I/O Li mi t Upper 16 Bi ts I/O Base Upper 16 Bi ts 30h Subsystem ID Subsystem Vendor ID 34h Reserved 38h B ridge C ontrol Interrupt Pi n Reserved 3C h Arbi ter C ontrol D i agnosti c C ontrol C hi p C ontrol 40h Pri mary Prefetchable Memory Li mi t Reserved Pri mary Prefetchable Memory Base 44h Reserved 48h-60h Reserved 64h Reserved Secondary C lock C ontrol Reserved 68h 6C h Non-Posted Memory Li mi t Non-Posted Memory Base 70h Reserved Reserved 74h Reserved 78h Sampli ng Ti mer 7C h Secondary Successful I/O read count 80h Secondary Successful I/O wri te count 84h Secondary Successful memory read count 88h Secondary Successful memory wri te count 8C h Reserved 90h Reserved 94h Reserved 98h Reserved 9C h Reserved A0h-FFh 53 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 13.2.1 Config Register 1 or 2: Vendor ID Register (read only, bit 15-0; offset 00h) Pericom ID is 12D8h. 13.2.2 Config Register 1: Device ID Register (read only, bit 31-16; offset 00h) Hardwired to 1B59h (S1) 13.2.3 Config Register 2: Device ID Register (read only, bit 31-16; offset 00h) Hardwired to 1B5Ah (S2) 13.2.4 Configuration Register 1: Command Register (bit 15-0; offset 04h) B it 15-10 9 Function Ty pe Reserved R/O Reset to '000000' Fast Back to Back Enable R/W C ontrols bri dge's abi li ty to generate fast back-to-back transacti ons to di fferent devi ces on the pri mary i nterface. 0 = no fast back to back transaction 1 = enable fast back to back transacti on R eset to 0 SERR# Enable R/W C ontrols the enable for the P_SERR# pi n. 0=disable the P_SER R # driv er 1 = enable the P_SERR# dri ver R eset to 0 Wai t C ycle C ontrol R/O No data steppi ng supported. R eset to 0 Pari ty Error Enable R/W C ontrols bri dge's response to pari ty errors. 0 = ignore any parity errors 1 = normal pari ty checki ng performed R eset to 0 VGA Palette Snoop Enable R/W C ontrols bri dge's response to VGA compati ble palette accesses. 0 = ignore VGA palette accesses on the primary interface 1 = enable response to VGA palette wri tes on the pri mary i nterface (I/O address AD [9:0] = 3C 6h, 3C 8h and 3C 9h) R eset to 0 Memory Wri te and Invali date Enable R/O Memory Wri te and Invali date not supported R eset to 0 Speci al C ycle Enable R/O No speci al cycle i mplementati on R eset to 0 Bus Master Enable R/W C ontrols bri dge's abi li ty to operate as a master on the pri mary i nterface. 0 = do not initiate transaction on the primary interface and disable response to memory or I/O transactions on secondary interface 1 = enable the bri dge to operate as a master on the pri mary i nterface R eset to 0 Memory Space Enable R/W C ontrols bri dge's response to memory accesses on the pri mary i nterface. 0 = ignore all memory transaction 1 = enable response to memory transacti on R eset to 0 I/O Space Enable R/W C ontrols bri dge's response to I/O accesses on the pri mary i nterface. 0 = ignore I/O transaction 1 = enable response to I/O transacti on R eset to 0 8 7 6 5 4 3 2 1 0 D escription Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear 54 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 13.2.5 Configuration Register 2: Command Register (bit 15-0; offset 04h) B it Function Ty pe D escription 15-10 Reserved R/O R eset to '000000' 9 Reserved R/W R eset to 0 8 Reserved R/W R eset to 0 Wai t C ycle C ontrol R/O No data steppi ng supported. R eset to 0 Reserved R/W R eset to 0 VGA Palette Snoop Enable R/W C ontrols bri dge's response to VGA compati ble palette accesses. 0 = ignore VGA palette accesses on the primary interface 1 = enable response to VGA palette wri tes on the pri mary i nterface (I/O address AD [9:0] = 3C 6h, 3C 8h and 3C 9h) R eset to 0 4 Memory Wri te and Invali date Enable R/O Memory Wri te and Invali date not supported. R eset to 0 3 Speci al C ycle Enable R/O No speci al cycle i mplementati on. R eset to 0 Bus Master Enable R/W C ontrols bri dge's abi li ty to operate as a master on the pri mary i nterface. 0 = do not initiate transaction on the primary interface and disable response to memory or I/O transactions on secondary interface 1 = enable the bri dge to operate as a master on the pri mary i nterface R eset to 0 7 6 5 2 Memory Space Enable R/W C ontrols bri dge's response to memory accesses on the pri mary i nterface. 0 = ignore all memory transaction 1 = enable response to memory transacti on R eset to 0 I/O Space Enable C ontrols bri dge's response to I/O accesses on the pri mary i nterface. 0 = ignore I/O transaction 1 = enable response to I/O transacti on R eset to 0 1 0 R/W Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear 55 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 13.2.6 Configuration Register 1 or 2: Status Register (for primary bus, bits 31-16; offset 04h) B it Function Ty pe D escription 31 D etected Pari ty Error R/WC Should be set whenever a pari ty error i s detected regardless of the state of bi t 6 of the command regi ster. R eset to 0 30 Si gnaled System Error R/WC Should be set whenever P_SERR# i s asserted. R eset to 0 29 Recei ved Master Abort R/WC Set to '1' (by a master) when transacti ons are termi nated wi th Master Abort. R eset to 0 28 Recei ved Target Abort R/WC Set to '1' (by a master devi ce) when transacti ons are termi nated wi th Target Abort. R eset to 0 27 Si gnaled Target Abort R/WC Should be set (by a target devi ce) whenever a Target Abort cycle occurs. R eset to 0 D EVSEL Ti mi ng R/O 24 D ata Pari ty Error D etected R/WC It i s set when the followi ng condi ti ons are met: 1. P_PERR# i s asserted 2. Bi t 6 of C ommand Regi ster i s set R eset to 0 23 Fast Back to Back C apable R/O Fast back-to-back wri te capable on pri mary si de. R eset to 1 22 Reserved R/O R eset to 0 21 Reserved R/O R eset to 1 20 C apabi li ti es Li st R/O C apabi li ti es Li st i s not supported. R eset to 0 Reserved R/O R eset to 0 26-25 19-16 Medi um D EVSEL# ti mi ng. R eset to '01' Note: R/W - Read/Write; R/O - Read Only; R/WC - Read/Write1 to clear. 56 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 13.2.7 Config Register 1 or 2: Revision ID Register (read only, bit 7-0; offset 08h) Hardwired to 01h 13.2.8 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h) Hardwired to 060400h 13.2.9 Config Register 1 or 2: Cache Line Size Register (read/write, bit 7-0; offset 0Ch) This register is used when terminating memory write and invalidate transactions and when pre-fetching. Only cache line sizes (in units of 4-byte) which are power of two are valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, 10h are valid values). Reset to 00h 13.2.10 Config Register 1: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) This register sets the value for Master Latency Timer which starts counting when master asserts FRAME#. Reset to 00h 13.2.11 Config Register 2: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) This register is implemented but not being used internally. Reset to 00h 13.2.12 Config Register 1: Header Type Register (read only, bit 23-16; offset 0Ch) Hardwired to 81h for function 0 (multiple function PCI-to-PCI bridge, for secondary bus S1) 13.2.13 Config Register 2: Header Type Register (read only, bit 23-16; offset 0Ch) Hardwired to 01h for function 1 (single function PCI-to-PCI bridge, for secondary bus S2) 13.2.14 Config Register 1: Primary Bus Number Register (read/write, bit 7-0; offset 18h) Programmed with the number of the PCI bus to which the primary bridge interface is connected. This value is set by software during configuration. Reset to 00h 13.2.15 Config Register 2: Primary Bus Number Register (read/write, bit 7-0; offset 18h) This register is implemented but not being used internally. Reset to 00h 13.2.16 Config Register 1 or 2: Secondary Bus Number Register (read/write, bit 15-8; offset 18h) Programmed with the number of the PCI bridge secondary bus interface. This value is set by software during configuration. Reset to 00h 13.2.17 Config Register 1 or 2: Subordinate Bus Number Register (read/write, bit 23-16; offset 18h) Programmed with the number of the PCI bus with the highest number that is subordinate to the bridge. This value is set by software during configuration. Reset to 00h 13.2.18 Config Register 1 or 2: Secondary Latency Timer (read/write, bit 31-24; offset 18h) This register is programmed in units of PCI bus clocks.The latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. Reset to 00h 13.2.19 Config Register 1 or 2: I/O Base Register (read/write, bit 7-0; offset 1Ch) This register defines the bottom address of the I/O address range for the bridge. The upper four bits define the bottom address range used by the chip to determine when to forward I/O transactions from one interface to the other. These 4 bits correspond to address bits [15:12] and are write-able. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base upper 16 bits address register. The address bits [11:0] are assumed to be 000h. The lower four bits (3:0) of this register set to 0001 (read-only) to indicate 32-bit I/O addressing. Reset to 00h 13.2.20 Config Register 1 or 2: I/O Limit Register (read/write, bit 15-8; offset 1Ch) This register defines the top address of the I/O address range for the bridge. The upper four bits define the top address range used by the chip to determine when to forward I/O transactions from one interface to the other. These 4 bits correspond to address bits [15:12] and are write-able. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O limit upper 16 bits address register. The address bits [11:0] are assumed to be FFFh. The lower four bits (3:0) of this register set to 0001 (read-only) to indicate 32-bit I/O addressing. Reset to 00h. 57 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 13.2.21 Configuration Register 1 or 2: Secondary Status Register (bits 31-16; offset 1Ch) B it Function Ty pe D escription 31 D etected Pari ty Error R/WC Should be set whenever a pari ty error i s detected regardless of the state of bi t 6 of the command regi ster. R eset to 0 30 Si gnaled System Error R/WC Should be set whenever S1_SERR# or S2_SERR# i s detected. Should be a '0' after reset. R eset to 0 29 Recei ved Master Abort R/WC Set to '1' (by a master) when transacti ons are termi nated wi th Master Abort. R eset to 0 28 Recei ved Target Abort R/WC Set to '1' (by a master devi ce) when transacti ons are termi nated wi th Target Abort. R eset to 0 27 Si gnaled Target Abort R/WC Should be set (by a target devi ce) whenever a Target Abort cycle occurs. Should be '0' after reset. R eset to 0 R/O Medi um D EVSEL# ti mi ng. R eset to '01' 26-25 D EVSEL ti mi ng 24 D ata Pari ty Error D etected R/WC It i s set when the followi ng condi ti ons are met: 1. S1_PERR# or S2_PERR# i s asserted 2. Bi t 6 of C ommand Regi ster i s set R eset to 0 23 Fast Back-to-Back C apable R/O Fast back-to-back wri te capable on secondary buses. R eset to 1 22 Reserved R/O R eset to 0 21 Reserved R/O R eset to 0 20-16 Reserved R/O R eset to '00000' Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear 58 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 13.2.22 Config Register 1 or 2: Memory Base Register (read/write, bit 15-0; offset 20h) This register defines the base address of the memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The twelve bits are reset to 000h. The lower 20 address bits (19:0) are assumed to be 00000h. 13.2.23 Config Register 1 or 2: Memory Limit Register (read/write, bit 31:16; offset 20h) This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bridge. Upper twelve bits corresponding to address bit [31:20] are read/write. Upper twelve bits are reset to 0000h. Lower 20 address bits (19:0) are assumed to be FFFFFh. 13.2.24 Config Register 1 or 2: Prefetchable Memory Base Register (read/write, bit 15-0;offset 24h) This register defines the base address of the prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 000h. The lower four bits are read only and are set to 0. The lower 20 address bits (19:0) are assumed to be 00000h. 13.2.25 Config Register 1 or 2: Prefetchable Memory Limit Register (read/write, bit 31-16; offset 24h) This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits correspond to address bit [31:20] are read/write. The upper twelve bits are reset to 000h. The lower four bits are read only and are set to 0. The lower 20 address bits (19:0) are assumed to be FFFFFh. 13.2.26 Config Register 1 or 2: I/O Base Address Upper 16 Bits Register (read/write, bit 15-0; offset 30h) This register defines the upper 16 bits of a 32-bit base I/O address range used for forwarding the cycle through the bridge. Reset to 0000h. 13.2.27 Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register (read/write, bit 31-16; offset 30h) This register defines the upper 16 bits of a 32-bit limit I/O address range used for forwarding the cycle through the bridge. Reset to 0000h. 13.2.28 Config Register 1 or 2: Subsystem Vendor ID (read/write, bit 15-0; offset 34h) A 16-bit register for add-on cards to distinguish from one another. Reset to 0000h. 13.2.29 Config Register 1 or 2: Subsystem ID (read/write, bit 31-16; offset 34h) A 16-bit register for add-on cards to distinguish from one another. Reset to 0000h. 13.2.30 Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch) The register reads as 00h to indicate that PI7C7100 does not use any interrupt pins. 59 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 13.2.31 Configuration Register 1 or 2: Bridge Control Register (bits 31-16; offset 3Ch) B it Function 31-28 Reserved Ty pe D escription R/O R eset to '0000' 27 Reserved R/W R eset to 0 26 Master Ti meout Status R/WC Set to '1' when ei ther pri mary master or secondary master ti meout. R eset to 0 25 Reserved R/W R eset to 0 24 Reserved R/W R eset to 0 23 Fast Back-to-Back Enable R/W C ontrols bri dge's abi li ty to generate fast back-to-back transacti ons to different devi ces on the secondary i nterface. 0 = no fast back-to-back transaction 1 = enable fast back-to-back transacton R eset to 0 22 Secondary Interface Reset R/W Forces the asserti on of S1_RESET# or S2_RESET# si gnal pi n on the secondary i nterface. 0 = do not force the assertion of S1_R ESET# or S2_R ESET# pin 1 = force the asserti on of S1_RESET# or S2_RESET# pi n R eset to 0 21 Master Abort Mode R/W C ontrols bri dge's behavi or respondi ng to master aborts on secondary i nterface. 0 = do not report master aborts (return FFFF_FFFFh on read and discard data on write) 1 = report master aborts by si gnali ng target abort i f possi ble by the asserti on of P_SERR# i f enabled R eset to 0 20 Reserved R/O R eset to 0 19 VGA Enable R/W C ontrols the bri dge's response to VGA compati ble addresses. 0 = do not forward VGA compatible memory and I/O addresses from primary to secondary 1 = forward VGA compati ble memory and I/O address from pri mary to secondary regardless of other setti ngs R eset to 0 18 ISA Enable R/W C ontrols bri dge's response to ISA I/O address whi ch i s li mi ted to the fi rst 64K. 0 = forward all I/O addresses in the range defined by the I/O B ase and I/O Limit registers, 1 = block forwardi ng of ISA I/O addresses i n the range defi ned by the I/O Base and I/O Li mi t regi sters that are i n the fi rst 64K of I/O space that address the last 768 bytes i n each 1 Kbytes block. Secondary I/O transacti ons are forwarded upstream i f the address falls wi thi n the last 768 bytes i n each 1 Kbyte block R eset to 0 17 S1_SERR# or S2_SERR# Enable C ontrols the forwardi ng of S1_SERR# or S2_SERR# to the pri mary i nterface. 0 = disable the forwarding S1_SER R # or S2_SER R # to primary 1 = enable the forwardi ng of S1_SERR# or S2_SERR# to pri mary i nterface. R eset to 0 16 Pari ty Error Response Enable C ontrols the bri dge's response to pari ty errors on the secondary i nterface. 0 = ignore address and data parity errors on the secondary interface. 1 = enable pari ty error reporti ng and detecti on on the secondary i nterface. R eset to 0 Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear. 60 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 13.2.32 Configuration Register 1 or 2: Diagnostic/Chip Control Register (bit 15-0, offset 40h) B it Function Ty pe D escription 15-11 Reserved R/O R eset to '00000' 10-9 Test Mode R/W C ontrols testabi li ty of chi p's i nternal counters. When 00, all bi ts of counter are exerci sed. When 01, byte 1 of counter i s exerci sed. When 10, byte 2 of counter i s exerci sed. When 11, byte 3 of counter i s exerci sed. R eset to 0 8-5 Reserved R/O R eset to '0000' 4 Reserved R/W R eset to 0 3-2 Reserved R/O R eset to '00' 1 Reserved R/W R eset to 0 0 Reserved R/O R eset to 0 13.2.33 Configuration Register 1 or 2: Arbiter Control Register (bit 31-16, offset 40h) B it 31:28 Function Ty pe D escription Reserved R/O R eset to '0000' 27 Hybri d R/W Mi xed arbi trati on for masters from secondary bus 1 and 2. 0 = separate arbi trati on for S1_REQ[7:0]# and S2_REQ[7:0]# 1 = S1_REQ[3:0]# are mi xed wi th S2_REQ[3:0]# for arbi trati on. Only one arbi ter i s used. R eset to 0 26 Reserved R/W R eset to 0 25 Pri ori ty of Secondary Port R/W D efi nes whether the secondary port of PI7C 7100 i s i n hi gh pri ori ty group or the low pri ori ty group. 0 = low pri ori ty group 1 = high priority group R eset to 1 24 Reserved R/O R eset to 0 Arbi ter C ontrol R/W Each bi t controls whether a secondary-bus master i s assi gned to the hi gh pri ori ty group or the low pri ori ty group. Bi t [7:0] correspond to request i nputs S1_REQ[7:0]# or S2_REQ[7:0]#. R eset to '00000000' 23-16 Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear. 61 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 13.2.34 Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) This register defines the base address of the primary prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h. The lower 20 address bits (19:0) are assumed to be 00000h. 13.2.35 Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) This register is implemented but not being used internally. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h. 13.2.36 Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) This register defines the upper limit address of the primary prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h. The lower 20 address bits (19:0) are assumed to be FFFFFh. 13.2.37 Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) This register is implemented but not being used internally. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h. 13.2.38 Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h) B it Function Ty pe D escription 7 Reserved R/O R eset to 0 6 D elayed read no data from target R/W C ontrols abi li ty of PI7C 7100 to assert P_SERR# when i t i s unable to transfer any read data from the target after 224 attempts. P_SERR# i s asserted i f thi s event occurs when thi s bi t i s 0 and SERR# enable bi t i n the command regi ster i s set. R eset to 0 5 D elayed wri te nondeli ver R/W C ontrols abi li ty of PI7C 7100 to assert P_SERR# when i t i s unable to transfer delayed wri te data after 224 attempts. P_SERR# i s asserted i f thi s event occurs when thi s bi t i s 0 and SERR# enable bi t i n the command regi ster i s set. R eset to 0 4 Master abort on posted wri te R/W C ontrols abi li ty of PI7C 7100 to assert P_SERR# when i t recei ves a master abort when attempti ng to deli ver posted wri te data. P_SERR# i s asserted i f thi s event occurs when thi s bi t i s 0 and SERR# enable bi t i n the command regi ster i s set. R eset to 0 3 Target abort duri ng posted wri te R/W C ontrols abi li ty of PI7C 7100 to assert P_SERR# when i t recei ves a target abort when attempti ng to deli ver posted wri te data. P_SERR# i s asserted i f thi s event occurs when thi s bi t i s 0 and SERR# enable bi t i n the command regi ster i s set. R eset to 0 2 Posted wri te non-deli very R/W C ontrols abi li ty of PI7C 7100 to assert P_SERR# when i t i s unable to deli ver posted wri te data after 224 attempts. P_SERR# i s asserted i f thi s event occurs when thi s bi t i s 0 and SERR# enable bi t i n the command regi ster i s set. R eset to 0 1 Posted wri te pari ty error R/W C ontrols abi li ty of PI7C 7100 to assert P_SERR# when a pari ty error i s detected on the target bus duri ng a posted wri te transacti on. P_SERR# i s asserted i f thi s event occurs when thi s bi t i s 0 and SERR# enable bi t i n the command regi ster i s set. R eset to 0 0 Reserved R/O R eset to 0 Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear. 62 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 13.2.39 Configuration Register 1: Secondary Clock Control Register (bit 15-0; offset 68h) B it 15-14 13-12 11-10 9-8 7-6 5-4 3-2 1-0 Function Ty pe D escription C lock 7 D i sable If ei ther bi t i s 0, S_C LKOUT[7] i s enabled When both bi ts are 1, S_C LKOUT[7] i s di sabled C lock 6 D i sable If ei ther bi t i s 0, S_C LKOUT[6] i s enabled When both bi ts are 1, S_C LKOUT[6] i s di sabled C lock 5 D i sable If ei ther bi t i s 0, S_C LKOUT[5] i s enabled When both bi ts are 1, S_C LKOUT[5] i s di sabled C lock 4 D i sable If ei ther bi t i s 0, S_C LKOUT[4] i s enabled When both bi ts are 1, S_C LKOUT[4] i s di sabled R/W C lock 3 D i sable If ei ther bi t i s 0, S_C LKOUT[3] i s enabled When both bi ts are 1, S_C LKOUT[3] i s di sabled C lock 2 D i sable If ei ther bi t i s 0, S_C LKOUT[2] i s enabled When both bi ts are 1, S_C LKOUT[2] i s di sabled C lock 1 D i sable If ei ther bi t i s 0, S_C LKOUT[1] i s enabled When both bi ts are 1, S_C LKOUT[1] i s di sabled C lock 0 D i sable If ei ther bi t i s 0, S_C LKOUT[0] i s enabled When both bi ts are 1, S_C LKOUT[0] i s di sabled 13.2.40 Configuration Register 2: Secondary Clock Control Register (bit 15-0; offset 68h) B it 15-14 13-12 11-10 9-8 7-6 5-4 3-2 1-0 Function Ty pe D escription C lock 7 D i sable If ei ther bi t i s 0, S_C LKOUT[15] i s enabled When both bi ts are 1, S_C LKOUT[15] i s di sabled C lock 6 D i sable If ei ther bi t i s 0, S_C LKOUT[14] i s enabled When both bi ts are 1, S_C LKOUT[14] i s di sabled C lock 5 D i sable If ei ther bi t i s 0, S_C LKOUT[13] i s enabled When both bi ts are 1, S_C LKOUT[13] i s di sabled C lock 4 D i sable If ei ther bi t i s 0, S_C LKOUT[12] i s enabled When both bi ts are 1, S_C LKOUT[12] i s di sabled R/W C lock 3 D i sable If ei ther bi t i s 0, S_C LKOUT[11] i s enabled When both bi ts are 1, S_C LKOUT[11] i s di sabled C lock 2 D i sable If ei ther bi t i s 0, S_C LKOUT[10] i s enabled When both bi ts are 1, S_C LKOUT[10] i s di sabled C lock 1 D i sable If ei ther bi t i s 0, S_C LKOUT[9] i s enabled When both bi ts are 1, S_C LKOUT[9] i s di sabled C lock 0 D i sable If ei ther bi t i s 0, S_C LKOUT[8] i s enabled When both bi ts are 1, S_C LKOUT[8] i s di sabled Note: R/W - Read/Write. 63 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 13.2.41 Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h) This register defines the base address of the non-posted memory-mapped address range for forwarding the cycle through the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed to be 00000h. 13.2.42 Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h) This register defines the upper limit address of the non-posted memory-mapped address range for forwarding the cycle through the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed to be FFFFFh. 13.2.43 Configuration Register 1: Port Option Register (bit 15-0; offset74h) B it Function Ty pe D escription R/O R eset to '000' R/W Enable 1 more read for MEMR command on pri mary 1 = Enable 0 = N o ch an g e R/O R eset to '00' R/W Enable Long request for lock cycle 0 = N o ch an g e 1 = Enable R/W Reset Secondary D elayed Transacti on Queue 0 = N o ch an g e 1 = R eset Reserved R/O Reset to '00' 5 ID Wri te Enable R/W Allow wri te to Vendor ID , D evi ce ID , Subsystem Vendor ID and Subsystem ID i n the confi gurati on space. 0 = Write protect 1 = Wri te enable R eset to 0 4 Secondary MEMW C ommand Ali as Enable R/W C ontrols the bri dge's detecti on mechani sm for matchi ng non-posted memory wri te retry cycle from i ni ti ator on secondary i nterface. 0 = C ommand has to be exact 1 = MEMW i s equi valent to MEMWI R eset to 0 3 Secondary MEMR C ommand Ali as Enable R/W C ontrols the bri dge's detecti on mechani sm for matchi ng memory read retry cycle from i ni ti ator on secondary i nterface. 0=C ommand has to be exact 1=MEMR i s equi valent to MEMRL or MEMRM R eset to 0 2 Pri mary MEMW C ommand Ali as Enable R/W C ontrols the bri dge's detecti on mechani sm for matchi ng non-posted memory wri te retry cycle from i ni ti ator on pri mary i nterface. 0 = C ommand has to be exact 1 = MEMW i s equi valent to MEMWI R eset to 0 1 Pri mary MEMR C ommand Ali as Enable R/W C ontrols the bri dge's detecti on mechani sm for matchi ng memory read retry cycle from i ni ti ator on pri mary i nterface. 0 = C ommand has to be exact 1 = MEMR i s equi valent to MEMRL or MEMRM R eset to 0 0 Secondary Pre Read R/W Enable 1 more read for MEMR command on secondary. 0 = disable 1 = enable R eset to 0 15-13 12 11-10 9 8 7-6 Reserved Pri mary Pre Read Reserved Enable Long Request Reset D TQUEUE 64 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 13.2.44 Configuration Register 2: Port Option Register (bit 15-0; offset74h) B it Function Ty pe D escription 15-13 Reserved R/O R eset to '000' 12 Reserved R/W R eset to 0 11-10 Reserved R/O R eset to '00' 9-8 Reserved R/W R eset to '00' 7-6 Reserved R/O R eset to '00' 5 ID Wri te Enable R/W Allow wri te to Vendor ID , D evi ce ID , Subsystem Vendor ID , and Subsystem ID i n the confi gurati on space. 0 = Write protect 1 = Wri te enable R eset to 0 4 Secondary MEMW C ommand Ali as Enable R/W C ontrols the bri dge's detecti on mechani sm for matchi ng non-posted memory wri te retry cycle from i ni ti ator on secondary i nterface. 0 = C ommand has to be exact 1 = MEMW i s equi valent to MEMWI R eset to 0 3 Secondary MEMR C ommand Ali as Enable R/W C ontrols the bri dge's detecti on mechani sm for matchi ng memory read retry cycle from i ni ti ator on secondary i nterface. 0=C ommand has to be exact 1=MEMR i s equi valent to MEMRL or MEMRM R eset to 0 2 Reserved R/W R eset to 0 1 Reserved R/W R eset to 0 0 Secondary Pre Read R/W Enable 1 more read for MEMR command on secondary. 0 = disable 1 = enable R eset to 0 65 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 13.2.45 Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h) This register holds the maximum number of PCI clocks that PI7C7100 will wait for initiator to retry the same cycle before reporting timeout. Default is 8000h. 13.2.46 Config Register 1 or 2: Retry Counter Register (read/write, bit 31-0; offset 78h) This register holds the maximum number of attempts that PI7C7100 will try before reporting retry timeout. Default is 0100_0000h. 13.2.47 Config Register 1 or 2: Sampling Timer Register (read/write, bit 31-0; offset 7Ch) This register set the duration (in PCI clocks) during which PI7C7100 will record the number of successful transactions for performance evaluation. The recording will start right after this register is programmed and will be cleared after the timer expires. The maximum period is 128 seconds. Reset to 0000_0000h. 13.2.48 Config Register 1 or 2: Successful I/O Read Count Register (read/write, bit 31-0; offset 80h) This register stores the successful I/O read count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h. 13.2.49 Config Register 1 or 2: Successful I/O Write Count Register (read/write, bit 31-0; offset 84h) This register stores the successful I/O write count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h. 13.2.50 Config Register 1 or 2: Successful Memory Read Count Register (read/write, bit 31-0; offset 88h) This register stores the successful memory read count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h. 13.2.51 Config Register 1 or 2: Successful Memory Write Count Register (read/write, bit 31-0; offset 8Ch) This register stores the successful memory write count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h. 13.2.52 Config Register 1: Primary Successful I/O Read Count Register (read/write, bit 31-0; offset 90h) This register stores the successful I/O read count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h. 13.2.53 Config Register 1: Primary Successful I/O Write Count Register (read/write, bit 31-0; offset 94h) This register stores the successful I/O write count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h. 13.2.54 Config Register 1: Primary Successful Memory Read Count Register (read/write, bit 31-0; offset 98h) This register stores the successful memory read count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h. 13.2.55 Config Register 1: Primary Successful Memory Write Count Register (read/write, bit 31-0; offset 9Ch) This register stores the successful memory write count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h. 66 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 14. Bridge Behavior A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number of possibilities. Those possibilities are summarized in the table below: 14.1 Bridge Actions for Various Cycle Types Initiator Target R esp o n se Master on pri mary Target on Pri mary PI7C 7100 does not respond. It detects thi s si tuati on by decodi ng the address as well as moni tori ng the P_D EVSEL# for other fast and medi um devi ces on the pri mary port. Master on pri mary Target on secondary PI7C 7100 asserts P_D EVSEL#, termi nates the cycle normally i f i t i s able to be posted, otherwi se returns wi th a retry. It then passes the cycle to the appropri ate port. When the cycle i s complete on the target port, i t wi ll wai t for the i ni ti ator to repeat the same cycle and end wi th normal termi nati on. Master on pri mary Target not on pri mary nor secondary port PI7C 7100 does not respond and the cycle wi ll termi nate as master abort. Master on secondary Target on the same secondary port PI7C 7100 does not respond. Master on secondary Target on pri mary or the other secondary port PI7C 7100 asserts S1_D EVSEL# or S2_D EVSEL#, termi nates the cycle normally i f i t i s able to be posted, otherwi se returns wi th a retry. It then passes the cycle to the appropri ate port. When cycle i s complete on the target port, i t wi ll wai t for the i ni ti ator to repeat the same cycle and end wi th normal termi nati on. Master on secondary Target not on pri mary nor the other secondary PI7C 7100 does not respond. A target then has up to three cycles to respond before subtractive decoding is initiated. If the target detects an address hit, it should assert its DEVSEL# signal in the cycle corresponding to the values of bits 9 and 10 in the Configuration Status Register. Termination of a PCI cycle can occur in a number of ways. Normal termination begins by the initiator (master) de-asserting FRAME# with IRDY# being asserted (or remaining asserted) on the same cycle. The cycle completes when TRDY# and IRDY# are both asserted simultaneously. The target should de-assert TRDY# for one cycle following final assertion (sustained 3-state signal). 14.2 Transaction Ordering To maintain data coherency and consistency, PI7C7100 complies with the ordering rules put forth in the PCI Local Bus Specification, Rev 2.1. The following table summarizes the ordering relationship of all the transactions through the bridge. PMW - Posted write (either memory write or memory write & invalidate) DRR - Delayed read request (all memory read, I/O read & configuration read) DWR - Delayed write request (I/O write & configuration write) DRC - Delayed read completion (all memory read, I/O read & configuration read) DWC - Delayed write completion (I/O write & configuration write ) 67 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Cycle type shown on each row is the subsequent cycle after the previous shown on the column. C an R ow pass C olumn? PMW C olumn 1 DRR C olumn 2 D WR C olumn 3 DRC C olumn 4 D WC C olumn 5 PMW (Row 1) No Yes Yes Yes Yes D RR (Row 2) No No No Yes Yes D WR (Row 3) No No No Yes Yes D RC (Row 4) No Yes Yes No No D WC (Row 5) Yes Yes Yes No No In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must complete on the target bus in the order in which they were received in the initiator bus. In Row 2 Column 1, DRR cannot pass the previous PMW and that means the previous PMW heading to the same direction must be completed before the DRR can be attempted on the target bus. In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches the head of the delayed transaction queue. 14.3 Abnormal Termination (Initiated by Bridge Master) 14.3.1 Master Abort Master abort indicates that when PI7C7100 acts as a master and receives no response (i.e., no target asserts P_DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the bridge de-asserts FRAME# and then de-asserts IRDY#. 14.3.2 Parity and Error Reporting Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, S1_PAR, and S2_PAR signals. Parity should be even (i.e. an even number of 1s) across AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For reads, even parity must be generated using the initiators CBE signals combined with the read data. Again, the PAR signal corresponds to read data from the previous data phase cycle. 14.3.3 Reporting Parity Errors For all address phases, if a parity error is detected, the error should be reported on the P_SERR# signal by asserting P_SERR# for one cycle and then 3-stating two cycles after the bad address. P_SERR# can only be asserted if bit 6 and 8 in the Command Register are both set to 1. For write data phases, a parity error should be reported by asserting the P_PERR# signal two cycles after the data phase and should remain asserted for one cycle when bit 8 in the Command register is set to a 1. The target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master Abort. When the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a Master Abort. 14.3.4 Secondary IDSEL mapping When PI7C7100 detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device number. This is translated to S1_AD[31:16] or S2_AD[31:16] by PI7C7100. 68 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 15. IEEE 1149.1 Compatible JTAG Controller An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C7100 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST#. All digital input, output, input/output pins are tested except TAP pins and clock pin. The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass, Device Identification and Boundary Scan registers. The TAP controller is a synchronous 16 state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles. PI7C7100 implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, EXTEST. 15.1 Boundary Scan Architecture Boundary-scan test logic consists of a boundary-scan register and support logic. These are accessed through a Test Access Port (TAP). The TAP provides a simple serial interface that allows all processor signal pins to be driven and/or sampled, thereby providing direct control and monitoring of processor pins at the system level. This mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not normally accessible to the test system. The following subsections describe the boundary-scan test logic elements: TAP pins, instruction register, test data registers and TAP controller. Figure 15-1 illustrates how these pieces fit together to form the JTAG unit. TAP Pins PI7C7100 System Pins TDI Instruction Register Boundary-Scan Register TDO Bypass Register TMS TCK TAP Controller Control and Clock Signals TRST# 15.1.1 TAP Pins Figure 15-1. Test Access Port Block Diagram The PI7C7100s TAP pins form a serial port composed of four input connections (TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins are described in Table 15-1. The TAP pins provide access to the instruction register and the test data registers. 15.1.2 Instruction Register The Instruction Register (IR) holds instruction codes. These codes are shifted in through the Test Data Input (TDI) pin. The instruction codes are used to select the specific test operation to be performed and the test data register to be accessed. The instruction register is a parallel-loadable, master/slave-configured 2-bit wide, serial-shift register with latched outputs. Data is shifted into and out of the IR serially through the TDI pin clocked by the rising edge of TCK. The shifted-in instruction becomes active upon latching from the master stage to the slave stage. At that time the IR outputs along with the TAP finite state machine outputs are decoded to select and control the test data register selected by that instruction. Upon latching, all actions caused by any previous instructions terminate. 69 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 The instruction determines the test to be performed, the test data register to be accessed, or both. The IR is two bits wide. When the IR is selected, the most significant bit is connected to TDI, and the least significant bit is connected to TDO. The value presented on the TDI pin is shifted into the IR on each rising edge of TCK. The TAP controller captures fixed parallel data (01 binary ). When a new instruction is shifted in through TDI, the value 01 (binary) is always shifted out through TDO, least significant bit first. This helps identify instructions in a long chain of serial data from several devices. Upon activation of the TRST# reset pin, the latched instruction asynchronously changes to the idcode instruction. When the TAP controller moves into the test state other than by reset activation, the opcode changes as TDI shifts, and becomes active on the falling edge of TCK. 15.2 Boundary-Scan Instruction Set The PI7C7100 supports three mandatory boundary-scan instructions (bypass, sample/preload and extest). The table shown below lists the PI7C7100s boundary-scan instruction codes. The reserved code should not be used. Instruction C ode (binary ) Instruction N ame Instruction C ode (binary ) Instruction N ame 00 extest 10 reserved 01 sample/preload 11 bypass Table 15-1. TAP Pins Instruction / R equisite Opcode (binary ) D escription extest IEEE 1149.1 Requi red 00 Extest i ni ti ates testi ng of external ci rcui try, typi cally board-level i nterconnects and off chi p ci rcui try. extest connects the boundary-scan regi ster between TD I and TD O. When Extest i s selected, all output si gnal pi n values are dri ven by values shi fted i nto the boundary-scan regi ster and may change only on the falli ng edge of TC K. Also, when extest i s selected, all system i nput pi n states must be loaded i nto the boundary-scan regi ster on the ri si ng-edge of TC K. sample/ preload IEEE 1149.1 Requi red 01 Sample/preload performs two functi ons: A snapshot of the sample i nstructi on i s captured on the ri si ng edge of TC K wi thout i nterferi ng wi th normal operati on. The i nstructi on causes boundary-scan regi ster cells associ ated wi th outputs to sample the value bei ng dri ven. On the falli ng edge of TC K the data held i n the boundary-scan cells i s transferred to the slave regi ster cells. Typi cally the slave latched data i s appli ed to the system outputs vi a the extest i nstructi on. i d co d e IEEE 1149.1 Opti onal 10 Reserved bypass IEEE 1149.1 Requi red 11 Bypass i nstructi on selects the one-bi t bypass regi ster between TD I and TD O pi ns. 0 (bi nary) i s the only i nstructi on that accesses the bypass regi ster. Whi le thi s i nstructi on i s i n effect, all other test data regi sters have no effect on system operati on. Test data regi sters wi th both test and system functi onali ty perform thei r system functi ons when thi s i nstructi on i s selected. 70 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 15.3 TAP Test Data Registers The PI7C7100 contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data registers most significant bit. TDO is connected to the least significant bit. Data is shifted one bit position within the register towards TDO on each rising edge of TCK. While any register is selected, data is transferred from TDI to TDO without inversion. The following sections describe each of the test data registers. 15.4 Bypass Register The required bypass register, a one-bit shift register, provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C7100. 15.5 Boundary-Scan Register The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high-impedance pin. Table 15-2 shows the bit order of the PI7C7100 boundary-scan register. All table cells that contain Control select the direction of bidirectional pins or high-impedance output pins. When a 0 is loaded into the control cell, the associated pin(s) are high-impedance or selected as input. The boundary-scan register is a required set of serial-shiftable register cells, configured in master/slave stages and connected between each of the PI7C7100s pins and on-chip system logic. The VDD, GND, PLL, AGND, AVDD and JTAG pins are NOT in the boundary-scan chain. The boundary-scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary-scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory sample/ preload and extest instructions. Parallel loading takes place on the rising edge of TCK. Data may be scanned into the boundary-scan register serially via the TDI serial input pin, clocked by the rising edge of TCK. When the required data has been loaded into the master-cell stages, it can be driven into the system logic at input pins or onto the output pins on the falling edge of TCK state. Data may also be shifted out of the boundary-scan register by means of the TDO serial output pin at the falling edge of TCK. 15.6 TAP Controller The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that controls the sequence of test logic operations. The TAP can be controlled via a bus master. The bus master can be either automatic test equipment or a component (i.e., PLD) that interfaces to the TAP. The TAP controller changes state only in response to a rising edge of TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls the sequence of state changes. The TAP controller is initialized after power-up by applying a low to the TRST# pin. In addition, the TAP controller can be initialized by applying a high signal level on the TMS input for a minimum of five TCK periods. For greater detail on the behavior of the TAP controller, test logic in each controller state and the state machine and public instructions, refer to the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture document (available from the IEEE). 71 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Table 15-2. JTAG Boundary Register Order Order Pin Names Type Order Pin Names Type Order Pin Names Type 1 S2_AD[20-31] co ntro l e nab le 36 S2_AD[26] inp ut 71 BYPASS inp ut 2 S2_AD[21] o utp ut 37 S2_AD[28] o utp ut 72 FLUSH# inp ut 3 S2_AD[21] inp ut 38 S2_AD[28] inp ut 73 P_RESET# inp ut 4 S2_PERR# co ntro l e nab le 39 S2_AD[27] o utp ut 74 P_GNT# inp ut 5 S2_PERR# o utp ut 40 S2_AD[27] inp ut 75 P_REQ# co ntro l e nab le 6 S2_PERR# inp ut 41 S2_AD[29] o utp ut 76 P_REQ# o utp ut 7 S2_AD[8-19] co ntro l e nab le 42 S2_AD[29] inp ut 77 P_AD[20-31] co ntro l e nab le 8 S2_AD[16] o utp ut 43 S2_AD[30] o utp ut 78 P_AD[30] o utp ut 9 S2_AD[16] inp ut 44 S2_AD[30] inp ut 79 P_AD[30] inp ut 10 S2_FRAME# co ntro l e nab le 45 S2_AD[31] o utp ut 80 P_AD[31] o utp ut 11 S2_FRAME# o utp ut 46 S2_AD[31] inp ut 81 P_AD[31] inp ut 12 S2_FRAME# inp ut 47 S2_GNT[0]# co ntro l e nab le 82 P_AD[27] o utp ut 13 S2_DEVSEL# /S2_TRDY# co ntro l e nab le 48 S2_GNT[0]# o utp ut 83 P_AD[27] inp ut 14 S2_DEVSEL# o utp ut 49 S2_REQ[0]# inp ut 84 P_AD[26] o utp ut 15 S2_DEVSEL# inp ut 50 S2_REQ[1]# inp ut 85 P_AD[26] inp ut 16 S2_AD[19] o utp ut 51 S2_GNT[1]# o utp ut 86 P_AD[28] o utp ut 17 S2_AD[19] inp ut 52 S2_GNT[2]# o utp ut 87 P_AD[28] inp ut 18 S2_AD[17] o utp ut 53 S2_REQ[2]# inp ut 88 P_AD[29] o utp ut 19 S2_AD[17] inp ut 54 S2_REQ[3]# inp ut 89 P_AD[29] inp ut 20 S2_AD[18] o utp ut 55 S2_GNT[3]# o utp ut 90 P_CBE[0-3] co ntro l e nab le 21 S2_AD[18] inp ut 56 S2_GNT[4]# o utp ut 91 P_CBE[3] o utp ut 22 S2_AD[20] o utp ut 57 S2_REQ[4]# inp ut 92 P_CBE[3] inp ut 23 S2_AD[20] inp ut 58 S2_REQ[5]# inp ut 93 P_AD[24] o utp ut 24 S2_AD[22] o utp ut 59 S2_GNT[5]# o utp ut 94 P_AD[24] inp ut 25 S2_AD[22] inp ut 60 S2_GNT[6]# o utp ut 95 P_AD[25] o utp ut 26 S2_AD[24] o utp ut 61 S2_REQ[6]# inp ut 96 P_AD[25] inp ut 27 S2_AD[24] inp ut 62 S2_REQ[7]# inp ut 97 P_AD[23] o utp ut 28 S2_AD[23] o utp ut 63 S2_GNT[7]# o utp ut 98 P_AD[23] inp ut 29 S2_AD[23] inp ut 64 S2_RESET# o utp ut 99 P_AD[22] o utp ut 30 S2_CBE[0-3] co ntro l e nab le 65 S_CFN# inp ut 100 P_AD[22] inp ut 31 S2_CBE[3] o utp ut 66 S1_EN# inp ut 101 P_IDSEL inp ut 32 S2_CBE[3] inp ut 67 S2_EN# inp ut 102 P_AD[21] o utp ut 33 S2_AD[25] o utp ut 68 SCAN_TM# inp ut 103 P_AD[21] inp ut 34 S2_AD[25] inp ut 69 SCAN_EN inp ut 104 P_AD[20] o utp ut 35 S2_AD[26] o utp ut 70 PLL_TM inp ut 105 P_AD[20] inp ut 72 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 Table 15-2. JTAG Boundary Register Order Order Pin Names Type Order Pin Names Type (continued) Order Pin Names Type 106 P_AD[8-19] co ntro l e nab le 141 P_AD[14] o utp ut 176 P_AD[3] o utp ut 107 P_AD[19] o utp ut 142 P_AD[14] inp ut 177 P_AD[3] inp ut 108 P_AD[19] inp ut 143 P_AD[11] o utp ut 178 P_AD[4] o utp ut 109 P_AD[18] o utp ut 144 P_AD[11] inp ut 179 P_AD[4] inp ut 110 P_AD[18] inp ut 145 P_AD[15] o utp ut 180 S1_AD[0-7] co ntro l e nab le 111 P_AD[17] o utp ut 146 P_AD[15] inp ut 181 S1_AD[0] o utp ut 112 P_AD[17] inp ut 147 P_AD[12] o utp ut 182 S1_AD[0] inp ut 113 P_AD[16] o utp ut 148 P_AD[12] inp ut 183 S1_AD[1] o utp ut 114 P_AD[16] inp ut 149 P_AD[8] o utp ut 184 S1_AD[1] inp ut 115 P_CBE[2] o utp ut 150 P_AD[8] inp ut 185 S1_AD[2] o utp ut 116 P_CBE[2] inp ut 151 P_CBE[1] o utp ut 186 S1_AD[2] inp ut 117 P_FRAME# co ntro l e nab le 152 P_CBE[1] inp ut 187 S1_AD[5] o utp ut 118 P_FRAME# o utp ut 153 P_AD[9] o utp ut 188 S1_AD[5] inp ut 119 P_FRAME# inp ut 154 P_AD[9] inp ut 189 S1_AD[3] o utp ut 120 P_IRDY# co ntro l e nab le 155 P_AD[0-7] co ntro l e nab le 190 S1_AD[3] inp ut 121 P_IRDY# o utp ut 156 P_AD[5] o utp ut 191 S1_AD[4] o utp ut 122 P_IRDY# inp ut 157 P_AD[5] inp ut 192 S1_AD[4] inp ut 123 P_DEVSEL/P_TRDY# co ntro l e nab le 158 P_M66EN inp ut 193 S1_CBE[0-3] co ntro l e nab le 124 P_TRDY# o utp ut 159 P_AD[6] o utp ut 194 S1_CBE[0] o utp ut 125 P_TRDY# inp ut 160 P_AD[6] inp ut 195 S1_CBE[0] inp ut 126 P_DEVSEL# o utp ut 161 P_AD[2] o utp ut 196 S1_AD[7] o utp ut 127 P_DEVSEL# inp ut 162 P_AD[2] inp ut 197 S1_AD[7] inp ut 128 P_STOP# co ntro l e nab le 163 P_PAR co ntro l e nab le 198 S1_AD[6] o utp ut 129 P_STOP# o utp ut 164 P_PAR o utp ut 199 S1_AD[6] inp ut 130 P_STOP# inp ut 165 P_PAR inp ut 200 S1_AD[8-19] co ntro l e nab le 131 P_PERR# co ntro l e nab le 166 P_AD[0] o utp ut 201 S1_AD[8] o utp ut 132 P_PERR# o utp ut 167 P_AD[0] inp ut 202 S1_AD[8] inp ut 133 P_PERR# inp ut 168 P_CBE[0] o utp ut 203 S1_AD[9] o utp ut 134 P_LOCK# co ntro l e nab le 169 P_CBE[0] inp ut 204 S1_AD[9] inp ut 135 P_LOCK# o utp ut 170 P_AD[7] o utp ut 205 S1_AD[10] o utp ut 136 P_LOCK# inp ut 171 P_AD[7] inp ut 206 S1_AD[10] inp ut 137 P_SERR# co ntro l e nab le 172 P_AD[10] o utp ut 207 S1_AD[11] o utp ut 138 P_SERR# o utp ut 173 P_AD[10] inp ut 208 S1_AD[11] inp ut 139 P_AD[13] o utp ut 174 P_AD[1] o utp ut 209 S1_AD[12] o utp ut 140 P_AD[13] inp ut 175 P_AD[1] inp ut 210 S1_AD[12] inp ut 73 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Table 15-2. JTAG Boundary Register Order Order Pin Names Type Order Pin Names Type (continued) Order Pin Names Type 211 S1_AD[14] o utp ut 246 S1_AD[16]# inp ut 281 S1_GNT[0]# o utp ut 212 S1_AD[14] inp ut 247 S1_AD[20-31] co ntro l e nab le 282 S1_REQ[0]# inp ut 213 S1_AD[13] o utp ut 248 S1_AD[20] o utp ut 283 S1_REQ[1]# inp ut 214 S1_AD[13] inp ut 249 S1_AD[20] inp ut 284 S1_GNT[1]# o utp ut 215 S1_AD[15] o utp ut 250 S1_CBE[2] o utp ut 285 S1_GNT[2]# o utp ut 216 S1_AD[15] inp ut 251 S1_CBE[2] inp ut 286 S1_REQ[2]# inp ut 217 S1_SERR# inp ut 252 S1_AD[19] o utp ut 287 S1_REQ[3]# inp ut 218 S1_PAR co ntro l e nab le 253 S1_AD[19] inp ut 288 S1_GNT[3]# o utp ut 219 S1_PAR o utp ut 254 S1_CBE[3] o utp ut 289 S1_GNT[4]# o utp ut 220 S1_PAR inp ut 255 S1_CBE[3] inp ut 290 S1_REQ[4]# inp ut 221 S1_CBE[1] o utp ut 256 S1_AD[23] o utp ut 291 S1_REQ[5]# inp ut 222 S1_CBE[1] inp ut 257 S1_AD[23] inp ut 292 S1_GNT[5]# o utp ut 223 S1_DEVSEL# /S1_TRDY# co ntro l e nab le 258 S1_AD[26] o utp ut 293 S1_GNT[6]# o utp ut 224 S1_DEVSEL# o utp ut 259 S1_AD[26] inp ut 294 S1_REQ[6]# inp ut 225 S1_DEVSEL# inp ut 260 S1_AD[22] o utp ut 295 S1_REQ[7]# inp ut 226 S1_STOP# co ntro l e nab le 261 S1_AD[22] inp ut 296 S1_GNT[7]# o utp ut 227 S1_STOP# o utp ut 262 S1_AD[25] o utp ut 297 S1_RESET# o utp ut 228 S1_STOP# inp ut 263 S1_AD[25] inp ut 298 S2_AD[0-7] co ntro l e nab le 229 S1_LOCK# co ntro l e nab le 264 S1_AD[29] o utp ut 299 S2_AD[0] o utp ut 230 S1_LOCK# o utp ut 265 S1_AD[29] inp ut 300 S2_AD[0] inp ut 231 S1_LOCK# inp ut 266 S1_AD[21] o utp ut 301 S2_AD[1] o utp ut 232 S1_PERR# co ntro l e nab le 267 S1_AD[21] inp ut 302 S2_AD[1] inp ut 233 S1_PERR# o utp ut 268 S1_AD[28] o utp ut 303 S2_AD[2] o utp ut 234 S1_PERR# inp ut 269 S1_AD[28] inp ut 304 S2_AD[2] inp ut 235 S1_FRAME# co ntro l e nab le 270 S1_AD[30] o utp ut 305 S2_AD[3] o utp ut 236 S1_FRAME# o utp ut 271 S1_AD[30] inp ut 306 S2_AD[3] inp ut 237 S1_FRAME# inp ut 272 S1_AD[31] o utp ut 307 S2_AD[4] o utp ut 238 S1_IRDY# co ntro l e nab le 273 S1_AD[31] inp ut 308 S2_AD[4] inp ut 239 S1_IRDY# o utp ut 274 S1_AD[27] o utp ut 309 S2_AD[5] o utp ut 240 S1_IRDY# inp ut 275 S1_AD[27] inp ut 310 S2_AD[5] inp ut 241 S1_TRDY# o utp ut 276 S1_AD[24] o utp ut 311 S2_AD[6] o utp ut 242 S1_TRDY# inp ut 277 S1_AD[24] inp ut 312 S2_AD[6] inp ut 243 S1_AD[17]# o utp ut 278 S1_AD[18] o utp ut 313 S2_AD[7] o utp ut 244 S1_AD[17]# inp ut 279 S1_AD[18] inp ut 314 S2_AD[7] inp ut 245 S1_AD[16]# o utp ut 280 S1_GNT[0]# co ntro l e nab le 315 S2_CBE[0] o utp ut 74 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 Table 15-2. JTAG Boundary Register Order Order Pin Names Type Order Pin Names Type 316 S2_CBE[0] inp ut 335 S2_PAR o utp ut 317 S2_AD[8] o utp ut 336 S2_PAR inp ut 318 S2_AD[8] inp ut 337 S2_SERR# inp ut 319 S2_AD[10] o utp ut 338 S2_LOCK# co ntro l e nab le 320 S2_AD[10] inp ut 339 S2_LOCK# o utp ut 321 S2_AD[9] o utp ut 340 S2_LOCK# inp ut 322 S2_AD[9] inp ut 341 S2_TRDY# o utp ut 323 S2_AD[11] o utp ut 342 S2_TRDY# inp ut 324 S2_AD[11] inp ut 343 S2_STOP# co ntro l e nab le 325 S_M66EN inp ut 344 S2_STOP# o utp ut 326 S2_AD[12] o utp ut 345 S2_STOP# inp ut 327 S2_AD[12] inp ut 346 S2_IRDY# co ntro l e nab le 328 S2_AD[14] o utp ut 347 S2_IRDY# o utp ut 329 S2_AD[14] inp ut 348 S2_IRDY# inp ut 330 S2_CBE[1] o utp ut 349 S2_CBE[2] o utp ut 331 S2_CBE[1] inp ut 350 S2_CBE[2] inp ut 332 S2_AD[15] o utp ut 351 S2_AD[13] o utp ut 333 S2_AD[15] inp ut 352 S2_AD[13] inp ut 334 S2_PAR co ntro l e nab le 75 (continued) 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 16. Electrical and Timing Specifications 16.1 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested). Storage Temperature 65°C to +150°C Ambi ent Temperature wi th Power appli ed 0°C to +70°C Supply Voltage to Ground Potenti als (Inputs & AVC C , VD D only) 0.3V to +3.6V D C Input Voltage 0.5V to +3.6V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 16.2 3.3V DC Specifications Sy mbol VDD, AVCC Parameter C ondition Min. Max. 3 3.6 Supply Voltage V ih Input HIGH Voltage 0.5 VDD VDD + 0.5 V il Input LOW Voltage -0.5 0.3 V DD V ih C MOS Input HIGH Voltage 0.7 V DD VDD + 0.5 V il C MOS Input LOW Voltage 0.5 0.3 VDD Vipu Input Pull-up Voltage 0 < Vin < VDD Voh Output HIGH Voltage Iout = 500µA Vol Output LOW Voltage Iout = 1500µA Voh C MOS Output HIGH Voltage Iout = 500µA Vol C MOS Output LOW Voltage Iout = 1500µA C in Input Pi n C apaci tance C clk C LK Pi n C apaci tance C IDSEL Lpin V N otes 3 1 0.7 VDD Input Leakage C urrent Iil U nits ±10 µA 0.9 VDD 0.1 VDD VDD-0.5 3 V 2 0.5 10 5 12 ID SEL Pi n C apaci tance 8 Pi n Inductance 20 pF 3 nH Notes: 1. CMOS Input pins: S_CFN#, TCK, TMS, TDI, TRST#, SCAN_EN, SCAN_TM# 2. CMOS Output pin: TDO 3. PCI pins: P_AD[31:0], P_CBE[3:0], P_PAR, P_FRAME#, P_IRDY#, P_TRDY#, P_DEVSEL#, P_STOP#, P_LOCK#, PIDSEL#, P_PERR#, P_SERR#, P_REQ#, P_GNT#, P_RESET#, S1_AD[31:0], S2_AD[31:0], S1_CBE[3:0], S2_CBE[3:0], S1_PAR, S2_PAR, S1_FRAME#, S2_FRAME#, S1_IRDY#, S2_IRDY#, S1_TRDY#, S2_TRDY#, S1_DEVSEL#, S2_DEVSEL#, S1_STOP#, S2_STOP#, S1_LOCK#, S2_LOCK#, S1_PERR#, S2_PERR#, S1_SERR#, S2_SERR#, S1_REQ[7:0]#, S2_REQ[7:0]#, S1_GNT[7:0]#, S2_GNT[7:0], S1_RESET#, S2_RESET#, S1_EN, S2_EN, P_FLUSH#. 76 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 16.3 3.3V AC Specifications (For P_AD[31:0], P_CBE[3:0], P_PAR, P_FRAME#, P_IRDY#, P_TRDY#, P_DEVSEL#, P_STOP#, P_LOCK#, PIDSEL#, P_PERR#, P_SERR#, P_REQ#, P_GNT#, P_RESET#, S1_AD[31:0], S2_AD[31:0], S1_CBE[3:0], S2_CBE[3:0], S1_PAR, S2_PAR, S1_FRAME#, S2_FRAME#, S1_IRDY#, S2_IRDY#, S1_TRDY#, S2_TRDY#, S1_DEVSEL#, S2_DEVSEL#, S1_STOP#, S2_STOP#, S1_LOCK#, S2_LOCK#, S1_PERR#, S2_PERR#, S1_SERR#, S2_SERR#, S1_REQ[7:0]#, S2_REQ[7:0]#, S1_GNT[7:0]#, S2_GNT[7:0]#, S1_RESET#, S2_RESET#, S1_EN, S2_EN, P_FLUSH#) Sy mbol Ioh(AC ) Parameter C ondition Swi tchi ng 0V < Vout < 0.3 VD D C urrent HIGH 0.3 V D D <Vout < 0.9 VD D Min. Iol(AC ) V out = 0.7 VD D Swi tchi ng VD D > Vout > 0.6 VD D C urrent LOW 0.6 V D D > Vout > 0.1 VD D U nits 3 mA 0.5 VD D mA 0.7 V D D < Vout < VD D (Test Poi nt) Max. -0.5 Eqt'n C 0.7 VD D 32 V D D mA -0.5 mA 0.7 VD D mA 0.18 V D D > Vout >0V N otes Eqt'n D (Test Poi nt) Vout = 0.18 VD D Icl LOW C lamp C urrent 3V < V i n < 1V Ich HIGH C lamp C urrent VDD + 4 > Vin > VDD + 1 Slewr Output Ri se Slew Rate 0.2 VD D to 0.6 VD D load 4 V/ns Slewf Output Fall Slew Rate 0.6 VD D to 0.2VD D load 4 V/ns 0.9 VD D 38 V D D mA mA VD D -0.5 mA Notes: Equation C: Ioh = (98/VDD)*(Vout-VDD)*(Vout+0.4VDD) for VDD>Vout>0.7VDD Equation D: Iol = (256/VDD)*Vout*(VDD-Vout) for 0V<Vout<0.18VDD 16.4 Primary and Secondary Buses at 33 MHz Clock Timing Sy mbol Parameter C ondition Min. Max. 0 1.0 0 10 TSKEW SKEW among S_C LKOUT[15:0] TD ELAY D ELAY between PC LK and S_C LKOUT[15:0] TC YC LE PC LK, S_C LKOUT[15:0] cycle ti me 30 THIGH PC LK, S_C LKOUT[15:0] HIGH ti me 11 TLOW PC LK, S_C LKOUT[15:0] LOW ti me 11 77 20pF load U nits N otes ns 05/08/00 ADVANCE INFORMATION PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 SEATING PLANE 0.15 C 17. 256-Pin PBGA Package 27.00 ± 0.15 A 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 30 ±2 ° PIN #1 CORNER ø1.0 (3X) A B C D E F G H J K L M N P R T U V W Y C 1.27 BSC 24.00 ± 0.1 27.00 ± 0.15 0.60 ± 0.1 4 x 45° CHAMFER (4X) 1.44 8.00 B 0.56 ± 0.05 1.17 ± 0.1 256 x ø0.75 ± 0.15 0.30 S C A S B S 0.10 S C 2.33 Min. / 3.50Max. BOTTOM TOP Figure 17-1. 256-Pin PBGA Package 17.1 Part Number Ordering Information Part Pin - Package Temperature PI7C 7100BNA 256 - PBGA 0°C to +70°C 78 05/08/00 PI7C7100 3-Port PCI Bridge Appendix A Timing Diagrams ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 A-2 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 Figure 1. Configuration Read Transaction 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 17 18 19 20 21 22 Data Byte Enables Addr A Figure 2. Configuration Write Transaction 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL 1 Addr B 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Byte Enables Figure 3. Type 1 to Type 0 Configuration Read Transaction ( P --> S ) 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 1 Addr A 2 3 4 5 6 7 8 9 10 11 12 Byte Enables 13 14 15 16 Addr A Data Byte Enables 13 14 17 18 19 20 21 22 17 18 19 20 21 22 Addr Data A Byte Enables 0 1 2 3 4 5 6 7 8 9 10 A-3 11 12 15 16 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 Figure 4. Type 1 to Type 0 Configuration Write Transaction ( P --> S ) 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 1 2 3 4 5 6 7 8 9 10 11 12 Data Byte Enables Addr B 13 14 15 16 Addr B Data Byte Enables 13 14 17 18 19 20 21 22 17 18 19 20 21 22 21 22 23 Addr Data B Byte Enables 0 1 2 3 4 5 6 7 8 9 10 11 12 15 16 Figure 5. Upstream Type 1 to Special Cycle Transaction ( S --> P ) 0 1 2 3 4 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Data Addr 1 Byte Enables B Data Byte Enables 5 6 Addr 0 1 2 3 4 7 8 Addr Data B Byte Enables 9 10 A-4 11 12 13 14 15 16 17 18 19 20 21 22 23 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 Figure 6. Downstream Type 1 to Special Cycle Transaction ( P --> S ) 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 1 Addr B 2 3 4 5 6 7 8 9 10 11 12 Data Byte Enables 13 14 15 16 Addr B Data Byte Enables 13 14 17 18 19 20 21 22 17 18 19 20 21 22 Addr Data 1 Byte Enables 0 1 2 3 4 5 6 7 8 9 10 11 12 15 16 Figure 7. Downstream Type1 to Type1 Configuration Read Transaction ( P --> S ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 P_CLK P_AD [31:0] Addr P_CBE [3:0] B BytesEnables P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L Addr B Byte Enables Addr B Byte Enables Addr B Byte Enables Addr B Byte Enables Addr B Byte Enables Addr Data B Byte Enables Addr Data B Byte Enables 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 A-5 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 Figure 8. Downstream Type1 to Type1 Configuration Write Transaction ( P --> S ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L Addr Data B Byte Enables Addr Data B Byte Enables Addr Data B Byte Enables Addr Data B Byte Enables Addr Data B Byte Enables Addr Data B Byte Enables Addr Data B Byte Enables Addr Data B Byte Enables 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Figure 9. Upstream Delayed Burst Memory Read Transaction ( S --> P ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L Addr 6 Addr 6 Byte Enables Data Data Data Data Data Data Data Data Byte Enables Addr 6 Byte Enables Addr 6 Byte Enables Addr 6 Data Data Data Data Data Data Data Data Byte Enables 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 A-6 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 Figure 10. Downstream Delayed Burst Memory Read Transaction ( P --> S ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L Addr 6 Byte Enables Addr 6 Byte Enables Addr Addr 6 Byte Enables Addr Data Data Data Data Data Data Data Data Byte Enables 6 Data Data Data Data Data Data Data Data Byte Enables 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Figure 11. Downstream Delayed Memory Read Transaction (P/33MHz-->S/33MHz) 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 1 Addr 6 2 3 4 5 6 7 8 9 10 11 12 Byte Enables 13 14 15 16 Addr 6 Data Byte Enables 13 14 17 18 19 20 21 22 17 18 19 20 21 22 Addr Data 6 Byte Enables 0 1 2 3 4 5 6 7 8 9 10 A-7 11 12 15 16 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 Figure 12. Downstream Delayed Memory Read Transaction (S2/33MHz-->S1/33MHz) 0 1 2 3 4 S_CLKOUT[0] S1_AD [31:0] S1_CBE [3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] S2_CBE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Addr Data 6 Byte Enables Data Addr 6 Byte Enables Addr 0 1 2 3 4 6 Byte Enables 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 22 Figure 13. Downstream Delayed Memory Read Transaction (S1/33MHz-->S2/33MHz) 0 1 2 3 4 S_CLKOUT[0] S2_AD [31:0] S2_CBE [3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] S1_CBE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Addr Data 6 Byte Enables Data Addr 6 Byte Enables Addr 0 1 2 3 4 6 Byte Enables 5 6 7 8 9 10 A-8 11 12 13 14 15 16 17 18 19 20 21 22 23 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 Figure 14. Upstream Delayed Memory Read Transaction (S/33MHz-->P/33MHz) 0 1 2 3 4 5 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Addr Data 6 Byte Enables Addr Data 6 Byte Enables Addr 0 1 2 3 4 6 Byte Enables 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Figure 15. Downstream Posted Memory Write Transaction (P/33MHz-->S/33MHz) 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 12 13 14 15 16 17 18 19 20 21 22 Data Addr 7 Byte Enables Data Addr 7 Byte Enables 0 1 2 3 4 5 6 7 8 9 10 A-9 11 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 Figure 16. Downstream Posted Memory Write Transaction (S2/33MHz-->S1/33MHz) 0 S_CLKOUT[0] S1_AD [31:0] S1_CBE [3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] S2_CBE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 16 17 18 19 20 21 22 Addr Data 7 Byte Enables Addr Data 7 Byte Enables 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 17. Downstream Posted Memory Write Transaction (S1/33MHz-->S2/33MHz) 0 S_CLKOUT[0] S2_AD [31:0] S2_CBE [3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] S1_CBE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 16 17 18 19 20 21 22 Addr Data 7 Byte Enables Addr Data 7 Byte Enables 0 1 2 3 4 5 6 7 8 9 10 A-10 11 12 13 14 15 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 Figure 18. Upstream Posted Memory Write Transaction (S/33MHz-->P/33MHz) 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 18 19 20 21 22 Addr Data 7 Byte Enables Addr Data 7 Byte Enables 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 19. Downstream Flow-Through Posted Memory Write Transaction (P/33MHz-->S/33MHz) 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 1 2 3 4 6 7 8 9 1 2 3 11 12 13 14 15 16 17 18 19 20 21 22 4 5 6 7 8 21 22 Data Data Data Data Data Data Data Data Data Byte Enables Data Addr 7 0 10 Data Data Data Data Data Data Data Data Data Byte Enables Data Addr 7 5 9 10 A-11 11 12 13 14 15 16 17 18 19 20 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 Figure 20. Downstream Flow-Through Posted Memory Write Transaction (S2/33MHz-->S1/33MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 S_CLKOUT[0] S1_AD [31:0] Addr S1_CBE [3:0] 7 Data Data Data Data Data Data Data Data Data Data Byte Enables S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] Addr S2_CBE[3:0] 7 Data Data Data Data Data Data Data Data Data Data Byte Enables S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Figure 21. Downstream Flow-Through Posted Memory Write Transaction (S1/33MHz-->S2/33MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 S_CLKOUT[0] S2_AD [31:0] Addr S2_CBE [3:0] 7 Data Data Data Data Data Data Data Data Data Data Byte Enables S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] Addr S1_CBE[3:0] 7 Data Data Data Data Data Data Data Data Data Data Byte Enables S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L 0 1 2 3 4 5 6 7 8 9 10 11 A-12 12 13 14 15 16 17 18 19 20 21 22 23 24 25 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 Figure 22. Upstream Flow-Through Posted Memory Write Transaction (S/33MHz-->P/33MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 27 28 P_CLK P_AD [31:0] Addr P_CBE [3:0] 7 Data Data Data Data Data Data Data Data Data Data Byte Enables P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] Addr S_CBE[3:0] 7 Data Data Data Data Data Data Data Data Data Data Byte Enables S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 22 24 25 26 Figure 23. Downstream Delayed I/O Read Transaction ( P --> S ) 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 1 Addr 2 2 3 4 5 6 7 8 9 10 11 12 Byte Enables 13 14 15 16 Addr 2 Data Byte Enables 13 14 17 18 19 20 21 22 23 24 25 26 17 18 19 20 21 22 23 24 25 26 Addr Data 2 Byte Enables 0 1 2 3 4 5 6 7 8 9 10 11 12 A-13 15 16 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 Figure 24. Downstream Delayed I/O Read Transaction (S2/33MHz-->S1/33MHz) 0 1 2 3 4 S_CLKOUT[0] S1_AD [31:0] S1_CBE [3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] S2_CBE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Addr Data 2 Byte Enables Data Addr 2 Byte Enables Addr 0 1 2 3 4 2 Byte Enables 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 22 23 Figure 25. Downstream Delayed I/O Read Transaction (S1/33MHz-->S2/33MHz) 0 1 2 3 4 S_CLKOUT[0] S2_AD [31:0] S2_CBE [3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] S1_CBE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Addr Data 2 Byte Enables Data Addr 2 Byte Enables Addr 0 1 2 3 4 2 Byte Enables 5 6 7 8 9 10 A-14 11 12 13 14 15 16 17 18 19 20 21 22 23 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 Figure 26. Upstream Delayed I/O Read Transaction (S/33MHz-->P/33MHz) 0 1 2 3 4 5 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Addr Data 2 Byte Enables Addr Data 2 Byte Enables Addr 0 1 2 3 4 2 Byte Enables 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Figure 27. Downstream Delayed I/O Write Transaction ( P --> S ) 0 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 1 Addr 3 2 3 4 5 6 7 8 9 10 11 12 Data Byte Enables 13 14 15 16 Addr 3 Data Byte Enables 13 14 17 18 19 20 21 22 17 18 19 20 21 22 Addr Data 3 Byte Enables 0 1 2 3 4 5 6 7 8 9 10 A-15 11 12 15 16 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 Figure 28. Downstream Delayed I/O Write Transaction (S2/33MHz-->S1/33MHz) 0 1 2 3 4 S_CLKOUT[0] S1_AD [31:0] S1_CBE [3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] S2_CBE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Data Addr 3 Byte Enables 3 Data Byte Enables 5 6 Addr 0 1 2 3 4 7 8 Addr Data 3 Byte Enables 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 22 23 Figure 29. Downstream Delayed I/O Write Transaction (S1/33MHz-->S2/33MHz) 0 1 2 3 4 S_CLKOUT[0] S2_AD [31:0] S2_CBE [3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] S1_CBE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Data Addr 3 Byte Enables 3 Data Byte Enables 5 6 Addr 0 1 2 3 4 7 8 Addr Data Byte Enables 3 9 10 A-16 11 12 13 14 15 16 17 18 19 20 21 22 23 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123 Figure 30. Upstream Delayed I/O Write Transaction ( S --> P ) 0 1 2 3 4 P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Data Addr 3 Byte Enables 3 Data Byte Enables 5 6 Addr 0 1 2 3 4 7 8 Addr Data 3 Byte Enables 9 10 A-17 11 12 13 14 15 16 17 18 19 20 21 22 23 04/18/00 ADVANCE INFORMATION Appendix A PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 A-18 04/18/00 PI7C7100 3-Port PCI Bridge Appendix B Evaluation Board Users Manual ADVANCE INFORMATION Appendix B PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 B-2 04/18/00 ADVANCE INFORMATION Appendix B PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 PI7C7100 Evaluation Board Users Manual General Information 1. Please make sure you have included with your PI7C7100 evaluation board, the five-page schematic and the preliminary specification for the PI7C7100. 2. Check all jumpers for proper settings: Pin N ame Jumper Function Position S_C FN# JP 4 Internal arbi ter enable 1-2 ( 0 ) S 1_E N JP 5 S1 bus enable 2-3 ( 1 ) S 2_E N JP 6 S2 bus enable 2-3 ( 1 ) SC AN_EN JP 7 SC AN control 1-2 ( 0 ) SC AN_EN JP 7 SC LK_IN as clock i nput 2-3 ( 1 ) PLL_TM JP 8 PLL test mode di sable 1-2 ( 0 ) BYPASS JP 9 PLL enable 1-2 ( 0 ) P_FLUSH# JP 1 0 Pri mary FIFO flush di sable 2-3 ( 1 ) 3. Check and make sure there are no shorts between power (3.3V, 5V, 12V, and 12V) and ground. 4. Plug evaluation board in any PCI slot on your system. Make sure your system is powered off before doing so. 5. Connect any PCI devices on the secondary slots of the evaluation board. Be careful that the orientation of the card is correct (see Diagram A). PCI Add-In Card Pericom Semiconductor Three-Port PCI Bridge Board Diagram A B-3 04/18/00 ADVANCE INFORMATION Appendix B PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 General Information (continued) 6. Turn on the power for the system. Your OS should already have drivers for the PI7C7100 evaluation board. In Win9X, Plug and Play should detect the device as a PCI-to-PCI bridge. The system may prompt you for the Win9X CD for the drivers. The OS will detect two PCI-to-PCI bridges as the PI7C7100 has two secondary PCI buses. In Win NT, you should not have to install drivers. 7. Install drivers for any PCI devices you have attached to the evaluation board. 8. If any of the steps are unclear or were unsuccessful, please contact your Pericom support person at 408-435-0800. 9. Thank you for evaluating Pericom Semiconductor Corporations products. B-4 04/18/00 ADVANCE INFORMATION Appendix B PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 Frequently Asked Questions 1. What is the function of SCAN_EN? SCAN_EN is for a full scan test or S_CLKIN select. During SCAN mode, SCAN_EN will be driven to logic 0 or logic 1 depending on functionality. During normal mode, if SCAN_EN is connected to logic 0 (JP7 in the 1-2 position), S_CLKIN will be used for PLL test only when PL_TM is active. If SCAN_EN is connected to logic 1 (JP7 in the 2-3 position), S_CLKIN will be the clock input for the secondary buses. All secondary clock outputs, S_CLKOUT [15:0], are still derived from P_CLK with 0-10ns delay. The S_CLKOUT [15:0] should be disabled by programming the bits [15:0] in both configuration registers 1 and 2 at offset 68h. 2. What is the function of SCAN_TM#? SCAN_TM# is for full scan test and power on reset for the PLL. SCAN_TM# should be connected to logic 1 or to an RC path (R1 and C13) during normal operation. 3. How do you use the external arbiter? a) Disable the on chip arbiter by connecting S_CFN to logic 1 (JP4 in the 2-3 position). b) Use S1_REQ0# as GRANT and S1_GNT0# as REQUEST on the S1 bus. c) Use S2_REQ0# as GRANT and S2_GNT0# as REQUEST on the S2 bus. 4. What is the purpose of having JP1, JP2, and JP3? JP1, JP2, and JP3 are designed for easy access to the primary bus signals. You may connect any of these pins to an oscilloscope or a logic analyzer for observation. No connection is required for normal operation. The following table indicates which bus signals correspond to which pins. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 JP 2 REQ A D 29 A D 26 C BE3 A D 21 A D 18 C BE2 IRD Y LOC K PAR A D 14 AD 11 C BE0 AD6 AD 5 AD 0 JP 3 A D 31 A D 28 A D 25 A D 23 A D 20 A D 17 FRAME D VSEL PERR C BE1 A D 13 A D 10 AD 8 AD 4 AD 2 GND JP 1 GNT A D 30 A D 27 A D 24 A D 22 A D 19 A D 16 IRD Y STOP SERR A D 15 A D 12 AD 9 AD 7 AD 3 AD 1 5. What is the purpose for having U17, U19, and U20? U17, U19, and U20 are designed for easy access to the digital ground planes for observation. 6. How is the evaluation board constructed? The evaluation board is a six-layer PCB. The top and bottom layers (1 and 6) are for signals, power, and ground routing. Layer 2 and layer 5 are ground planes. Layer 3 is a digital 3.3V power plane. Layer 4 is a digital 5V power plane with an island of analog 3.3V power. 7. What is the function of S_CLKIN? The S_CLKIN pin is a test pin for the on chip PLL when PLL_TM is set to logic 1. During normal operation, if PLL_TM is set to logic 0, SCAN_TM# is set to logic 1, and SCAN_EN is set to logic 1, then S_CLKIN will be the clock input for both the secondary buses. However, the S_CLKOUT [15:0] are still derived by programming bits [15:0] in both configuration registers 1 and 2 at offset 68h. 8. What clock frequency combinations does the PI7C7100 support? Primary Bus Secondary (1 and 2) Buses 33MHz 33MHz 9. How are the JTAG signals being connected? The JTAG signals consist of TRST#, TCK, TMS, TDI, and TDO. All the mentioned signals have weak internal pull-up connections. Therefore, no connection is needed if you want the JTAG circuit to be disabled. If you want to activate the JTAG circuit, you need to connect all five signals according to the JTAG specification (IEEE 1149). B-5 04/18/00 ADVANCE INFORMATION Appendix B PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 B-6 04/18/00 PI7C7100 3-Port PCI Bridge Appendix C Schematics ADVANCE INFORMATION Appendix C PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 C-2 04/18/00 C-3 1 2 3 4 3 2 1 C16 0.1uF C43 0.001uF C24 0.01uF + +5V C7 10uF C44 0.01uF R16 5.1k R15 5.1K F3A A C26 0.01uF 150 R18 226 R25 C45 0.1uF C25 0.01uF +3.3V +3.3V 0 R17 2 JP10 Table1 JP9 ByPass_L P_Flush_L 1 JP7 SCAN_EN HEADER 3 JP10 JP6 S2_EN JP8 JP5 S1_EN PLL_TM JP4 1 3 C27 0.01uF JP Select S_CFNn Name t1 A 3 2 1 VO C28 0.01uF 121 R5 LT1117 GNDTAB VI U0 C46 0.01uF AVCC C55 0.001uF HEADER 3 JP9 4 2 C20 0.001uF C354 100uF C48 0.001uF C57 0.1uF 3 2 1 C21 0.001uF C360 0.01uF C17 0.1uF C9 10uF C361 0.001uF + C50 0.01uF C22 0.01uF +3.3V C38 0.001uF +3.3V C49 0.001uF C19 0.001uF HEADER 3 JP8 AVCC 2-3 1-2 1-2 1-2 2-3 2-3 1-2 Position +3.3V R14 5.1K R13 5.1k +3.3V C29 0.01uF C47 0.1uF C56 0.01uF +3.3V S2_Enable SCAN Disable PLL_TM Disable PLL Enable P_Flush Disable S1_Enable Function Internal Arbiter 1 C362 0.1uF C10 10uF + F3A B C8 10uF 2 C40 0.01uF AVCC +3.3V C11 0.01uF C32 0.1uF C364 0.001uF C33 0.1uF C365 0.1uF C12 0.1uF C41 0.1uF +3.3V C13 0.1uF R1 3.3k HEADER 3 3 2 1 +3.3V JP7 AVCC C31 0.001uF C363 0.01uF C30 0.001uF C51 0.1uF C23 0.1uF C39 0.001uF + +3.3V R12 5.1K R10 5.1k B 3 2 1 C34 0.1uF C366 0.01uF C35 0.1uF C59 0.1uF +3.3V 3 2 1 R7 5.1k +3.3V C C372 0.001uF C60 0.001uF P_AD[31:0] C373 0.01uF P_RESETN P_GNTN P_IDSEL P_REQN P_FRAMEN P_IRDYN P_TRDYN P_DEVSELN P_STOPN P_LOCKN P_PERRN P_SERRN P_PAR P_M66EN PLL_SCLK S_M66EN PLL_CAP1 PLL_CAP2 ByPass TRST_L TCK TMS TDO TDI P_CBE[3:0] R8 5.1K R4 5.1k PLL_PCLK HEADER 3 JP4 R3 5.1K C37 0.1uF C368 0.1uF C371 0.1uF C36 0.1uF C367 0.001uF C370 0.01uF 3 2 1 HEADER 3 JP5 C58 0.01uF R6 5.1k R2 5.1K +3.3V C42 0.001uF C353 0.001uF R11 5.1K R9 5.1k HEADER 3 JP6 +3.3V C + AVCC C374 10uF +3.3V P_AD[31:0] P_LOCKN P_PERRN P_SERRN S_M66EN P_M66EN P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 P_CBE0 P_CBE1 P_CBE2 P_CBE3 Y6 U9 W11 Y13 U14 V17 U17 T18 P18 M18 K19 H17 G17 D18 A20 A17 A15 D12 A10 A8 A5 A3 C2 E3 G2 J2 K4 N1 R2 U2 Y1 U4 E2 J3 N2 V1 V7 U10 V15 W20 P19 L17 F18 D15 C14 D11 B8 D5 W5 Y5 U7 Y10 W6 W13 V13 U13 Y14 W14 V14 Y15 W15 U15 V4 U5 Y3 U6 R4 Y4 V18 V5 D7 V6 W3 W4 U3 V2 W1 V3 W2 Y2 R17 T17 Y20 V20 U20 Y19 W19 U19 Y18 W18 U18 Y17 W17 Y16 W16 V16 V12 W12 Y12 U11 V11 Y11 V10 W10 W9 Y9 U8 V8 W8 Y8 W7 Y7 V19 U16 U12 V9 PI7C7100 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND AVCC AGND +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V P_FLUSH_L P_RESET_L P_GNT P_IDSEL P_REQ P_FRAME_L P_IRDY_L P_TRDY_L P_DEVSEL_L P_STOP_ L P_LOCK_L P_PERR_L P_SERR_L P_PAR SCAN_TM_L SCAN_EN_H PLL_TM_H CMPO1 RESERVED ByPass P_M66EN PLL_SCLK S_M66EN PLL_PCLK S1_EN S2_EN TRST_L JTAG_TCK JTAG_TMS JTAG_TD0 JTAG_TDI S_CFN_L P_AD[0] P_AD[1] P_AD[2] P_AD[3] P_AD[4] P_AD[5] P_AD[6] P_AD[7] P_AD[8] P_AD[9] P_AD[10] P_AD[11] P_AD[12] P_AD[13] P_AD[14] P_AD[15] P_AD[16] P_AD[17] P_AD[18] P_AD[19] P_AD[20] P_AD[21] P_AD[22] P_AD[23] P_AD[24] P_AD[25] P_AD[26] P_AD[27] P_AD[28] P_AD[29] P_AD[30] P_AD[31] P_CBE[0] P_CBE[1] P_CBE[2] P_CBE[3] U1 S1_AD[0] S1_AD[1] S1_AD[2] S1_AD[3] S1_AD[4] S1_AD[5] S1_AD[6] S1_AD[7] S1_AD[8] S1_AD[9] S1_AD[10] S1_AD[11] S1_AD[12] S1_AD[13] S1_AD[14] S1_AD[15] S1_AD[16] S1_AD[17] S1_AD[18] S1_AD[19] S1_AD[20] S1_AD[21] S1_AD[22] S1_AD[23] S1_AD[24] S1_AD[25] S1_AD[26] S1_AD[27] S1_AD[28] S1_AD[29] S1_AD[30] S1_AD[31] S1_CBE[0] S1_CBE[1] S1_CBE[2] S1_CBE[3] D SCLKOUT[15] SCLKOUT[14] SCLKOUT[13] SCLKOUT[12] SCLKOUT[11] SCLKOUT[10] SCLKOUT[9] SCLKOUT[8] SCLKOUT[7] SCLKOUT[6] SCLKOUT[5] SCLKOUT[4] SCLKOUT[3] SCLKOUT[2] SCLKOUT[1] SCLKOUT[0] S2_DEVSEL_L S2_FRAME_L S2_GNTN[0] S2_GNTN[1] S2_GNTN[2] S2_GNTN[3] S2_GNTN[4] S2_GNTN[5] S2_GNTN[6] S2_GNTN[7] S2_IRDY_L S2_LOCK_L S2_PAR_L S2_PERR_L S2_REQ[0] S2_REQ[1] S2_REQ[2] S2_REQ[3] S2_REQ[4] S2_REQ[5] S2_REQ[6] S2_REQ[7] S2_RESET_L S2_SERR_L S2_STOP_L S2_TRDY_L S1_DEVSEL_L S1_FRAME_L S1_GNTN[0] S1_GNTN[1] S1_GNTN[2] S1_GNTN[3] S1_GNTN[4] S1_GNTN[5] S1_GNTN[6] S1_GNTN[7] S1_IRDY_L S1_LOCK_L S1_PAR_L S1_PERR_L S1_REQ[0] S1_REQ[1] S1_REQ[2] S1_REQ[3] S1_REQ[4] S1_REQ[5] S1_REQ[6] S1_REQ[7] S1_RESET_L S1_SERR_L S1_STOP_L S1_TRDY_L S2_AD[0] S2_AD[1] S2_AD[2] S2_AD[3] S2_AD[4] S2_AD[5] S2_AD[6] S2_AD[7] S2_AD[8] S2_AD[9] S2_AD[10] S2_AD[11] S2_AD[12] S2_AD[13] S2_AD[14] S2_AD[15] S2_AD[16] S2_AD[17] S2_AD[18] S2_AD[19] S2_AD[20] S2_AD[21] S2_AD[22] S2_AD[23] S2_AD[24] S2_AD[25] S2_AD[26] S2_AD[27] S2_AD[28] S2_AD[29] S2_AD[30] S2_AD[31] S2_CBE[0] S2_CBE[1] S2_CBE[2] S2_CBE[3] D T3 T1 P3 N3 M4 L3 L2 J1 A11 C12 A13 B14 B15 C16 A18 A19 D3 D2 K2 L1 L4 M3 N4 R1 P4 U1 B2 B3 B4 D4 K3 K1 M1 M2 P1 P2 R3 T2 T4 C4 C3 A2 J20 H20 B18 D16 B16 D14 A14 B13 B12 C11 H19 J18 K18 J17 B17 C17 A16 C15 C13 D13 A12 B11 B10 K20 J19 H18 C10 D10 A9 B9 C9 D9 C8 D8 B7 C7 A6 B6 C6 D6 B5 C5 B1 C1 D1 E4 E1 F4 F3 F2 G4 G3 G1 H4 H3 H2 H1 J4 A7 A4 A1 F1 T19 T20 R18 R19 R20 P17 N17 N18 N19 N20 M17 M19 M20 L18 L19 L20 G19 G20 F17 F19 F20 E17 E18 E19 D17 D19 D20 C18 C19 C20 B19 B20 P20 K17 G18 E20 SCLKOUT15 SCLKOUT14 SCLKOUT13 SCLKOUT12 SCLKOUT11 SCLKOUT10 SCLKOUT9 SCLKOUT8 SCLKOUT7 SCLKOUT6 SCLKOUT5 SCLKOUT4 SCLKOUT3 SCLKOUT2 SCLKOUT1 SCLKOUT0 S2_REQN0 S2_REQN1 S2_REQN2 S2_REQN3 S2_REQN4 S2_REQN5 S2_REQN6 S2_REQN7 S2_GNTN0 S2_GNTN1 S2_GNTN2 S2_GNTN3 S2_GNTN4 S2_GNTN5 S2_GNTN6 S2_GNTN7 S2_AD0 S2_AD1 S2_AD2 S2_AD3 S2_AD4 S2_AD5 S2_AD6 S2_AD7 S2_AD8 S2_AD9 S2_AD10 S2_AD11 S2_AD12 S2_AD13 S2_AD14 S2_AD15 S2_AD16 S2_AD17 S2_AD18 S2_AD19 S2_AD20 S2_AD21 S2_AD22 S2_AD23 S2_AD24 S2_AD25 S2_AD26 S2_AD27 S2_AD28 S2_AD29 S2_AD30 S2_AD31 S2_CBE0 S2_CBE1 S2_CBE2 S2_CBE3 S1_REQN0 S1_REQN1 S1_REQN2 S1_REQN3 S1_REQN4 S1_REQN5 S1_REQN6 S1_REQN7 S1_DEVSELN S1_FRAMEN S1_GNTN0 S1_GNTN1 S1_GNTN2 S1_GNTN3 S1_GNTN4 S1_GNTN5 S1_GNTN6 S1_GNTN7 S1_IRDYN S1_LOCKN S1_PAR S1_AD0 S1_AD1 S1_AD2 S1_AD3 S1_AD4 S1_AD5 S1_AD6 S1_AD7 S1_AD8 S1_AD9 S1_AD10 S1_AD11 S1_AD12 S1_AD13 S1_AD14 S1_AD15 S1_AD16 S1_AD17 S1_AD18 S1_AD19 S1_AD20 S1_AD21 S1_AD22 S1_AD23 S1_AD24 S1_AD25 S1_AD26 S1_AD27 S1_AD28 S1_AD29 S1_AD30 S1_AD31 S1_CBE0 S1_CBE1 S1_CBE2 S1_CBE3 S2_RESETN S2_SERRN S2_STOPN S2_TRDYN S2_IRDYN S2_LOCKN S2_PAR S2_PERRN S2_DEVSELN S2_FRAMEN S1_RESETN S1_SERRN S1_STOPN S1_TRDYN S1_IRDYN S1_LOCKN S1_PAR S1_PERRN S1_DEVSELN S1_FRAMEN S1_AD[31:0] Date: Size C Title S2_AD[31:0] E Friday, March 17, 2000 PCI Chip Document Number PI7C7100 E Sheet 1 of 5 Rev 1.3 2380 Bering Dr., San Jose, CA Three Port PCI Bridge Evaluation Board SCLKOUT[15:0] S2_REQN[7:0] S2_GNTN[7:0] S2_CBE[3:0] S2_AD[31:0] S1_REQN[7:0] S1_GNTN[7:0] S1_CBE[3:0] S1_AD[31:0] 1 2 3 4 ADVANCE INFORMATION Appendix C PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 04/18/00 C-4 1 2 3 A 1header U38 1 T C121 0.001uF TDO C2 0.01uF R29 0 C106 0.1uF TCK 1header U43 + +3.3V C97 10uF B C119 0.001uF + C108 0.01uF C101 10uF + +5V C5 0.1uF C102 10uF +12V -12V C103 0.01uF PCIEDGE -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# NC NC NC GND CLK GND REQ# +5VIO1 AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5VIO2 ACK64# +5V +5V U5 C104 0.01uF TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5VIO1 NC NC NC NC RST# +5VIO1 GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5VIO2 REQ64# +5V +5V 1header U44 T C C105 0.01uF C3 0.1uF + C C113 0.1uF +5V C120 0.001uF +3.3V C114 0.1uF C109 10uF R26 0 A1 A2 A3 A4 A5 A6 INTA INTA_L A7 INTC INTC_L A8 A9 A10 A11 A12 A13 A14 A15 P_RESET_L A16 A17 P_GNT_L GNT_L A18 A19 A20 AD30 A21 AD28 A22 A23 AD26 A24 A25 AD24 A26 P_IDSEL_L IDSEL_L A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 P_FRAME_L FRAME_L A35 A36 P_TRDY_L TRDY_L A37 A38 P_STOP_ L STOP_ L A39 A40 A41 A42 A43 P_PAR PAR A44 AD15 A45 AD13 A46 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 A61 A62 1 B C115 0.01uF C107 0.01uF C1 0.1uF R32 5.1k R31 5.1k TRST_L 1header U42 T 1header U40 1 T 1 B1 R27 0 B2 B3 B4 B5 B6 B7 INTB INTB_L B8 INTD INTD_L U41 B9 B10 1header B11 B12 B13 B14 B15 B16 P_CLK CLK B17 B18 P_REQ_L REQ_L B19 AD31 B20 AD29 B21 B22 AD27 B23 B24 AD25 B25 C/BE3 B26 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 P_IRDY_L IRDY_L B36 B37 P_DVSEL_L DVSEL_L B38 B39 P_LOCK_L LOCK_L P_PERR_L B40 PERR_L B41 B42 P_SERR_L SERR_L B43 B44 C/BE1 AD14 B45 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 B61 B62 1 T 1 T 1 RESET_L R28 0 R30 0 TMS TDI D 1 1header U48 T 1header U47 T 1header U46 T 1header U45 T T2 P_GNT_L AD30 AD27 AD24 AD22 AD19 AD16 P_IRDY_L P_STOP_ L P_SERR_L AD15 AD12 AD9 AD7 AD3 AD1 INTD 1 1 INTB INTC 1 INTA HEADER 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 JP1 P_REQ_L AD29 AD26 C/BE3 AD21 AD18 C/BE2 P_TRDY_L P_LOCK_L P_PAR AD14 AD11 C/BE0 AD6 AD5 AD0 HEADER 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 JP2 C/BE[3:0] AD[31:0] E C116 0.01uF C4 0.1uF C110 0.01uF +5VIO2 C6 0.001uF C118 0.001uF C111 0.1uF +5VIO1 C14 0.001uF C112 0.01uF C15 0.001uF C18 0.001uF D C117 0.01uF Table2 M66EN Date: Size C Title 15 AD3 AD5 AD2 PCI Edge Connector Friday, March 17, 2000 E Sheet Three Port PCI Bridge Evaluation Board Document Number PI7C7100 16 AD1 AD0 GND HEADER 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 JP3 2 of 5 Rev 1.3 2380 Bering Dr., San Jose, CA 14 AD7 AD6 AD4 AD31 AD28 AD25 AD23 AD20 AD17 P_FRAME_L P_DVSEL_L P_PERR_L C/BE1 AD13 AD10 AD8 AD4 AD2 C/BE[3:0] AD[31:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 JP1 GNT AD30 AD27 AD24 AD22 AD19 AD16 IRDY STOP SERR AD15 AD12 AD9 JP2 REQ AD29 AD26 CBE3 AD21 AD18 CBE2 TRDY LOCK PAR AD14 AD11 CBE0 JP3 AD31 AD28 AD25 AD23 AD20 AD17 Frame DVSEL PERR CBE1 AD13 AD10 AD8 +3.3V 1header U39 T 4 A 1 2 3 4 ADVANCE INFORMATION Appendix C PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 04/18/00 C-5 1 2 3 4 IRDY_L REQ0_L CLK0 INTB_L INTD_L 5.1K R37 + +3.3V C204 10uF 2 M66EN C153 0.01uF SERR_L LOCK_L PERR_L DEVSEL_L 1 +12V C130 0.01uF A M66EN TCK0 A B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C147 B11 0.01uF B12 C150 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#0 B61 B62 C129 0.01uF -12V + +5V + +3.3V C206 10uF C156 10uF PCISLOT -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V U9 +12V +12V + C209 0.01uF C210 0.01uF C185 0.01uF C186 0.1uF C211 0.01uF C212 0.01uF +3.3V C187 0.1uF +3.3V REQ64#3 5.1K C213 0.01uF C188 0.1uF +12V 1 R70 2 R69 5.1K 5.1K 5.1K 1 R64 REQ64#2 5.1K 2 R63 -12V C184 0.01uF R51 5.1K 1 1 R58 REQ64#1 REQ64#0 AD[31:0] C154 0.01uF SERR_L LOCK_L PERR_L -12V 2 2 2 2 2 C214 0.01uF C189 0.1uF C161 0.01uF DEVSEL_L IRDY_L REQ1_L CLK1 INTC_L INTA_L 5.1K R38 R57 2 +3.3V PAR STOP_ L TRDY_L FRAME_L IDSEL0_L GNT0_L RESET_L 1 5.1K 2 +3.3V INTA_L INTC_L 2 2 2 5.1K R50 AD[31:0] R34 A1 1 TRST0_L 5.1K A2 R40 A3 TMS0 1 R43 1 5.1K A4 TDI0 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE0 A41 SBO0_ L A42 A43 A44 AD15 A45 A46 AD13 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#0 A61 A62 -12V 1 ACK64#3 C158 10uF 1 ACK64#2 +5V 1 1 ACK64#1 ACK64#0 TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V TCK1 B C215 0.01uF C190 0.1uF C162 0.01uF +3.3V C226 0.01uF +5V C194 0.1uF C163 0.01uF SDONE3 SDONE2 SDONE1 C217 0.01uF C195 0.1uF C218 0.01uF C134 0.1uF C219 0.01uF C191 0.1uF +5V C220 0.01uF C192 0.1uF C167 0.01uF SBO3_ L SBO2_ L SBO1_ L SBO0_ L C/BE[3:0] 1 1 1 1 2 2 2 5.1K R72 5.1K R66 5.1K R60 5.1K R53 C135 0.1uF R35 A1 1 TRST1_L 5.1K A2 R41 A3 TMS1 1 R44 1 5.1K A4 TDI1 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE1 A41 SBO1_ L A42 A43 A44 AD15 A45 AD13 A46 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#1 A61 A62 C166 0.01uF +3.3V C74 0.1uF C165 0.01uF 2 2 2 2 C133 0.1uF TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V +3.3V C132 0.1uF +3.3V 5.1K R71 5.1K R65 5.1K R59 5.1K R52 C164 0.01uF 1 1 1 1 PCISLOT -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V U10 C131 0.1uF SDONE0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C148 B11 0.01uF B12 C151 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 AD3 B56 B57 AD1 B58 B59 B60 ACK64#1 B61 B62 B 2 2 2 2 PAR STOP_ L TRDY_L REQ2_L CLK2 INTD_L INTB_L 5.1K R39 C155 0.01uF SERR_L LOCK_L PERR_L DEVSEL_L IRDY_L 1 +3.3V C C/BE[3:0] FRAME_L IDSEL1_L GNT1_L RESET_L INTB_L INTD_L +3.3V C 2 C138 0.1uF C140 0.1uF STOP_ L SERR_L PERR_L LOCK_L 5.1K R73 5.1K R67 5.1K R61 5.1K R54 C170 0.01uF 1 1 1 1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C149 B11 0.01uF B12 C152 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#2 B61 B62 TCK2 C139 0.1uF +5V A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 C72 0.01uF TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V C70 0.1uF C172 0.01uF +3.3V +5V C171 0.01uF 2 2 2 2 PCISLOT -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V U11 C69 0.1uF R36 1 1 C73 0.01uF DEVSEL_L 1 IRDY_L TRDY_L FRAME_L 1 REQ64#2 AD2 AD0 AD6 AD4 C/BE0 AD9 AD13 AD11 AD15 SDONE2 SBO2_ L AD18 AD16 AD22 AD20 AD24 AD28 AD26 AD30 5.1K R74 5.1K R68 5.1K R62 5.1K R55 5.1K R42 TMS2 1 R45 TDI2 1 5.1K 5.1K 1 TRST2_L D D +3.3V 2 2 2 2 PAR +3.3V STOP_L TRDY_L FRAME_L IDSEL2_L GNT2_L RESET_L INTC_L INTA_L 2 2 2 C216 0.01uF SERR_L LOCK_L PERR_L DEVSEL_L IRDY_L REQ3_L CLK3 INTA_L INTC_L 1 R33 5.1K 2 Date: Size C Title B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C339 B11 0.01uF B12 C340 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#3 B61 B62 TCK3 TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V Friday, March 17, 2000 E Secondary 1 PCI Bus Document Number PI7C7100 2 2 2 PAR STOP_ L TRDY_L FRAME_L IDSEL3_L GNT3_L RESET_L INTD_L INTB_L +3.3V Sheet 3 of 5 Rev 1.3 2380 Bering Dr., San Jose, CA R46 A1 TRST3_L 1 5.1K A2 R47 A3 TMS3 1 R48 A4 TDI3 1 5.1K 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE3 A41 SBO3_ L A42 A43 A44 AD15 A45 A46 AD13 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#3 A61 A62 Three Port PCI Bridge Evaluation Board PCISLOT -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V U8 E 1 2 3 4 ADVANCE INFORMATION Appendix C PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 04/18/00 C-6 1 2 3 4 IRDY_L REQ0_L CLK0 INTB_L INTD_L 5.1K R79 2 M66EN C258 0.01uF SERR_L LOCK_L PERR_L DEVSEL_L 1 + +3.3V M66EN TCK0 A + +5V + +5V + +3.3V C311 10uF C287 10uF C229 10uF PCISLOT -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V U13 C284 10uF B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C252 B11 0.01uF B12 C255 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#0 B61 B62 A +12V +12V + C314 0.01uF C315 0.01uF C290 0.01uF C291 0.1uF C316 0.01uF C317 0.01uF +3.3V C292 0.1uF +3.3V REQ64#3 5.1K C318 0.01uF C293 0.1uF +12V 1 -12V 2 2 2 2 2 +12V C319 0.01uF C294 0.1uF C266 0.01uF R112 2 R111 5.1K 5.1K 5.1K 1 R106 REQ64#2 5.1K 2 R105 -12V C289 0.01uF R93 5.1K 1 1 R100 REQ64#1 REQ64#0 AD[31:0] C259 0.01uF SERR_L LOCK_L PERR_L DEVSEL_L IRDY_L REQ1_L CLK1 INTC_L INTA_L 5.1K R80 R99 2 +3.3V PAR STOP_ L TRDY_L FRAME_L IDSEL0_L GNT0_L RESET_L 1 5.1K 2 +3.3V INTA_L INTC_L 2 2 2 C232 10uF 5.1K R92 AD[31:0] R76 A1 1 TRST0_L 5.1K A2 R82 A3 TMS0 1 R85 1 5.1K A4 TDI0 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE0 A41 SBO0_ L A42 A43 A44 AD15 A45 A46 AD13 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#0 A61 A62 -12V 1 ACK64#3 C263 10uF 1 ACK64#2 +5V 1 1 ACK64#1 ACK64#0 TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V + +5V -12V C235 0.01uF B C320 0.01uF C295 0.1uF C267 0.01uF +3.3V C268 0.01uF SDONE3 SDONE2 SDONE1 +3.3V 5.1K R113 5.1K R107 5.1K C323 0.01uF C239 0.1uF C324 0.01uF +5V C299 0.1uF +5V C325 0.01uF C300 0.1uF C272 0.01uF SBO3_ L SBO2_ L SBO1_ L SBO0_ L C/BE[3:0] 1 1 1 1 2 2 2 +3.3V 2 2 2 2 PAR REQ2_L CLK2 INTD_L INTB_L 5.1K R81 C260 0.01uF SERR_L LOCK_L PERR_L DEVSEL_L IRDY_L 1 C +3.3V C85 0.01uF C C275 0.01uF C/BE[3:0] C83 0.1uF STOP_ L TRDY_L FRAME_L IDSEL1_L GNT1_L RESET_L INTB_L INTD_L C84 0.01uF C82 0.1uF 5.1K R114 5.1K R108 5.1K R102 5.1K R95 C240 0.1uF R77 A1 1 TRST1_L 5.1K A2 R83 A3 TMS1 1 R86 1 5.1K A4 TDI1 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE1 A41 SBO1_ L A42 A43 A44 AD15 A45 AD13 A46 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#1 A61 A62 C271 0.01uF +3.3V C298 0.1uF C270 0.01uF 2 2 2 2 C238 0.1uF TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V +3.3V C237 0.1uF R101 5.1K R94 C269 0.01uF 1 1 1 1 PCISLOT -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V U14 C236 0.1uF SDONE0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C253 B11 0.01uF B12 C256 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 AD3 B56 B57 AD1 B58 B59 B60 ACK64#1 B61 B62 TCK1 C234 0.01uF B +5V C277 0.01uF STOP_ L SERR_L PERR_L LOCK_L TCK2 C244 0.1uF C245 0.1uF 1 1 1 1 C78 0.1uF 2 2 2 2 C81 0.01uF +3.3V PCISLOT -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V U15 C80 0.01uF 5.1K R115 5.1K R109 5.1K R103 5.1K R96 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C254 B11 0.01uF B12 C257 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#2 B61 B62 C276 0.01uF 2 C243 0.1uF +5V TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V C79 0.1uF A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 R78 1 1 DEVSEL_L 1 IRDY_L TRDY_L FRAME_L 1 REQ64#2 AD2 AD0 AD6 AD4 C/BE0 AD9 AD13 AD11 AD15 SDONE2 SBO2_ L AD18 AD16 AD22 AD20 AD24 AD28 AD26 AD30 5.1K D R116 5.1K R110 5.1K R104 5.1K R97 5.1K R84 TMS2 1 R87 TDI2 1 5.1K 5.1K 1 TRST2_L D +3.3V 2 2 2 2 PAR +3.3V STOP_L TRDY_L FRAME_L IDSEL2_L GNT2_L RESET_L INTC_L INTA_L 2 2 2 REQ3_L CLK3 INTA_L INTC_L 5.1K R75 C321 0.01uF SERR_L LOCK_L PERR_L DEVSEL_L IRDY_L 1 2 Date: Size C Title B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C330 B11 0.01uF B12 C331 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#3 B61 B62 TCK3 TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V Friday, March 17, 2000 E Secondary 2 PCI Bus Document Number PI7C7100 +3.3V PAR STOP_ L TRDY_L FRAME_L IDSEL3_L GNT3_L RESET_L INTD_L INTB_L 2 2 2 Sheet 4 of 5 Rev 1.3 2380 Bering Dr., San Jose, CA R89 A1 TRST3_L 1 5.1K A2 R90 A3 TMS3 1 R88 A4 TDI3 1 5.1K 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE3 A41 SBO3_ L A42 A43 A44 AD15 A45 A46 AD13 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#3 A61 A62 Three Port PCI Bridge Evaluation Board PCISLOT -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V U12 E 1 2 3 4 ADVANCE INFORMATION Appendix C PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 04/18/00 C-7 1 2 3 C350 100p PLL_CAP2 C351 100p R150 4.7k C352 47p PCICHIP PLL_CAP2 PLL_CAP1 P_M66EN TRST_L TDO TDI TMS TCK P_RESETN P_PAR P_PERRN P_SERRN P_GNTN P_REQN P_AD[31:0] P_CBE[3:0] P_FRAMEN P_IRDYN P_TRDYN P_DEVSELN P_STOPN P_LOCKN P_IDSEL CHIP PCIEDGE IDSEL_L LOCK_L STOP_ L DVSEL_L TRDY_L IRDY_L FRAME_L C/BE[3:0] AD[31:0] REQ_L GNT_L SERR_L PERR_L PAR RESET_L TCK TMS TDI TDO TRST_L M66EN S2_GNTN[7:0] S2_REQN[7:0] S2_RESETN S2_PAR S2_PERRN S2_SERRN U19 Test Point T A S1_GNTN[7:0] R161 S1_GNTN0 1 S1_GNTN2 1 S1_GNTN4 1 S1_GNTN1 1 S1_GNTN3 1 2 0 0 R180 0 R178 2 2 S1_REQN4 1 S1_REQN0 1 S1_REQN2 1 B 0 0 R184 0 R182 R166 S1_GNTN0/4 S1_REQN1 1 0 R183 0 R181 R162 R165 2 S1_REQN5 1 0 2 2 S1_GNTN1/5 S1_REQN6 S1_REQN7 2 2 2 2 2 2 S2_GNTN[7:0] S2_REQN[7:0] 5.1K R199 S1_REQN0/4 S1_REQN1/5 S1_REQN2/6 S1_REQN3/7 S2_RESET_L S2_PAR_L S2_PERR_L S2_SERR_L S2_AD[31:0] S2_C/BE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_DEVSEL_ L S2_STOP _L S2_LOCK_L S_M66EN 0 0 R179 0 R177 S1_GNTN2/6 S1_GNTN6 S1_GNTN5 1 S1_GNTN3/7 S1_GNTN7 S1_REQN[7:0] S1_RESET_ L S1_PAR_L S1_PERR_L S1_SERR_L S1_AD[31:0] S1_C/BE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_DEVSEL_ L S1_STOP _L S1_LOCK_L S_CLK SCLKOUT[15:0] B S1_GNTN[7:0] S1_REQN[7:0] INTD_L INTC_L INTB_L INTA_L P_CLK S1_REQN3 1 S2_AD[31:0] S2_CBE[3:0] S2_FRAMEN S2_IRDYN S2_TRDYN S2_DEVSELN S2_STOPN S2_LOCKN S_M66EN S1_GNTN[7:0] S1_REQN[7:0] S1_RESETN S1_PAR S1_PERRN S1_SERRN S1_AD[31:0] S1_CBE[3:0] S1_FRAMEN S1_IRDYN S1_TRDYN S1_DEVSELN S1_STOPN S1_LOCKN PLL_SCLK SCLKOUT[15:0] PLL_PCLK INTD_L INTC_L INTB_L INTA_L CLK Note: Those AGNDs are only connected to a small GND plane on the top signal layer C349 47p R148 4.7k PLL_CAP1 P_M66EN TRST_L TDO TDI TMS TCK P_RESET_L P_PAR_L P_PERR_L P_SERR_L P_GNT_L P_REQ_L P_AD[31:0] P_C/BE[3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_DEVSEL_L P_STOP_ L P_LOCK_L P_IDSEL_L P_IDSEL_L P_LOCK_L P_STOP_ L P_DEVSEL_L P_TRDY_L P_IRDY_L P_FRAME_L P_C/BE[3:0] P_AD[31:0] P_REQ_L P_GNT_L P_SERR_L P_PERR_L P_PAR_L P_RESET_L TCK TMS TDI TDO TRST_L P_M66EN Edge 2 1 4 A S2_GNTN[7:0] 5.1K R49 S2_GNTN0 1 S2_GNTN2 1 S2_GNTN4 1 S2_GNTN1 1 S2_GNTN3 1 S2_GNTN5 1 S2_GNTN6 S2_GNTN7 1 0 0 R188 0 R186 R167 0 0 R187 0 R185 R163 2 2 2 2 2 2 2 INTA_L INTB_L INTC_L INTD_L C S2_GNTN0/4 S2_GNTN1/5 S2_GNTN2/6 PCIBUS2 INTA_L INTB_L INTC_L INTD_L REQ0_L REQ1_L REQ2_L REQ3_L GNT0_L GNT1_L GNT2_L GNT3_L S2_REQN5 1 S2_REQN6 S2_REQN7 CLK0 CLK1 CLK2 CLK3 CLK0 CLK1 CLK2 CLK3 S2_REQN0 1 S2_REQN2 1 S2_REQN4 1 S2_REQN1 1 S2_REQN3 1 RESET_L PAR PERR_L SERR_L AD[31:0] IDSEL0_L IDSEL1_L IDSEL2_L IDSEL3_L C/BE[3:0] FRAME_L IRDY_L TRDY_L DEVSEL_L STOP_ L LOCK_L M66EN S2_INTERFACE PCIBUS M66EN INTA_L INTB_L INTC_L INTD_L REQ0_L REQ1_L REQ2_L REQ3_L GNT0_L GNT1_L GNT2_L GNT3_L RESET_L PAR PERR_L SERR_L AD[31:0] IDSEL0_L IDSEL1_L IDSEL2_L IDSEL3_L C/BE[3:0] FRAME_L IRDY_L TRDY_L DEVSEL_L STOP_ L LOCK_L S1_INTERFACE S2_REQN[7:0] S2_REQN0/4 S2_REQN1/5 S2_REQN2/6 S2_REQN3/7 S2_GNTN0/4 S2_GNTN1/5 S2_GNTN2/6 S2_GNTN3/7 S2_RESET_L S2_PAR_L S2_PERR_L S2_SERR_L S2_IDSEL0_L S2_IDSEL1_L S2_IDSEL2_L S2_IDSEL3_L S2_C/BE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_DEVSEL_L S2_STOP _L S2_LOCK_L S2_GNTN3/7 +3.3V INTA_L INTB_L INTC_L INTD_L S1_REQN0/4 S1_REQN1/5 S1_REQN2/6 S1_REQN3/7 S1_GNTN0/4 S1_GNTN1/5 S1_GNTN2/6 S1_GNTN3/7 S1_RESET_ L S1_PAR_L S1_PERR_L S1_SERR_L S1_IDSEL0_L S1_IDSEL1_L S1_IDSEL2_L S1_IDSEL3_L S1_C/BE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_DEVSEL_ L S1_STOP _L S1_LOCK_L C 0 0 R192 0 R190 R168 0 0 R191 0 R189 R164 2 2 2 2 2 2 S1_IDSEL2_L S1_AD22 1 1 S2_REQN0/4 22 22 R170 22 R169 22 R146 22 R145 22 R144 R143 1 1 1 1 1 1 1 1 22 R176 22 R175 22 22 R174 22 R152 R149 22 22 R173 22 R151 R147 22 R172 22 R171 1 1 1 1 1 1 D 2 SCLKOUT15 2 SCLKOUT14 2 SCLKOUT13 2 SCLKOUT11 2 SCLKOUT9 2 SCLKOUT12 2 SCLKOUT10 2 SCLKOUT8 2 SCLKOUT7 2 SCLKOUT6 2 SCLKOUT5 2 SCLKOUT4 2 SCLKOUT3 2 SCLKOUT2 2 SCLKOUT1 2 SCLKOUT0 S1_IDSEL3_L S1_IDSEL1_L S1_AD21 S1_AD23 S1_IDSEL0_L D S1_AD20 S2_REQN1/5 S2_REQN2/6 S2_REQN3/7 SCLKOUT8/12 SCLKOUT9/13 SCLKOUT10/14 SCLKOUT11/15 SCLKOUT0/4 SCLKOUT1/5 SCLKOUT2/6 SCLKOUT3/7 S1_AD[31:0] S1_REQN0/4 S1_REQN1/5 S1_REQN2/6 S1_REQN3/7 S1_GNTN0/4 S1_GNTN1/5 S1_GNTN2/6 S1_GNTN3/7 1 1 1 1 1 1 1 1 T T T T T T T T U26 1header U27 1header U28 1header U29 1header U22 1header U23 1header U24 1header U25 1header S2_AD[31:0] Date: Size C Title 1 1 1 1 1 1 1 1 T T T T T T T T U34 1header U35 1header U36 1header U37 1header U30 1header U31 1header U32 1header U33 1header Test Point T U20 HEADER 6 1 2 3 4 5 6 P1 Friday, March 17, 2000 Top View Document Number PI7C7100 E U17 Test Point T Sheet 5 of 5 Rev 1.3 2380 Bering Dr., San Jose, CA Three Port PCI Bridge Evaluation Board S2_REQN0/4 S2_REQN1/5 S2_REQN2/6 S2_REQN3/7 S2_GNTN0/4 S2_GNTN1/5 S2_GNTN2/6 S2_GNTN3/7 +3.3V +5V S2_IDSEL3_L S2_IDSEL2_L S2_AD22 S2_AD23 S2_IDSEL1_L S2_IDSEL0_L S2_AD21 S2_AD20 E 1 2 3 4 ADVANCE INFORMATION Appendix C PI7C7100 3-Port PCI Bridge 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 04/18/00 ADVANCE INFORMATION Appendix C PI7C7100 3-Port PCI Bridge 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 C-8 04/18/00