ETC QS5805ATSO

QS5805T/AT/BT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS CLOCK
DRIVER/BUFFER
QS5805T/AT/BT
FEATURES:
DESCRIPTION:
−
−
The QS5805T clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of five non-inverting outputs. This device provides low propagation delay
buffering with on-chip skew of 0.7ns for same-transition, same-bank signals.
−
−
−
−
−
10 output, low skew signal buffer
Guaranteed low skew:
• 0.7ns output skew (same bank)
• 0.9ns output skew (different bank)
• 1ns part-to-part skew
Input hysteresis for better noise margin
Monitor output
Undershoot clamp diodes on all inputs
Std., A, and B speed grades
Available in QSOP and SOIC packages
The QS5805T is characterized for operation at -40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
OE A
5
OA 5
IN A
OA 1
MON
5
OB 5
IN B
OB 1
OE B
INDUSTRIAL TEMPERATURE RANGE
JULY 2000
1
c
1999
Integrated Device Technology, Inc.
DSC-5267
QS5805T/AT/BT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Symbol
VTERM(2)
(1)
Description
Supply Voltage to Ground
Max.
– 0.5 to +7
Unit
V
V CC A
1
20
V CC B
DC Output Voltage VOUT
– 0.5 to +7
V
OA1
2
19
OB1
VTERM(3)
DC Input Voltage VIN
– 0.5 to +7
V
OA2
3
18
OB2
VAC
AC Input Voltage (pulse width ≤20ns)
-3
V
IOUT
DC Input Diode Current VIN < 0
-20
mA
DC Output Current Max. Sink Current/Pin
120
mA
17
OB3
16
G ND B
15
OB4
7
14
OB5
G N DQ
8
13
MON
O EA
9
12
O EB
IN A
10
11
IN B
OA3
4
G ND A
5
OA4
6
OA5
SO20-2
SO20-8
TSTG
Storage Temperature
– 65 to +150
°C
TJ
Junction Temperature
150
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
QSOP/ SOIC
TOP VIEW
CAPACITANCE
(TA = +25OC, f = 1.0MHz, VIN = 0V)
Pins
CIN
Typ.
4
Max. (1)
6
Unit
pF
COUT
7
9
pF
NOTE:
1. This parameter is guaranteed but not production tested.
PIN DESCRIPTION
Pin Names
OEA, OEB
2
I/O
I
Description
Output Enable Inputs
INA, INB
I
Clock Inputs
OAn, OBn
O
Clock Outputs
MON
O
Unbuffered Monitor Output
QS5805T/AT/BT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = -40°C to +85°C, VCC = 5.0V ± 10%
Symbol
VIH
Parameter
Input HIGH Voltage
Test Conditions
Guaranteed Logic HIGH for All Inputs
Min.
2
Typ.(1)
—
Max.
—
Unit
V
VIL
Input LOW Voltage
Guaranteed Logic LOW for All Inputs
—
—
0.8
V
Vcc = Min., IIN = -18mA
—
–0.7
–1.2
V
Vcc = Min., IOH = -24mA
2.4
—
—
V
(3)
VIC
Clamp Diode Voltage
VOH
Output HIGH Voltage
Vcc = Min., IOH = -32mA
2
—
—
V
VOL
Output LOW Voltage
Vcc = Min., IOL = 64mA
—
—
0.55
V
IIN
Input Leakage Current
Vcc = Max., VIN = Vcc or GND
—
—
±1
µA
IOFF
Input/Output Power Off Leakage
Vcc = 0V, VIN or VOUT = Vcc or GND
—
—
±1
µA
IOZ
Output Leakage Current
Vcc = Max., VOUT = Vcc or GND
—
—
±1
µA
Vcc = Max., VOUT = GND
–60
—
–250
mA
VTLH - VTHL for All Inputs
—
0.2
—
V
IOS
Short Circuit Current
∆VT
Input Hysteresis
(2,3)
NOTES:
1. Typical values are at VCC = 5.0V, TA = 25°C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
POWER SUPPLY CHARACTERISTICS
Parameter
Quiescent Power Supply Current
Test Conditions (1)
VCC = Max., VIN = GND or Vcc
∆ICC
Supply Current per Input HIGH
ICCD
Dynamic Power Supply Current per Output (2)
IC
Total Power Supply Current Examples (2,4)
Symbol
ICC
Typ. (3)
0.005
Max.
0.5
Unit
mA
VCC = Max., VIN = 3.4V, fI = 0MHz
1
2.5
mA
VCC = Max., VIN = GND or Vcc
Outputs Enabled, 50% duty cycle
VCC = Max.,
OEA = OEB = GND
50% duty cycle, fI = 10MHz
Five outputs toggling
Unused inputs = GND or Vcc
VCC = Max.,
OEA = OEB = GND
50% duty cycle, fI = 2.5MHz
All outputs toggling
0.08
0.18
mA/MHz
VIN = GND or Vcc
4
9.5
mA
VIN = GND or 3.4V
4.5
10.8
VIN = GND or Vcc
2.2
5.5
VIN = GND or 3.4V
3.2
8
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Guaranteed by design but not tested. CL = 0pF.
3. Typical values are for reference only. Conditions are VCC = 5.0V, TA = 25°C.
4. IC = ICC + (∆ICC)(DH)(NT) + ICCD (fO)(NO)
where:
DH = Input Duty Cycle
NT = Number of TTL HIGH inputs at DH (one or two)
fO = Output Frequency
NO = Number of outputs at fO
3
QS5805T/AT/BT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SKEW CHARACTERISTICS OVER OPERATING RANGE
TA = -40°C to +85°C, VCC = 5.0V ± 10%
CLOAD = 50pF; RLOAD = 500Ω
QS5805T
Parameter (1)
Symbol
QS5805AT
QS5805BT
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tSK(01)
Skew between two outputs, same transition, same bank
—
0.7
—
0.7
—
0.7
ns
tSK(02)
Skew between two outputs, same transition, different banks
—
0.9
—
0.9
—
0.9
ns
tSK(P)
Pulse Skew; opposite transition skew, same output (tPHL - tPLH)
—
0.7
—
0.7
—
0.7
ns
tSK(T)
Part-to-part skew (2)
—
1.5
—
1
—
1
ns
NOTES:
1. Skew parameters are guaranteed across temperature range, but not tested. Skew parameters apply to propagation delays only.
2. tSK(T) only applies to devices of the same transition, part type, temperature, power supply voltage, loading, package, and speed grade.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TA = -40°C to +85°C, VCC = 5.0V ± 10%
CLOAD = 50pF; RLOAD = 500Ω
QS52805T
Symbol
tPLH
tPHL
tPZL
tPZH
tPLZ
tPHZ
tR
tF
Parameter (1)
Propagation Delay (2)
Output Enable Time
Output Disable Time
Output Rise Time, 0.8V to 2V (3)
Output Fall
Time, 2V to 0.8V (3)
QS52805AT
QS5805BT
Min.
Max.
Min.
Max.
Min.
Max.
Unit
1.5
6.5
1.5
5.8
1.5
5
ns
1.5
8
1.5
8
1.5
7
ns
1.5
7
1.5
7
1.5
6
ns
—
1.5
—
1.5
—
1.5
ns
—
1.5
—
1.5
—
1.5
ns
NOTES:
1. Minimums guaranteed but not production tested.
2. The propagation delay other range indicated by Min. and Max. specifications results from process and environmental variables. These propagation
delays do not imply limit skew.
3. This parameter is guaranteed but not tested.
4
QS5805T/AT/BT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
Parameter
Tested
Switch
Position
tPLZ, tPZL
Closed
All Others
Open
500Ω
V CC
6.0 V
V IN
V OUT
Pulse
Generator
DUT
50 Ω
50pF
500Ω
Pulse generator for all pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
PROPAGATION DELAY
PULSE SKEW — tSK(P)
3V
3V
1.5V
INPUT
0V
tPLH
1.5V
INPUT
tPHL
0V
VOH
2.0V
1.5V
0.8V
VOL
OUTPUT
tR
tPHL
tPLH
VOH
OUTPUT
1.5V
VOL
tF
tSK(p) = t PHL - tPLH
OUTPUT SKEW (SAME BANK) — tSK(O1)
OUPUT SKEW (DIFFERENT BANKS) — tSK(O2)
3V
3V
1.5V
INPUT
1.5V
INPUT
0V
0V
tPHL1
tPLH1
tPHLA
tPLHA
VOH
OUTPUT 1
VOH
OUTPUT A
1.5V
1.5V
VOL
tSK(01)
tSK(01)
VOL
OUTPUT 2
tSK(02)
tSK(02)
VOH
OUTPUT B
1.5V
1.5V
VOL
VOL
tPLH2
tPLHB
tPHL2
tSK(01) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHLB
tSK(02) = tPLHB - tPLHA or tPHLB - tPHLA
PART-TO-PART SKEW — tSK(T)
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
CONTROL
INPUT
1.5V
0V
tPLH1
tPLZ
tPHL1
VOH
3V
SWITCH
CLOSED
PART 1 OUTPUT
1.5V
VOL
tPHZ
tSK(t)
0.3V VOH
SWITCH
OPEN
1.5V
0.3V V OL
tPZH
OUTPUT
NORMALLY
HIGH
1.5V
INPUT
0V
tPZL
OUTPUT
NORMALLY
LOW
VOH
1.5V
tSK(t)
PART 2 OUTPUT
VOH
1.5V
VOL
0V
tPLH2
tPHL2
tSK(t) = t PLH2 - tPLH1 or tPHL2 - tPHL1
5
QS5805T/AT/BT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
QS
XXXX
XX
Device Type
Package
Q
SO
Quarter Size Small Outline Package (SO20-8)
Small Outline IC (SO20-2)
5805T
5805AT
5805BT
Guaranteed Low Skew CMOS Clock Driver/Buffer
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.
6