ETC TPS3600D20PWR

TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
features
typical applications
Supply Current of 40 µA (Max)
Precision Supply Voltage Monitor
– 2.0 V, 3.3 V, 5.0 V
– Other Versions on Request
Watchdog Timer With 800-ms Time-Out
Backup-Battery Voltage Can Exceed VDD
Power-On Reset Generator With Fixed
100-ms Reset Delay Time
Battery OK Output
Voltage Monitor for Power-Fail or
Low-Battery Monitoring
Manual Switchover to Battery-Backup
Mode
Chip-Enable Gating –3 ns (at VDD = 5 V)
Max. Propagation Delay
Manual Reset
Battery Freshness Seal
14-Pin TSSOP Package
Temperature Range . . . –40°C to 85°C
Fax Machines
Set-Top Boxes
Advanced Voice Mail Systems
Portable Battery Powered Equipment
Computer Equipment
Advanced Modems
Automotive Systems
Portable Long-Time Monitoring Equipment
Point of Sale Equipment
PW PACKAGE
(TOP VIEW)
VOUT
VDD
GND
MSWITCH
CEIN
BATTON
PFI
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VBAT
RESET
WDI
MR
CEOUT
BATTOK
PFO
typical operating circuit
Address
Decoder
Power
Supply
0.1 µF
External
Source
CEIN
Rx
VDD
VBAT
TPS3600
PFI
MR
uC
WDI
I/O
I/O
BATTOK
I/O
MSWITCH V
OUT
GND
8
RESET
PFO
BATTON
CE
CMOS
RAM
VCC
Address Bus
Backup
Battery
RESET
Ry
Manual
Reset
CEOUT
CE
CMOS
RAM
VCC
RealTime
Clock
VCC
8
Data Bus
16
I/O
Switchover
Capacitor
0.1 µF
VCC
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
description
The TPS3600 family of supervisory circuits monitor and control processor activity. In case of power-fail or
brownout conditions, the backup-battery switchover function of TPS3600 allows to run a low-power processor
and its peripherals from the installed backup battery without asserting a reset beforehand.
During power on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than 1.1 V.
Thereafter, the supply voltage supervisor monitors VOUT and keeps RESET output active as long as VOUT
remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state
(high) to ensure proper system reset. This delay timer starts its time-out, after VOUT has risen above the
threshold voltage (VIT). In case of a brownout or power failure of both supply sources, a voltage drop below the
threshold voltage (VIT) get detected and the output becomes active (low) again.
The product spectrum is designed for supply voltages of 2 V, 3.3 V, and 5 V. The circuits are available in a 14-pin
TSSOP package. The TPS3600 devices are characterized for operation over a temperature range of –40°C to
85°C.
PACKAGE INFORMATION
TA
DEVICE NAME
TPS3600D20
–40°C
85°C
40 C to 85
C
TPS3600D33
TPS3600D50
ordering information application specific versions (see Note)
TPS360
0
D
20
PW
R
Reel
Package
Nominal Supply Voltage
Nominal BATTOK Threshold Voltage
Functionality
Family
DEVICE NAME
NOMINAL VOLTAGE, VNOM
TPS3600x20 PW
TPS3600x25 PW
2.0 V
TPS3600x30 PW
3.0 V
TPS3600x33 PW
3.3 V
TPS3600x50 PW
5.0 V
DEVICE NAME
THRESHOLD VOLTAGE, VBOK
TPS3600Dxx PW
TPS3600Fxx PW
VIT + 7%
VIT + 6%
2.5 V
NOMINAL BATTOK
TPS3600Hxx PW
TPS3600Jxx PW
VIT + 8%
VIT + 10%
† For the application specific versions, please contact the local TI sales
office for availability and lead time.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
FUNCTION TABLES
VDD > VSW
0
VOUT > VIT
0
VDD > VBAT
0
MSWITCH
MR
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
VBAT > VBOK
0
BATTOK
1
1
VOUT
VBAT
BATTON
RESET
CEOUT
1
0
DIS
VBAT
VBAT
1
0
DIS
1
0
DIS
VBAT
VDD
1
0
DIS
0
0
DIS
VDD
VBAT
0
0
DIS
1
0
DIS
VBAT
VBAT
1
0
DIS
1
0
DIS
VBAT
VBAT
1
1
EN
1
0
DIS
VBAT
VDD
1
1
EN
0
0
DIS
VDD
VBAT
0
1
EN
1
0
DIS
VBAT
VDD
1
1
EN
0
0
DIS
VDD
VBAT
VBAT
0
1
EN
1
0
DIS
1
1
EN
VDD
VDD
0
0
DIS
0
1
EN
VBAT
VBAT
1
0
DIS
1
1
EN
0
CONDITION: VOUT > VDD(min)
CEIN
CEOUT
0
0
1
1
CONDITION: Enabled
PFI > VPFI
PFO
0
0
1
1
CONDITION: VOUT > VDD(min)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
functional schematic
TPS3600
MR
MSWITCH
VBAT
+
_
Switch
Control
VOUT
Power to
Circuitry
VDD
BATTON
+
_
Reference
Voltage
or 1.15 V
BATTOK
R1
GND
_
+
R2
RESET
Logic
and
Timer
RESET
_
PFO
+
PFI
Oscillator
WDI
Transition
Detector
Watchdog
Logic
and
Control
VOUT
40 kΩ
CEOUT
CEIN
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
timing diagram
VBAT
V(BOK)
V(SWP)
V(SWN)
VIT
VDD
1.1 V
t
VOUT
VBAT
V(SWP)
V(SWN)
t
BATTOK
1
V(BOK)
0
t
RESET
t
BATTON
t
Undefined Behavior
NOTES: A. MSSWITCH = 0, MR = 1
B. Timing diagram shown under normal operation, not in freshness seal mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BATTOK
9
O
Battery status output
BATTON
6
O
Logic output/external bypass switch driver output
CEIN
5
I
Chip-enable input
CEOUT
10
O
Chip-enable output
GND
3
I
Ground
MR
11
I
Manual reset input
MSWITCH
4
I
Manual switch to force device into battery-backup mode
PFI
7
I
Power-fail comparator input
PFO
8
O
Power-fail comparator output
RESET
13
O
Active-low reset output
VBAT
VDD
14
I
Backup-battery input
2
I
Input supply voltage
1
O
Supply output
12
I
Watchdog timer input
VOUT
WDI
detailed description
battery freshness seal
The battery freshness seal of the TPS3600 family disconnects the backup battery from the internal circuitry until
it is needed. This ensures that the backup battery connected to VBAT should be fresh when the final product is
put to use. The following steps explain how to enable the freshness seal mode:
1. Connect VBAT (VBAT > VBAT(min) or VDD(min))
2. Ground PFO
3. Connect PFI to VDD (PFI = VDD)
4. Connect VDD to power supply (VDD > VIT) and keep connected for 5 ms < t < 35 ms
The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied.
BATTOK output
This is a logic feedback of the device to indicate the status of the backup battery. The supervisor checks the
battery voltage every 200 ms with a voltage divider load of approximately 100 KΩ and a measure cycle on-time
of 25 µs. This measurement cycle starts after the reset is released. If the battery voltage VBATT is below the
negative-going threshold voltage V(BOK), the indicator BATTOK does a high-to-low transition. Otherwise, it its
status remains to the VOUT level.
Table 1. Typical Values for BATTOK Indication
SUPERVISOR TYPE
6
TPS3600x20
VIT TYP
1.78 V
VBOK MIN
1.84 V
VBOK TYP
1.91 V
VBOK MAX
1.97 V
TPS3600x33
2.93 V
3.04 V
3.14 V
3.24 V
TPS3600x50
4.40 V
4.56 V
4.71 V
4.86 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
detailed description (continued)
I
25 µs
200 ms
100 µA
t
Figure 1. BATTOK Timing
chip-enable signal gating
The internal gating of chip-enable (CE) signals prevents erroneous data from corrupting CMOS RAM during
an under-voltage condition. The TPS3600 use a series transmission gate from CEIN to CEOUT. During normal
operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset
is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short
CE propagation delay from CEIN to CEOUT enables the TPS3600 devices to be used with most processors.
The CE transmission gate is disabled and CEIN is high impedance (disable mode) while reset is asserted.
During a power-down sequence when VDD crosses the reset threshold, the CE transmission gate will be
disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low during
reset is asserted, the CE transmission gate will be disabled same time when CEIN goes high, or 10 µs after reset
asserts, whichever occurs first. This will allow the current write cycle to complete during power down. When the
CE transmission gate is enabled, the impedance of CEIN appears as a 50-Ω resistor in series with the load at
CEOUT. To achieve minimum propagation delay, the capacitive load at CEOUT should be minimized, and a
low-output-impedance driver be used.
During disable mode, the transmission gate is off and an active pullup connects CEOUT to VOUT. This pullup
turns off when the transmission gate is enabled.
VDD
VBAT
V(BOK)
V(SWP)
V(SWN)
VIT
1.1 V
VDD
VBAT
CEIN
V(BOK)
V(SWP)
V(SWN)
VIT
10 µs
COUT
RESET
td
td
10 µs
td
V(SWN)
VIT
Undefined Behavior
Figure 2. Chip-Enable Timing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
detailed description (continued)
VDD
VDD
VBAT
3.6 V
25 Ω Equivalent
Source Impedance
TPS3600
50 Ω Cable
50 Ω
CEIN
CEOUT
CL†
50 pF
50 Ω
GND
† CL Includes load capacitance and scope probe capacitance.
Figure 3. CE Propagation Delay Test Circuit
power-fail comparator (PFI and PFO)
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail
input (PFI) will be compared with an internal voltage reference of 1.15 V. If the input voltage falls below the
power-fail threshold (V(PFI)) of 1.15 V typical, the power-fail output (PFO) goes low. If it goes above 1.15 V plus
about 20-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to
supervise any voltages above 1.15 V. The sum of both resistors should be about 1 MΩ, to minimize power
consumption and also to ensure that the current in the PFI pin can be neglected compared with the current
through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure
minimal variation of sensed voltage.
If the power-fail comparator is unused, connect PFI to ground and leave PFO unconnected.
BATTON
Most often BATTON is used as a gate or base drive for an external pass transistor for high-current applications.
In addition it can be also used as a logic output to indicate the battery switchover status. BATTON is high when
VOUT is connected to VBAT.
BATTON can be directly connected to the base of a PNP transistor (see Figure 4a) or the gate of a PMOS
transistor (see Figure 4b). No current-limiting resistor is required, but a resistor connecting the base of the PNP
to BATTON can be used to limit the current drawn from VDD, prolonging battery life in portable equipment. If
you are using a PMOS transistor, however, it must be connected backwards from the traditional method (see
Figure 4b). This method orients the body diode from VDD to VOUT and prevents the backup battery from
discharging through the FET when its gate is high.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
detailed description (continued)
PMOS FET
Body Diode
3 V or 3.3 V
To CMOS RAM
D
S
G
VDD BATTON VOUT
VDD BATTON VOUT
TPS3600
TPS3600
GND
GND
(a)
(b)
Figure 4. Driving an External Transistor With BATTON
backup-battery switchover
In the event of a brownout or power failure, it may be necessary to keep a processor running. If a backup battery
is installed at VBAT, the devices automatically connect the processor to backup power when VDD fails. In order
to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, this family of supervisors
will not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 2-Ω switch)
when VOUT falls below VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred either until
VDD crosses VBAT, or when VDD rises above the threshold (V(SWP). VOUT will connect to VDD through a 2-Ω (max)
PMOS power switch when VDD crosses the reset threshold.
VDD > VBAT
1
VDD > V(SW)
1
VOUT
VDD
1
0
0
1
VDD
VDD
0
0
VBAT
manual switchover (MSWITCH)
While operating in the normal mode from VDD, the device can be manually forced to operate in the
battery-backup mode by connecting MSWITCH to VDD. The table below shows the different switchover modes.
MSWITCH
GND
VDD mode
Battery back p mode
Battery-backup
VDD
GND
VDD
STATUS
VDD mode
Switch to battery-backup mode
Battery-backup mode
Battery-backup mode
If the manual switchover feature is not used, MSWITCH must be connected to ground.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
detailed description (continued)
watchdog
In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also
important to ensure the correct program execution. The task of a watchdog is to ensure that the program is not
stalled in an indefinite loop. The microprocessor, microcontroller, or the DSP have to toggle the watchdog input
within typically 0.8 s to avoid a time-out from occurring. Either a low-to-high or a high-to-low transition resets
the internal watchdog timer. If the input is unconnected the watchdog is disabled and will be retriggered
internally.
saving current while using the watchdog
The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily
pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power
consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once
within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead, WDI is externally driven high
for the majority of the time-out period, a current of e.g. 5 V/40 kΩ ≈ 125 µA can flow into WDI.
VOUT
VIT
VBAT
WDI
Time-Out
RESET
td
td
Figure 5. Watchdog Timing
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage: VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Continuous output current at VOUT: IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mA
All other pins, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PW
700 mW
5.6 mW/°C
448 mW
364 mW
recommended operating conditions at specified temperature range
MIN
Supply voltage, VDD
MAX
1.65
Battery supply voltage, VBAT
Input voltage, VI
High-level input voltage, VIH
UNIT
5.5
V
1.5
5.5
V
0
VO + 0.3
V
0.7 x VO
Low-level input voltage, all other pins, VIL
V
0.3 x VO
V
Continuous output current at VO, IO
200
Input transition rise and fall rate at WDI, MSWITCH, ∆t/∆V
100
ns/V
34
mV/µs
85
°C
Slew rate at VDD or VBAT
Operating free-air temperature range, TA
–40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mA
11
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
High-level output
voltage
TEST CONDITIONS
Low-level output
voltage
IOH = –2 mA
IOH = –3 mA
VOUT – 0.4 V
VO = 1.8 V,
VO = 3.3 V,
VO = 5.0 V,
IOH = –20 µA
VOUT – 0.3 V
PFO
IOH = –80 µA
IOH = –120 µA
VOUT – 0.4 V
CEOUT
Enable mode
CEIN = VOUT
CEOUT
Disable mode
VO = 2.0 V,
VO = 3.3 V,
VO = 5.0 V,
IOH = –1 mA
VOUT – 0.2 V
IOH = –2 mA
IOH = –5 mA
VOUT – 0.3 V
VO = 3.3 V,
IOH = –0.5 mA
VOUT – 0.4 V
RESET
VO = 2.0 V,
VO = 3.3 V,
IOL = 400 µA
BATTOK
VO = 5.0 V,
VO = 1.8 V,
IOL = 3 mA
IOL = 500 µA
0.2
BATTON
VO = 3.3 V,
VO = 5.0 V,
VO = 2.0 V,
IOL = 3 mA
IOL = 5 mA
0.4
IOL = 1 mA
0.2
VO = 3.3 V,
VO = 5.0 V,
VBAT > 1.1 V
VDD > 1.4 V,
IO = 5 mA,
IOL = 2 mA
IOL = 5 mA
0.3
Power-up reset voltage (see Note 2)
Battery backup mode
Battery-backup
V(PFI)
V(BOK)
V(SWN)
IO = 75 mA,
VDD = 3.3 V
VDD to VO on-resistance
VBAT to VO on-resistance
Negative-going input
in ut
threshold voltage
(see Notes 3 and 4)
V
0.2
IOL = 2 mA
OR
IOL = 20 µA
VDD = 1.8 V
IO = 75 mA, VDD = 3.3 V
IO = 150 mA, VDD = 5 V
IO = 4 mA,
VBAT = 1.5 V
VO
VIT
UNIT
RESET
BATTOK
BATTON
Normal mode
rds(on)
d ( )
MAX
VOUT – 0.2 V
CEOUT
Enable mode
CEIN = 0 V
Vres
TYP
IOH = –400 µA
PFO
VOL
MIN
VO = 2.0 V,
VO = 3.3 V,
VO = 5.0 V,
VBAT = 3.3 V
04
0.4
0.4
VDD – 50 mV
VDD – 150 mV
VDD – 250 mV
V
V
V
VBAT – 50 mV
VBAT – 150 mV
VBAT = 3.3 V
1
2
1
2
Ω
TPS3600x20
1.74
1.78
1.82
V
TPS3600x25
2.17
2.22
2.27
V
TPS3600x30
2.57
2.63
2.69
V
2.87
2.93
2.99
V
TPS3600x50
4.31
4.40
4.49
V
PFI
1.13
1.15
1.17
TPS3600x33
TA = –40°C
40 C to 85°C
85 C
TPS3600Dxx
Battery switch threshold voltage
negative-going VO
VIT + 5.8%
VIT + 7.1%
VIT + 8.3%
VIT + 1%
VIT + 2%
VIT + 3.2%
V
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr(VDD) ≥ 15 µs/V.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal.
4. Voltage is sensed at VO
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
(continued)
PARAMETER
TEST CONDITIONS
VIT
BATTOK
Vhys
Hysteresis
MIN
1.65 V < VIT < 2.5 V
20
2.5 V < VIT < 3.5 V
40
3.5 V < VIT < 5.5 V
50
1.65 V < V(BOK) < 2.5 V
30
2.5 V < V(BOK) < 3.5 V
60
3.5 V < V(BOK) < 5.5 V
100
PFI
V(SWN)
High level input current
High-level
UNIT
mV
12
V(BSW)
IIH
MA
X
TYP
VDD = 1.8 V
1.65 V < V(SWN) < 2.5 V
66
2.5 V < V(SWN) < 3.5 V
100
3.5 V < V(SWN) < 5.5 V
110
WDI (see Note 5)
WDI = VDD = 5 V
MR
MR = 0.7 × VDD, VDD = 5 V
WDI (see Note 5)
WDI = 0 V,
VDD = 5 V
VDD = 5 V
85
150
–33
–76
–150
IIL
Low level input current
Low-level
MR
MR = 0 V,
II
Input current
PFI, MSWITCH
VI < VDD
PFO = 0 V,
Short-circuit
Short
circuit current
PFO
PFO = 0 V,
VDD = 1.8 V
VDD = 3.3 V
–0.3
IOS
PFO = 0 V,
VDD = 5 V
–2.4
IDD
VDD supply current
VO = VDD
VO = VBAT
I(BAT)
VBAT supply current
VO = VDD
VO = VBAT
Ilkg
CEIN leakage current
Disable mode, VI < VDD
Ci
Input capacitance
–110
–255
–25
25
–1.1
40
8
–0.1
VI = 0 V to 5.0 V
NOTE 5: For details on how to optimize current consumption when using WDI, see the detailed description section.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.1
40
±1
5
µA
nA
mA
µA
A
µA
µA
pF
13
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
timing requirements at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 85°C
PARAMETER
tw
Pulse width
TEST CONDITIONS
VDD
MR
WDI
VIH = VIT + 0.2 V, VIL = VIT – 0.2 V
VDD > VIT + 0.2
0 2 V,
V VIL = 0
0.3
3 x VDD, VIH = 0
0.7
7 x VDD
MIN
TYP
MAX
UNIT
6
µs
100
ns
switching characteristics at RL= 1 MΩ, CL = 50 pF, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
td
Delay time
VDD ≥ VIT + 0.2 V,
MR ≥ 0.7 x VDD,
See timing diagram
t(tout)
Watchdog time-out
VDD > VIT + 0.2 V,
See timing diagram
tPLH
Propagation (delay) time,
low-to-high-level output
tPHL
Propagation (delay) time,
high-to-low-level output
MAX
UNIT
60
100
140
ms
0.48
0.8
1.12
s
µs
VOUT = VIT
VDD to RESET
VIL = VIT – 0.2 V,
VIH = VIT + 0.2 V
2
5
µs
PFI to PFO
VIL = V(PFI) – 0.2 V,
VIH = V(PFI) + 0.2 V
3
5
µs
0.1
1
µs
5
15
ns
1.6
5
ns
1
3
ns
3
µs
MR to RESET
VDD to BATTON
VDD ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
VDD < 1.8 V
VDD < 3.3 V
VDD < 5 V
VIL = V(BAT) – 0.2 V,
VIH = V(BAT) + 0.2 V,
V(BAT) < VIT
NOTE 6: Assured by design.
14
TYP
50% RESET to 50% CEOUT
50% CEIN to
t 50% CEOUT
CL = 50 pF only (see Note 6)
Transition time
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: C.
D.
E.
F.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated