WIRELESS COMMUNICATIONS DIVISION TQ9142B RF OUT RFOUT 1 16 GND 2 15 GND VG3 3 14 VD2 GND 4 13 GND GND 5 12 GND RFIN 6 11 VG2 GND 7 10 GND VG1 8 9 VD1 DATA SHEET High-Efficiency 3-Stage AMPS Power Amplifier IC Features TQ9142B 60% drain efficiency +31.0 dBm power output @4.8V Product Description 4.8 V to 6.0 V battery operation The TQ9142B is a highly efficient 3-stage power amplifier developed for handsets S0-16 package and portable terminals operating in the AMPS cellular band (824 to 849 MHz). The part is designed to require minimal external circuitry for matching or bias, simplifying design and keeping board space and cost to a minimum. Access to each stage’s 50-ohm matched input gate and drain voltages is provided for maximum flexibility in selection of output power control method, making output power vs. efficiency tradeoffs, or for implementing alternative biasing schemes. The amplifier is packaged in a SOIC-16 plastic package with specially modified central thermal tabs. These tabs provide reliable operation for the 1.4 Watt power output. Electrical Specifications1 Parameter Min Typ Output Power +30 +31 dBm Efficiency 55 60 % 10 dB Input Return Loss Max Applications AMPS Mobile Phones CDPD Terminals/Modems Units Note 1: Test Conditions: VDD = 4.8 V, VGG = -3.5 V, Freq. = 836 MHz, PIN = 0 dBm, TC = 25° C Note 2: Min/max values 100% production tested. For additional information and latest specifications, see our website: www.triquint.com 1 TQ9142B Data Sheet Electrical Characteristics 1 Parameter Frequency Conditions Min tuned for cellular band Typ 824 Max Units 849 MHz 2.7 5.0 7.00 V -40 25 +110 oC 30.0 31.0 dBm 55 60 % Input Return Loss 10 dB Power Control Range 25 dB Rx Band Noise -88 dBc 40 dB -35 -45 dBc dBc Supply Voltage (VDD) Temperature measured at case POUT Efficiency 2 Small Signal Gain PIN = -10 dBm Harmonics 2nd Harmonic 3rd Harmonic Negative Supply Current Spurious (Stability) 3 2 PIN = -40 to +0 dBm -80 Ruggedness 4 5 mA dBc No degradation Note 1: Test Conditions: VDD = 4.8 V, VGG = -3.5 V, Freq. = 836 MHz, PIN = 0 dBm, BW = 30 kHz, TC = 25° C. Note 2: Load VSWR set to 7:1 and angle varied 360o. All spurious outputs less than –80 dBc. No large-signal oscillations permitted Note 2: Noise power measured in 30 kHz bandwidth at the transmit frequency plus 45 MHz. Note 2: Burnout testing. Load set to 50 ohms, output power measured at nominal test conditions. Load VSWR set to 10:1 and the angle varied 360o over 60 seconds. Load set to 50 ohms; output power is measured again and compared with the first measurement to check for no degradation from first measurement. Absolute Maximum Ratings Parameter Value Units DC Power Supply 8.0 V DC Gate Voltage -5.0 to –0.5 V RF Input Power +10 dBm Storage Temperature -55 to +150 °C Operating Temperature (case) -40 to +125 °C 5 °C/Watt Theta j-c 2 For additional information and latest specifications, see our website: www.triquint.com TQ9142B Data Sheet Typical Performance Test Conditions (Unless Otherwise Specified): VDD = 4.6 V, Freq. = 836 MHz, VGG = -3.5 V, PIN = 0 V, VBC = 2.7 V, TC = 25° C Efficiency vs. Frequency vs. Temperaure 32 70 31 65 30 60 29 Efficiency (%) 25 C 28 -40 C 27 100 C 26 55 50 25 C 45 -40 C 100 C 40 800 800 810 820 830 840 850 860 870 880 810 820 60 60 25 45 Eff 849 MHz 6 6.5 50 20 40 15 30 10 5 POUT 35 0 Eff 30 -5 40 Eff 836 MHz Output Power (dBm) 65 Efficiency (%) POUT (dBm) 70 Po 849 MHz 5.5 20 10 0 0 7 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VD2 (V) VDD (V) Efficiency vs. Freq. vs. Temp (POUT=30 dBm) VD2 vs. Frequency vs. Temp (POUT=30 dBm) 70 5 65 Efficiency (%) 4 VD2 (V) 880 30 50 5 870 35 Po 836 MHz Eff 824 MHz 4.5 860 70 55 Po 824 MHz 4 850 Output Power & Eff vs. VD2 Output Power & Eff. vs. VDD vs. Frequency 34 33 32 31 30 29 28 27 26 25 24 840 Frequency (MHz) Frequency (MHz) . 830 Efficiency (%) Output Power (dBm) Output Power vs. Frequency vs. Temperature 3 VDC 25 C 2 VDC -40 C 1 60 55 Eff 25 C 50 Eff -40 C 45 VDC 100 C Eff 100 C 40 0 800 810 820 830 840 850 Frequency (MHz) 860 870 880 800 810 820 830 840 850 860 870 880 Frequency (MHz) For additional information and latest specifications, see our website: www.triquint.com 3 TQ9142B Data Sheet Typical Performance Test Conditions (Unless Otherwise Specified): VDD = 4.6 V, Freq. = 836 MHz, VGG = -3.5 V, PIN = 0 V, VBC = 2.7 V, TC = 25° C. Fundamental & Harmonics vs. Frequency 40 30 60 30 -20 -15 -10 -5 0 5 10 -30 Frequency (MHz) Input Power (dBm) S11 vs. Frequency 0 -5 S11 (dB) -10 -15 -20 -25 -30 800 810 820 830 840 850 860 870 Frequency (MHz) 4 For additional information and latest specifications, see our website: www.triquint.com 4245 10 4120 10 -20 3344 20 2547 Eff 15 0 -10 2472 30 POUT 1672 20 10 849 40 20 824 50 25 Power (dBm) 70 Efficiency (%) Output Power (dBm) Output Power & Eff. vs. Input Power 35 TQ9142B Data Sheet Application/Test Circuit VCntrl (0 to 4.8V) 5 RFOUT RFOUT 16 2 GND GND 15 3 VG3 VD2 14 4 GND C5 TQ9142B GND VG2 11 7 GND GND 10 8 VG1 VD1 9 7 R2 2 VPDWN VDD R7 R3 C7 1 Q1 8 2 R5 C6 VPCNTRL 3 1 VDD 12 RFIN RFOUT 8 13 6 6 C2 C4 5 RFIN 50 Ohm VDD MAX850 1 R1 C1 C3 4 Si9947 L1 3 R4 VDD 7 6 5 4 SHDN R6 Bill of Material for TQ9142B Power Amplifier Application/Test Circuit Component Reference Designator Power Amplifier IC PNP Transistor Part Number Value TQ9142B Size Manufacturer Power SO-16 TriQuint Semiconductor Q1 2N3906 Capacitor C1, C4, C5, C6, C7 MCH155F103ZK 0.1 µF 0402 Rohm Capacitor C2 MCH155A8R2CK 8.2 pF 0402 Rohm Capacitor C3 MCH155A330JK 33 pF 0402 Rohm Resistor R1 MCR01JW100 10 Ω 0402 Rohm Resistor R2 MCR01JW240 24 Ω 0402 Rohm Resistor R3 MCR01JW1R3 1.3 kΩ 0402 Rohm Resistor R4 MCR01JW221 220 Ω 0402 Rohm Resistor R5 MCR01JW3R6 3.6 kΩ 0402 Rohm Resistor R6 MCR01JW1R3 1.0 kΩ 0402 Rohm Resistor R7 MCR01JW510 51 Ω 0402 Rohm Inductor L1 KL32TE047J 47 nH 1210 KOA For additional information and latest specifications, see our website: www.triquint.com 5 TQ9142B Data Sheet TQ9142B Operation The TQ9142B is a gallium arsenide (GaAs) power FET amplifier. It has three stages of gain and features 1 Watt output power at 60% drain efficiency. It can operate at supply voltage from 4.8 to 6.0 V. The device is optimized for operation at The specific values required for optimum performance vary slightly due to fabrication tolerances in FET pinchoff voltage. The active bias circuit overcomes these small variations and provides the extremely repeatable performance and operation frequencies from 824 to 849 MHz. The input is matched to 50 ohms and a simple output match and bypassing complete the minimal external circuitry required for normal operation. The need for high volume production output match and all gate and drain voltages are access8ible, allowing the device to be optimized for supply voltage, output power and efficiency. positive. Efficiency tends to rise to a peak, then to decrease with more positive gate voltage. See the POUT and efficiency vs. VG2 plots. The TQ9142B is packaged in a low-cost SOIC-16 package with thermal tabs. It is optimized for use as the transmit amplifier in analog cellular (AMPS) phones and Cellular Digital Packet Data (CDPD) wide-area network (WAN) applications. Its high Quiescent current, the total drain current flowing with no RF drive, also tends to increase with more positive gate voltage, and must be considered when selecting “optimum” gate bias efficiency, high output power and ease of use make the TQ9142B an excellent solution for RF system designers with tight time to market and cost requirements. Gate Biasing A negative voltage is required to bias the TQ9142B Power Amplifier. This is usually generated from the battery voltage with a commercially available charge pump IC such as the Harris 7660 or one of the Maxim 850 series Negative Supply Generator ICs. A simple resistive voltage divider can be used to produce the gate voltages for each stage, but the most consistent operation of the amplifier will be obtained by using the active bias circuit shown in the Application/Test Circuit Schematic. The following table gives the approximate values of gate voltage for the TQ9142B at 4.8 V and at 5.8 V. Nominal Gate Bias Voltages 6 VDD 4.8 V 5.8 V VG1 -1.3 V -1.0 V VG2 -1.3 V -1.4 V VG3 -1.8 V -1.7 V For a fixed output-matching network, output power increases monotonically but gradually, as gate voltage becomes more voltages. The bias stabilization circuit used in the Application /Test Circuit Schematic does an excellent job of controlling quiescent current with variations in FET pinch-off voltage. As with all GaAs power FETs, it is imperative to ensure that the gate bias is present before applying the drain voltage. Without the gate control, the drain current will rise to full IDSS (-1.5 A), which is potentially destructive to power FETs which are designed to operate at 20% to 50% of IDSS. This is usually more of a problem in a lab test environment, but it is a good idea to provide safeguards in the circuit design to minimize the risk that VDD is applied for any significant length of time without VGG applied. Output Match For maximum output power and efficiency, the output matching circuit for the TQ9142B is implemented off-chip with high-Q components. The use of external matching elements allows for some tradeoff adjustments to be made between supply voltage, output power and efficiency. It also allows some flexibility for optimizing the performance in different frequency ranges near the cellular band. The desired output match impedance for optimum output power should have the impedance for optimum output power should have the impedance shown in the following table. For additional information and latest specifications, see our website: www.triquint.com TQ9142B Data Sheet Output Power Match Output Match Topology – Lumped Inductance VDD 4.8 V 5.8 V ο S11 .76=∠−179 Impedance 6.77 – j.36 ohm VDD .73=∠−178ο 7.74 + j.74 ohm >43 nH The basic output network for the TQ9142B, (and for most GaAs FET power amplifiers), consists of a series inductor followed by TQ9142B a shunt capacitor. An RF choke for bringing the output stage supply voltage and a DC blocking capacitor are also needed. The series inductance can be realized using a series transmission line or a combination of a series transmission line LSERIES 50 Ω Transmission Line -33 pF CSHUNT Lumped Inductor Power Match with a lumped element inductor. The transmission line characteristic impedance should be kept at 50 ohms. VDD 4.8 V 5.8 V LSERIES 3.3 nH 3.9 nH The preferred topology for the output match is shown in the CSHUNT 10 pF 8.2 pF following figures for both the transmission line approach and the combination transmission line/lumped inductor approach. Output Match Topology – Transmission Line been made here to estimate the approximate value of the physical lumped inductor. The closest standard values of lumped inductors that are lower than the required values are 2.2 >43 nH -33 pF RFOUT (50 Ω ) 50 ohm CSHUNT Please note that the value shown in the table for LSERIES includes the equivalent inductance of any transmission line connecting the power amplifier to the inductor and any transmission line connecting the inductor to the shunt capacitor. Since these lines vary significantly from layout to layout, no attempt has VDD TQ9142B RFOUT (50 Ω ) nH and 1.8 nH. The connecting transmission lines must be kept fairly short since lumped inductors with values of less than 1.2 nH are not available in most sizes. Power Control The best method of power control for the TQ9142B is to vary VD2. It is also possible to vary any of the gate voltages to achieve the same result, but the bias stabilization circuit shown Transmission Line Power Match VDD 4.8 V 5.8 V Line Length 338 mils 365 mils CSHUNT 8.2 pF 6.8 pF in the Application/Test Schematic works best if VD2 is the control voltage. Power Down Function To achieve minimum current leakage in standby mode, a silicon PMOS switching FET (PFET) such as the Siliconix SI9947 can be used in series with the supply voltage. When VSTANDBY For additional information and latest specifications, see our website: www.triquint.com 7 TQ9142B Data Sheet (active high) is applied to the gate of the PFET, the switch is turned off and only a few microamperes of current will flow. When VSTANDBY = 0, the switch is turned on and VDD is applied to the power amplifier. Typically, the switch will drop the supply voltage by 0.1 to 0.2 V. Single Supply Operation (Negative Voltage Generators Depletion-mode GaAs power FETs require a negative gate bias voltage with respect to the grounded source. Several highly efficient negative supply generator ICs are available, such as the Maxim MAX850. The Application Circuit Schematic includes the negative supply. The silicon PFET and the bias circuit to illustrate a complete solution suitable for many cellular telephone designs. 8 For additional information and latest specifications, see our website: www.triquint.com TQ9142B Data Sheet Package Pinout RFOUT 1 16 RFOUT GND 2 15 GND VG3 3 14 VD2 GND 4 5 GND TQ9142B RFIN 6 11 VG2 GND 7 10 GND VG1 8 9 VD1 Pin Descriptions Pin Name Pin # Description and Usage RFOUT 1, 16 Power amplifier output. Simple bur critical matching circuit required. VG3 3 Output stage gate voltage. Requires series resistor near device for stability. Local bypass capacitor required. RFIN 6 Power amplifier input. Matched to 50 ohms. Internal DC block. VG1 8 First- stage gate voltage. Set VG1 = -1.5V or use bias stabilization circuit. VD1 9 Input stage supply voltage. Local bypass capacitor recommended. Use the same voltage as VD3 or use bias stabilization circuit. VG2 11 Second stage gate voltage. Local bypass capacitor required. VD2 14 Second stage drain voltage. Local bypass capacitor required. Use the same voltage as VD3 GND 2, 4, 5, 7, 10,12,13,15 Ground connections. Provide thermal path for heat dissipation and RF grounding. Very important to place multiple via holes immediately adjacent to the pins. Revision E TQS Wireless Communications 8900 • 2300 NE Brookwood Parkway • Hillsboro, OR 97124 • (503) 615-9000 • December 12, 2000 FAX:(503) 615- TQ9142B Data Sheet Package Type: SOIC-16 Plastic Package with Thermal Tabs Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Tel: (503) 615-9000 Email: [email protected] Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1998 TriQuint Semiconductor, Inc. All rights reserved. Revision E, December 12, 2000 10 For additional information and latest specifications, see our website: www.triquint.com