UC1633 UC2633 UC3633 Phase Locked Frequency Controller FEATURES • • • • DESCRIPTION Precision Phase Locked Frequency Control System The UC1633 family of integrated circuits was designed for use in phase locked frequency control loops. While optimized for precision speed control of DC motors, these devices are universal enough for most apCrystal Oscillator plications that require phase locked control. A precise reference freProgrammable Reference Frequency quency can be generated using the device’s high frequency oscillator Dividers and programmable frequency dividers. The oscillator operates using a Phase Detector with Absolute Frequency broad range of crystals, or, can function as a buffer stage to an external frequency source. Steering • Digital Lock Indicator • Double Edge Option on the Frequency Feedback Sensing Amplifier • Two High Current Op-Amps • 5V Reference Output The phase detector on these integrated circuits compares the reference frequency with a frequency/phase feedback signal. In the case of a motor, feedback is obtained at a hall output of other speed detection device. This signal is buffered by a sense ampilfier that squares up the signal as it goes into the digital phase detector. The phase detector responds proportionally to the phase error between the reference and the sense amplifier output. This phase detector includes absolute frequency steering to provide maximum drive signals when any frequency error exists. This feature allows optimum start-up and lock times to be realized. Two op-amps are included that can be configured to provide necessary loop filtering. The outputs of the op-amps will source or sink in excess of 16mA, so they can provide a low impedence control signal to driving circuits. BLOCK DIAGRAM Additional features include a double edge option on the sense amplifier that can be used to double the loop reference frequency for increased loop bandwidths. A digital lock signal is provided that indicates when there is zero frequency error, and a 5V reference output allows DC operating levels to be accurately set. 4/97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1 UC1633 UC2633 UC3633 ABSOLUTE MAXIMUM RATINGS Input Supply Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . +20V Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . -30mA Op-Amp Output Currents . . . . . . . . . . . . . . . . . . . . . . . . ±30mA Op-Amp Input Voltages . . . . . . . . . . . . . . . . . . . . . -.3V to +20V Phase Detector Output Current . . . . . . . . . . . . . . . . . . . ±10mA Lock Indicator Output Current . . . . . . . . . . . . . . . . . . . . +15mA Lock Indicator Output Voltage . . . . . . . . . . . . . . . . . . . . . . +20V Divide Select Input Voltages . . . . . . . . . . . . . . . . . -.3V to +10V Double Edge Disable Input Voltage . . . . . . . . . . . . -.3V to +10V Oscillator Input Voltage . . . . . . . . . . . . . . . . . . . . . . -.3V to +5V Sense Amplifier Input Voltage . . . . . . . . . . . . . . . . .3V to +20V Power Dissipation at TA = 25°C (Note 2 . . . . . . . . . . . 1000mW Power dissipation at TC = 25°C (Note 2) . . . . . . . . . . . 2000mW Operating Junction Temperature . . . . . . . . . . . -55°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C Note1: Voltages are referenced to ground, (Pin 16). Currents are positive into, negative out of, the specified terminals. Note 2: Consult Packaging Section of Databook for thermal limitations and considerations of package. CONNECTION DIAGRAMS PLCC-20 (TOP VIEW) Q Package DIL-16 (TOP VIEW) J or N Package PACKAGE PIN FUNCTION FUNCTION PIN N/C Div 4/5 Input Div 2/4/8 Input Lock Indicator Output Phase Detector Output N/C Dbl Edge Disable Input Sense Amp Input 5V Ref Output Loop Amp Inv Input N/C Loop Amp Output Aux Amp Non-Inv Input Aux Amp Inv Input Aux Amp Output N/C +VIN OSC Output OSC Input Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA = 0°C to +70°C for the UC3633, -25°C to +85°C for the UC2633, -55°C to +125°C for the UC1633, +VIN = 12V; TA=TJ.) PARAMETER Supply Current TEST CONDITIONS MIN. +VIN = 15V TYP. MAX. UNITS 20 28 mA 5.0 5.25 V 5.0 20 mV 2.0 20 Reference Output Voltage (VREF) 4.75 Load Regulation IOUT = 0V to 7mA Line Regulation +VIN = 8V to 15V Short Circuit Current VOUT = 0V 12 30 mV mA Oscillator DC Voltage Gain Oscillator Input to Oscillator Output 12 16 20 dB Input DC Level (VIB) 1.15 1.3 1.45 V Input Impedance (Note 3) Oscillator Input Pin Open, TJ = 25°C VIN = VIB ±0.5V, TJ = 25°C 1.3 1.6 1.9 kΩ Output DC Level Oscillator Input Pin Open, TJ = 25°C 1.2 1.4 1.6 V Maximum Operating Frequency 10 MHz Dividers Maximum Input Frequency Input = 1VPP at Oscillator Input Div. 4/5 Input Current Input = 5V (Div. by 4) Input = 0V (Div. by 5) Div. 4/5 Threshold Note 3: These impedence levels will vary with TJ at about 1700ppm/°C Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 10 MHz 150 500 µA -5.0 0.0 5.0 µA 0.5 1.6 2.2 V UC1633 UC2633 UC3633 (Unless otherwise stated, these specifications apply for TA = 0°C to +70°C for the UC3633, ELECTRICAL CHARACTERISTICS (cont.): -25°C to +85°C for the UC2633, -55°C to +125°C for the UC1633, +VIN = 12V; TA=TJ.) PARAMETER TEST CONDITIONS MIN. TYP. -500 -150 1.5 2.5 0.20 0.8 MAX. UNITS Dividers (cont.) Div. 2/4/8 Input Current Input = 5V (Div. by 8) Input = 0V (Div. by 2) Div. 2/4/8 Open Circuit Voltage Input Current = 0µA (Div. by 4) Div. by 2 Threshold Div. by 4 Threshold Div. by 8 Threshold 150 1.5 Volts Below VREF 500 µA µA 3.5 V V 3.5 V 0.20 0.8 V 27 30 10 mV -1.0 -0.2 µA Sense Amplifier Threshold Voltage Percent of VREF Threshold Hysteresis Input Bias Current Input = 1.5V 33 % Double Edge Disable Input Input Current 150 500 µA -5.0 0.0 5.0 µA 0.5 1.6 2.2 v Input = 5V (Disabled) Input = 0V (Enabled) Threshold Voltage Phase Detector High Output Level Positive Phase/Freq. Error, Volts Below VREF 0.2 0.5 V Low Output Level Negative Phase/Freq. Error 0.2 0.5 V Mid Output Level Zero Phase/Freq. Error, Percent of VREF 47 50 53 High Level Maximum Source Current VOUT = 4.3V 2.0 8.0 mA Low Level Maximum Sink Current VOUT = 0.7V 2.0 5.0 mA Mid Level Output Impedance (Note 3) IOUT = -200 to +200µA, TJ = 25°C 4.5 6.0 7.5 % kΩ Lock Indicator Output Saturation Voltage Freq. Error, IOUT = 5mA 0.3 0.45 V Leakage Current Zero Freq. Error, VOUT = 15V 0.1 1.0 µA 47 50 53 % -0.8 -0.2 µA 60 75 dB +VIN = 8V to 15V 70 100 dB Source, VOUT = 0V 16 35 mA Sink, VOUT = 5V 16 30 mA Loop Amplifier NON INV. Reference Voltage Percent of VREF Input Bias Current Input = 2.5V AVOL PSRR Short Circuit Current Auxiliary Op-Amp Input Offset Voltage VCM = 2.5V Input Bias Current VCM = 2.5V Input Offset Current VCM = 2.5V 8 -0.8 AVOL µA -0.2 .01 mV 0.1 µA 70 120 dB PSRR +VIN = 8V to 15V 70 100 dB CMRR VCM = 0V to 10V 70 100 dB Source, VOUT = 0V 16 35 mA Sink, VOUT = 5V 16 30 mA Short Circuit Current Note 3: These impedence levels will vary with TJ at about 1700ppm/°C Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 UC1633 UC2633 UC3633 APPLICATION AND OPERATING INFORMATION Determining the Oscillator Frequency The resulting reference frequency appearing at the phase detector inputs is equal to the oscillator frequency divided by the selected divide ratio. If the double edge option is used, (Pin 5 low), the frequency of the sense amplifier input signal is doubled by responding to both the rising and falling edges of the input signal. Using this option, the loop reference frequency can be doubled for a given motor RPM. The frequency at the oscillator is determined by the desired RPM of the motor, the divide ratio selected, the number of poles in the motor, and the state of the double edge select pin. fOSC(Hz) = (Divide Ratio) • (Motor RPM) • (1/60 SEC/MIN) • (No. of Rotor Poles/2) • (x 2 if Pin 5 Low) Recommended Oscillator Configuration Using AT Cut Quartz Crystal External Reference Frequency Input Method for Deriving Rotation Feedback Signal from Analog Hall Effect Device *This signal may require filtering if chopped mode drive scheme is used. Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 UC1633 UC2633 UC3633 APPLICATION AND OPERATION INFORMATION Phase Detector Operation The phase detector on these devices is a digital circuit that responds to the rising edges of the detector’s two inputs. The phase detector output has three states: a high, 5V state, a low, 0V state, and a middle, 2.5V state. In the high and low states the output impedance of the detector is low and the middle state output impedence is high, typically 6.0kΩ. When there is any static frequency difference between the inputs, the detector output is fixed at its high level if the +input (the sense amplifier signal) is greater in frequency, and fixed at its low level if the -input (the reference frequency signal) is greater in frequency. 5V/4π radians or about 0.4V/radian. The dynamic range of the detector is ±2π radians. The operation of the phase detector is illustrated in the figures below. The upper figure shows typical voltage waveforms seen at the detector output for leading and lagging phase conditions. The lower figure is a state diagram of the phase detector logic. In this figure, the circles represent the 10 possible states of the logic, and the connecting arrows represent the transition events/paths to and from these states. Transition arrows that have a clockwise rotation are the result of a rising edge on the +input, and conversely, those with counter-clockwise rotation are tied to the rising edge of the -input signal. When the frequencies of the two inputs to the detector are equal, the phase detector switches between its middle state and either the high or low states, depending on the relative phase of the two signals. If the +input is leading in phase then, during each period of the input frequency, the detector output will be high for a time equal to the time difference between the rising edges of the inputs, and will be at its middle level for the remainder of the period. If the phase relationship is reversed, then the detector will go low for a time proportional to the phase difference of the inputs. The resulting gain of the phase detector. kø, is The normal operational states of the logic are 6 and 7 for positive phase error, 1 and 2 for a negative phase error. States 8 and 9 occur during positive frequency error, 3 and 4 during negative frequency error. States 5 and 10 occur only as the inputs cross over from the frequency error to a normal phase error only condition. The level of the phase detector output is determined by the logic state as defined in the state diagram figure. The lock indicator output is high, off, when the detector is in states 1, 2, 6, or 7. Typical Phase Detector Output Waveforms Phase Detector State Diagram Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 UC1633 UC2633 UC3633 APPLICATION AND OPERATION INFORMATION Suggested Loop Filter Configuration s νOUT R3 1 + ⁄ ω z • (s) = R1 1 + s⁄ω p νIN * The static phase error of the loop is easily adjusted by adding resistor, R4, as shown. To lock at zero phase error R4 is determined by: R4 = 2.5V • R3 | ∆ VOUT | ωp = 1 R2C1 ωz = 1 (R1 + R2) C1 Where: |∆VOUT| = |VOUT - 2.5V| and VOUT = DC Operating Voltage At Loop Amplifier Output During Phase Lock If: (VOUT - 2.5) > 0, R4 Goes to 0V (VOUT - 2.5) < 0, R4 Goes to 5.0V Reference Filter Configuration νOUT 1 (s) = s2ζ νIN + 1+ ωN ωN = ζ = s2 ωN2 1 √ R1R2C1C2 1 1 = 2Q 2 √CC 2 1 R1 + R2 √ R1R2 Note: with R1 = R2, ζ = Reference Filter Design Aid - Gain Response Powered by ICminer.com Electronic-Library Service CopyRight 2003 √CC 2 1 Reference Filter Design Aid - Phase Response 6 UC1633 UC2633 UC3633 APPLICATION AND OPERATION INFORMATION Design Example Bode Plots - Design Example Open Loop Response 1.) KLF(s) • KRF(s) N • Kφ • GPD • KT 2.*) s2 • J 3.) Combined Overall Open Loop Response Where: KLF(s) = Loop Filter Response KRF(s) = Reference Filter Response N = 4 (Using Double Edge Sensing With 4 Pole Motor) Kφ = Phase Detector Gain (.4V/RAD) GPD = Power Stage Transductance (1A/V) KT = Motor Torque Constant (.022NM/A) J = Motor Moment of Inertia (.0015NM/A - SEC2) s = 2πjf *Note: For a current mode driver the electrical time constant, LM / RM, of the motor does not enter into the small signal response. If a voltage mode drive scheme is used, then the asymptote, plotted as 2 above, can be approximated by: N • K φ • KPD • KT 2 s • J • RM if: RM > KT √LJ M and, Here: KPD = Voltage gain of Driver Stage RM = Motor Winding Resistance LM = Motor Winding Inductance UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 RM KT 2 <f< 2π • J • RM 2π • LM IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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