ETC UCC35702D

UCC15701/2
UCC25701/2
UCC35701/2
application
INFO
available
Advanced Voltage Mode Pulse Width Modulator
FEATURES
DESCRIPTION
• 700kHz Operation
The UCC35701/UCC35702 family of pulse width modulators is intended for
isolated switching power supplies using primary side control. They can be
used for both off-line applications and DC/DC converter designs such as in
a distributed power system architecture or as a telecom power source.
• Integrated Oscillator/ Voltage Feed
Forward Compensation
• Accurate Duty Cycle Limit
The devices feature low startup current, allowing for efficient off-line starting, yet have sufficient output drive to switch power MOSFETs in excess of
500kHz.
• Accurate Volt-second Clamp
• Optocoupler Interface
Voltage feed forward compensation is operational over a 5:1 input range
and provides fast and accurate response to input voltage changes over a
4:1 range. An accurate volt-second clamp and maximum duty cycle limit
are also featured.
• Fault Counting Shutdown
• Fault Latch off or Automatic Shutdown
• Soft Stop Optimized for Synchronous
Rectification
Fault protection is provided by pulse by pulse current limiting as well as the
ability to latch off after a programmable number of repetitive faults has occurred.
• 1A Peak Gate Drive Output
• 130µA Start-up Current
Two UVLO options are offered. UCC35701 family has turn-on and turn-off
thresholds of 13V/9V and UCC35702 family has thresholds of 9.6V/8.8V.
• 750µA Operating Current
The UCC35701/2 and the UCC25701/2 are offered in the 14 pin SOIC (D),
14 pin PDIP (N) or in 14 pin TSSOP (PW) packages. The UCC15701/2 is
offered in the 14 pin CDIP (J) package.
TYPICAL APPLICATION DIAGRAM
VIN SUPPLY
R1
R6
R2
6
R7
VFF
VDD
3
R3
VREF
7
RT
10
CT
UCC35701
CT
C6 VOUT
C4
C1
R4
R5
9
VSCLAMP
11
SYNC
14
SS
R8
OUT
4
ILIM
2
R10
CS
C2
CF
1
COUNT
12
VREF
RCS
C3
RF
PGND
5
R8
VIN RETURN
RGND
8
FB
GND
13
R11
VOUT
C5
R13
R12
C6
R14
C7
R15
UDG-98005-1
SLUS293A - JANUARY 2000
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UCC15701/2
UCC25701/2
UCC35701/2
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Supply voltage (Supply current limited to 20mA) . . . . . . . . 15V
Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Input pins ( ILIM,VFF,RT,CT,VSCLAMP,SYNC,SS) . . . . . . 6V
Output Current (OUT) DC. . . . . . . . . . . . . . . . . . . . . +/–180mA
Output Current (OUT) Pulse (0.5ms) . . . . . . . . . . . . . . +/–1.2A
Storage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . +300°C
UVLO
Option
13V / 9V
–55°C to +125°C
9.6V / 8.8V
Note: All voltages are with respect to GND. Currents are positive into the specified terminal. Consult Packaging Section of
the Databook for thermal limitations and considerations of
packages.
9.6V / 8.8V
TA = TJ
13V / 9V
–40°C to +85°C
13V / 9V
0°C to +70°C
CONNECTION DIAGRAMS
9.6V / 8.8V
DIL-14, SOIC-14, TSSOP-14 (TOP VIEW)
N or J, D, PW PACKAGE
Package Part Number
CDIP-14
CDIP-14
SOIC-14
PDIP-14
TSSOP-14
SOIC-14
PDIP-14
TSSOP-14
SOIC-14
PDIP-14
TSSOP-14
SOIC-14
PDIP-14
TSSOP-14
UCC15701J
UCC15702J
UCC25701D
UCC25701N
UCC25701PW
UCC25702D
UCC25702N
UCC25702PW
UCC35701D
UCC35701N
UCC35701PW
UCC35702D
UCC35702N
UCC35702PW
The D and PW packages are available taped and reeled. Add
TR suffix to the device type (e.g., UCC35701DTR).
COUNT
1
14
SS
ILIM
2
13
GND
VDD
3
12
VREF
OUT
4
11
SYNC
PGND
5
10
CT
VFF
6
9
VSCLAMP
RT
7
8
FB
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 11V, RT = 60.4k, CT = 330pF, CREF = CVDD =
0.1 F, VFF = 2.0V, and no load on the outputs.
PARAMETER
UVLO Section
Start Threshold
Stop Threshold
Hysteresis
Supply Current
Start-up Current
IDD Active
VDD Clamp Voltage
VDD Clamp – Start Threshold
Voltage Reference
VREF
Line Regulation
Load Regulation
Short Circuit Current
TEST CONDITIONS
(UCCX5701)
(UCCX5702)
(UCCX5701)
(UCCX5702)
(UCCX5701)
(UCCX5702)
(UCCX5701) VDD = 11V, VDD Comparator Off
(UCCX5702) VDD = 8V, VDD Comparator Off
VDD Comparator On
(UCCX5701) IDD = 10mA
(UCCX5702) IDD = 10mA
(UCCX5701)
(UCCX5702)
VDD = 10V to 13V, IVREF = 0mA to 2mA
VDD = 10V to 13V
IVREF = 0mA to 2mA
VREF = 0V, TJ = 25°C
2
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MIN
TYP
12
8.8
8
8.0
3
0.3
13
9.6
9
8.8
4
0.8
14
10.4
10
9.6
V
V
V
V
V
V
130
120
0.75
14.3
13.8
1.3
4.2
200
190
1.5
15
15
µA
A
mA
V
V
V
V
5
20
2
20
5.1
V
mV
mV
mA
13.5
13
4.9
MAX UNITS
50
UCC15701/2
UCC25701/2
UCC35701/2
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 11V, RT = 60.4k, CT = 330pF, CREF = CVDD =
0.1 F, VFF = 2.0V, and no load on the outputs.
PARAMETER
TEST CONDITIONS
Line Sense
Vth High Line Comparator
Vth Low Line Comparator
Input Bias Current
Oscillator Section
Frequency
Frequency
SYNC VIH
SYNC VIL
SYNC Input Current
RT Voltage
CT Peak Voltage
CT Valley Voltage
VFF = 0.8V to 3.2V
VFF = 0.6V to 3.4V (Note 1)
VSYNC = 2.0V
VFF = 0.4V
VFF = 0.8V
VFF = 2.0V
VFF = 3.2V
VFF = 3.6V
VFF = 0.8V (Note 1)
VFF = 3.2V (Note 1)
(Note 1)
Soft Start/Shutdown/Duty Cycle Control Section
ISS Charging Current
ISS Discharging Current
Saturation
VDD = 11V, IC Off
Fault Counter Section
Threshold Voltage
Saturation Voltage
Count Charging Current
VFF = 0.8V to 3.2V
VFF = 0.8V to 3.2V
Current Limit Section
Input Bias Current
Current Limit Threshold
Shutdown Threshold
MIN
TYP
3.9
0.5
–100
4
0.6
4.1
0.7
100
V
V
nA
90
90
2
100
100
110
110
0.8
10
0.7
0.85
2.05
3.25
3.5
kHz
kHz
V
V
µA
V
V
V
V
V
V
V
V
0.5
0.75
1.95
3.15
3.3
3
0.6
0.8
2.0
3.2
3.4
0.8
3.2
0
MAX UNITS
10
300
18
500
25
30
750
100
A
µA
mV
3.8
4
10
18
4.2
100
30
V
mV
µA
–100
180
500
0
200
600
100
220
700
nA
mV
mV
k
%
%
%/V
Pulse Width Modulator Section
FB Pin Input Impedance
Minimum Duty Cycle
Maximum Duty Cycle
PWM Gain
VFB = 3V
VFB <= 1V
VFB >= 4.5V, VSCLAMP >= 2.0V
VFF = 0.8V
30
50
95
35
99
50
100
0
100
70
Volt Second Clamp Section
Maximum Duty Cycle
Minimum Duty Cycle
VFF = 0.8V, VSCLAMP = 0.6V
VFF = 3.2V, VSCLAMP = 0.6V
69
17
74
19
79
21
%
%
Output Section
VOH
VOL
Rise Time
Fall Time
IOUT = –100mA, (VDD – VOUT)
IOUT = 100mA
CLOAD = 1000pF
CLOAD = 1000pF
0.4
0.4
20
20
1
1
100
100
V
V
ns
ns
Note 1: Guaranteed by design. Not 100% tested in production.
3
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UCC15701/2
UCC25701/2
UCC35701/2
DETAILED BLOCK DIAGRAM
2*IRT
11
S
VFF
6
Q
RT
7
CT
10
RD
PEAK
IRT
VDD
4
OUT
5
PGND
0.2V
S
+
VALLEY
8
1.5R
VSCLAMP
3
PWM
0.7V
FB
SYNC
3µA
Q
RD
R
9
4V
HIGH LINE
VREF
I
SS
0.6V
4.5V
14
SSDONE
0.6V
ILIM
2
25*I
CURRENT FAULT
0.2V
CURRENT LIMIT
VREF
0.2V
D
PWM
SSDONE
COUNT
13/9V (35701)
9.6/8.8V (35702)
RUN
LOW LINE
Q
Q
VDD
SD
I
R
R
1
R
Q
FAULT
LATCH
5.0V
REF
12 VREF
SD
4V
13 GND
SHUTDOWN
LATCH
UDG-98004
PIN DESCRIPTIONS
VDD: Power supply pin. A shunt regulator limits supply
voltage to 14V typical at 10mA shunt current.
RT: The voltage on this pin mirrors VFF over a 0.8V to
3.2V range. A resistor to ground sets the ramp capacitor
charge current. The resistor value should be between
20k and 200k.
PGND: Power Ground. Ground return for output driver
and currents.
CT: A capacitor to ground provides the oscillator/
feedforward sawtooth waveform. Charge current is 2 •
IRT, resulting in a CT slope proportional to the input voltage. The ramp voltage range is GND to VRT.
GND: Analog Ground. Ground return for all other circuits.
This pin must be connected directly to PGND on the
board.
OUT: Gate drive output. Output resistance is 10Ω maximum.
Period and oscillator frequency is given by:
VFF: Voltage feedforward pin. This pin connects to the
power supply input voltage through a resistive divider and
provides feedforward compensation over a 0.8V to 3.2V
range. A voltage greater than 4.0V or less than 0.6V on
this pin initiates a soft stop cycle.
4
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T=
VRT • CT
+ t DISCH ≈ 0 .5 • RT • CT
2 • IRT
F≈
2
RT • CT
UCC15701/2
UCC25701/2
UCC35701/2
PIN DESCRIPTIONS (cont.)
while VSS < (0.4 • VFB), the duty cycle, and therefore the
output voltage of the converter is determined by the soft
start circuitry.
VSCLAMP: Voltage at this pin is compared to the CT
voltage, providing a constant volt-second limit. The comparator output terminates the PWM pulse when the ramp
voltage exceeds VSCLAMP. The maximum on time is
given by:
t ON =
At High Line or Low Line fault conditions, the soft start
capacitor is discharged with a controlled discharge current of about 500µA. During the discharge time, the duty
cycle of the converter is gradually decreased to zero.
This soft stop feature allows the synchronous rectifiers to
gradually discharge the output LC filter. An abrupt shut
off can cause the LC filter to oscillate, producing unpredictable output voltage levels.
VVSCLAMP • CT
2 • IRT
The maximum duty cycle limit is given by:
DMAX =
t ON VVSCLAMP
=
T
VRT
All other fault conditions (UVLO, VREF Low, Over Current (0.6V on ILIM) or COUNT) will cause an immediate
stop of the converter. Furthermore, both the Over Current
fault and the COUNT fault will be internally latched until
VDD drops below 9V or VFF goes below the 600mV
threshold at the input of the Low Line comparator.
FB: Input to the PWM comparator. This pin is intended
to be driven with an optocoupler circuit. Input impedance
is 50kΩ. Typical modulation range is 1.6V to 3.6V.
SYNC: Level sensitive oscillator sync input. A high level
forces the gate drive output low and resets the ramp capacitor. On-time starts at the negative edge the pulse.
There is a 3µA pull down current on the pin, allowing it to
be disconnected when not used.
After all fault conditions are cleared and the soft start capacitor is discharged below 200 mV, a soft start cycle will
be initiated to restart the converter.
VREF: 5.0V trimmed reference with 2% variation over
line, load and temperature. Bypass with a minimum of
0.1µF to ground.
ILIM: Provides a pulse by pulse current limit by terminating the PWM pulse when the input is above 200mV. An
input over 600mV initiates a latched soft stop cycle.
SS: Soft Start pin. A capacitor is connected between this
pin and ground to set the start up time of the converter.
After power up (VDD>13V AND VREF>4.5V), or after a
fault condition has been cleared, the soft start capacitor
is charged to VREF by a nominal 18µA internal current
source. While the soft start capacitor is charging, and
COUNT: Capacitor to ground integrates current pulses
generated when ILIM exceeds 200mV. A resistor to
ground sets the discharge time constant. A voltage over
4V will initiate a latched soft stop cycle.
APPLICATION INFORMATION
(Note: Refer to the Typical Application Diagram on the first
page of this datasheet for external component names.) All the
equations given below should be considered as first order approximations with final values determined empirically for a specific application.
The circuit will start at this point. IVDD will increase from
the start up value of 130 A to the run value of 750 A.
The capacitor on SS is charged with a 18 A current.
When the voltage on SS is greater than 0.8V, output
pulses can begin, and supply current will increase to a
level determined by the MOSFET gate charge requirements to IVDD ~ 1mA + QT • fs. When the output is active, the bootstrap winding should be sourcing the supply
current. If VDD falls below the UVLO stop threshold, the
controller will enter a shutdown sequence and turn the
controller off, returning the start sequence to the initial
condition.
Power Sequencing
VDD is normally connected through a high impedance
(R6) to the input line, with an additional path (R7) to a
low voltage bootstrap winding on the power transformer.
VFF is connected through a divider (R1/R2) to the input
line.
For circuit activation, all of the following conditions are required:
VDD Clamp
An internal shunt regulator clamps VDD so the voltage
does not exceed a nominal value of 14V. If the regulator
is active, supply current must be limited to less than
20mA.
1. VFF between 0.6V and 4.0V (operational input voltage
range).
2. VDD has been under the UVLO stop threshold to reset
the shutdown latch.
3. VDD is over the UVLO start threshold.
5
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UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
VFF is intended to operate accurately over a 4:1 range
between 0.8V and 3.2V. Voltages at VFF below 0.6V or
above 4.0V will initiate a soft stop cycle and a chip restart when the under/over voltage condition is removed.
Output Inhibit
During normal operation, OUT is driven high at the start
of a clock period and is driven low by voltages on CT, FB
or VSCLAMP.
Volt-Second Clamp
The following conditions cause the output to be immediately driven low until a clock period starts where none of
the conditions are true:
A constant volt-second clamp is formed by comparing
the timing capacitor ramp voltage to a fixed voltage derived from the reference. Resistors R4 and R5 set the
volt-second limit. For a volt-second product defined as
VIN • tON(max), the required voltage at VSCLAMP is:
1. ILIM > 0.2V
2. FB or SS is less than 0.8V
(
)
 R2 
 • VIN • t ON (max )

 R1 + R 2 
.
RT • CT
Current Limiting
ILIM is monitored by two internal comparators. The current limit comparator threshold is 0.2V. If the current limit
comparator is triggered, OUT is immediately driven low
and held low for the remainder of the clock cycle, providing pulse-by-pulse over-current control for excessive
loads. This comparator also causes CF to be charged for
the remainder of the clock cycle.
The duty cycle limit is then:
VVSCLAMP
, or
VVFF
If repetitive cycles are terminated by the current limit
comparator causing COUNT to rise above 4V, the shutdown latch is set. The COUNT integration delay feature
will be bypassed by the shutdown comparator which has
a 0.6V threshold. The shutdown comparator immediately
sets the shutdown latch. RF in parallel with CF resets the
COUNT integrator following transient faults. RF must be
greater than (4 • R4) • (1 – DMAX).
VVSCLAMP
.
 R2 

VIN • 
 R1 + R 2 
The maximum duty cycle is realized when the
feedforward voltage is set at the low end of the operating
range (VFF = 0.8V).
The absolute maximum duty cycle is:
DMAX =
VVSCLAMP VREF
R5
=
•
0 .8
0 .8 R 4 + R 5
Frequency Set
Latched Shutdown
The frequency is set by a resistor from RT to ground and
a capacitor from CT to ground. The frequency is approxi2
mately: F =
(RT • CT )
If ILIM rises above 0.6V, or COUNT rises to 4V, the shutdown latch will be set. This will force OUT low, discharge
SS and COUNT, and reduce IDD to approximately 750 A.
When, and if, VDD falls below the UVLO stop threshold,
the shutdown latch will reset and IDD will fall to 130 A,
allowing the circuit to restart. If VDD remains above the
UVLO stop threshold (within the UVLO band), an alternate restart will occur if VFF is momentarily reduced below 1V. External shutdown commands from any source
may be added into either the COUNT or ILIM pins.
External synchronization is via the SYNC pin. The pin
has a 1.5V threshold , making it compatible with 5V and
3.3V CMOS logic. The input is level sensitive, with a high
input forcing the oscillator ramp low and the output low.
An active pull down on the SYNC pin allows it to be unconnected when not used.
Voltage Feedforward
Gate Drive Output
The voltage slope on CT is proportional to line voltage
over a 4:1 range and equals 2•VFF/(RT•CT). The capacitor charging current is set by the voltage across RT.
V(RT) tracks VFF over a range of 0.8V to 3.2V. A changing line voltage will immediately change the slope of
V(CT), changing the pulse width in a proportional manner without using the feedback loop, providing excellent
dynamic line regulation.
The UCC35701/2 is capable of a 1A peak output current.
Bypass with at least 0.1 F directly to PGND. The capacitor must have a low equivalent series resistance and inductance. The connection from OUT to the power
MOSFET gate should have a 2 or greater damping resistor and the distance between chip and MOSFET
should be minimized. A low impedance path must be established between the MOSFET source (or ground side
of the current sense resistor), the VDD capacitor and
PGND. PGND should then be connected by a single path
(shown as RGND) to GND.
6
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UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
UCC35701/2 is pin to pin compatible to UCC3570 but is
not a direct drop-in replacement for UCC3570 sockets.
The changes required to the power supply printed circuit
board of for existing UCC3570 designs are minimal. For
conversion, only one extra resistor to set the volt-second
clamp needs to be added to the existing PC board layouts. In addition, some component values will need to be
changed due to the functionality change in of four of the
IC pins.
Transitioning From UCC3570 To UCC35701
The UCC35701/2 is an advanced version of the popular,
low power UCC3570 PWM. Significant improvements
were made to the IC’s oscillator and PWM control sections to enhance overall system performance. All of the
key attributes and functional blocks of the UCC3570 were
maintained in the UCC35701/2. A typical application using UCC3570 and UCC35701/2 is shown in Fig. 6 for
comparison.
The Pinout Changes from UCC3570 are as follows.
The advantages of the UCC35701/2 over the UCC3570
are as follows.
• Pin 7 was changed from SLOPE to RT (for timing
resistor)
• Improved oscillator and PWM control section.
• Pin 8 was changed from ISET to VSCLAMP (requiring
one additional resistor from pin 9 to VREF)
• A precise maximum volt-second clamp circuit. The
UCC3570 has a dual time base between oscillator and
feedforward circuitry. The integated time base in
UCC35701/2 improves the duty cycle clamp accuracy,
providing better than ± 5% accurate volt- second
clamp over full temperature range.
• Pin 10 was changed from RAMP to CT (single timing
capacitor)
• Pin 11 was changed from FREQ to SYNC (input only)
• Separately programmable oscillator timing resistor
(RT) and capacitor (CT) circuits provide a higher
degree of versatility.
Additional Information
• An independent SYNC input pin for simple external
synchronization.
[1] Application Note U-150, Applying the UCC3570 Voltage-Mode PWM Controller to Both Off-line and DC/DC
Converter Designs by Robert A. Mammano
Please refer to the following two Unitrode application
topics on UCC3570 for additional information.
• A smaller value filter capacitor (0.1 F) can be used
with the enhanced reference voltage.
[2] Design Note DN-62, Switching Power Supply Topology, Voltage Mode vs. Current Mode by Robert
Mammano
TYPICAL WAVEFORMS
FEEDBK
VSCLAMP
CT
SOFTST
SOFT START
HIGH DC
LOW DC
ZERO DC
SOFT STOP
V-S CLAMP
Figure 1. Timing diagram for PWM action with forward, soft start and volt-second clamp.
7
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UDG-98207
UCC15701/2
UCC25701/2
UCC35701/2
TYPICAL WAVEFORMS (cont.)
VFF
CT
SYNC
UDG-98208
Figure 2. Timing diagram for oscillator waveforms showing feedforward action and synchronization.
TYPICAL CHARACTERISTIC CURVES
1.03
1000
100
NORMALIZED DUTY CYCLE
FREQUENCY [kHz]
VFF=3.2
100pF
150pF
220pF
330pF
470pF
10
1.02
1.01
VFF=0.8
1.00
0.99
0.98
0.97
20
60
100
140
RT [KΩ]
180
220
-55
-15
5
25
45
65
85
105
TEMPERATURE [°C]
Figure 3. Oscillator frequency vs. RT and CT.
Figure 5. Normalized maximum duty cycle vs.
temperature.
Figure 4. Oscillator frequency vs. temperature.
8
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-35
125
UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
VIN+
R1
R5
UCC3570
R2
6
VFF
7
SLOPE
10
RAMP
9
ISET
11
FREQ
R6
VDD
3
VOUT
R3
C4
C1
CR
R8
OUT
4
R4
R9
ILIM
2
CT
RT
C2
RSNS
CSS
14 SS
5
PGND
CF
1
RF
COUNT
RGND
C3
12
VREF
8
FB
R7
13
GND
R11
VOUT
C5
R13
C6
R12
R14
C7
R15
VIN+
UCC35701
R1
R5
R2
R6
6
VFF
VDD
3
VOUT
R3
7
C4
RT
C1
CT
R8
10 CT
OUT
4
ILIM
2
R4
R9
9
VSCLAMP
C2
RNEW
11 SYNC
RSNS
CSS
14 SS
PGND
5
CF
1
RF
COUNT
RGND
C3
12 VREF
R7
GND 13
8
FB
R11
VOUT
C5
R13
R12
C6
R14
C7
R15
UDG-98210
Figure 6. Single-ended forward circuit comparison between UCC3750 and UCC37501.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
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9
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated
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