DATA SHEET MOS INTEGRATED CIRCUIT µPD78P083(A) 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78P083(A) is a member of the µ PD78083 Subseries of the 78K/0 Series products. Comparing with the µPD78P083 (standard), more strict quality assurance programs are applied to this product (called Special of the quality grade in NEC). The µ PD78P083(A) uses one-time PROM instead of internal ROMs of the µ PD78081(A) and µPD78082(A). Because this device can be programmed by users, it is ideally suited for applications involving the evaluation of systems in development stages, small-scale production of many different products, and rapid development and timeto-market of a new product. The details of functions are described in the user’s manuals. Be sure to read the following manuals before designing. µPD78083 Subseries User's Manual : U12176E 78K/0 Series User's Manual — Instructions : IEU-1372 FEATURES • Pin-compatible with mask ROM version (except VPP pin) • Internal PROM: 24 Kbytes Note • µPD78P083CU(A), µPD78P083GB(A): One-time programmable (ideally suited for small-scale production) • Internal high-speed RAM: 512 bytes Note • Can be operated in the same supply voltage as the mask ROM version (VDD = 1.8 to 5.5 V) • Corresponding to QTOPTM Microcontrollers (under planning) Note The internal PROM and internal high-speed RAM capacities can be changed by setting the internal memory size switching register (IMS). Remarks 1. QTOP microcontroller is a general term for microcontrollers which incorporate one-time PROM and are totally supported by NEC's programming service (from programming to marking, screening and verification). 2. For the differences between PROM and Mask ROM versions, refer to Chapter 1. DIFFERENCES BETWEEN THE µ PD78P083(A) AND MASK ROM VERSIONS. The information in this document is subject to change without notice. Document No. U12175EJ1V0DS00 (1st edition) Date Published March 1997 N Printed in Japan © © 1997 1996 µPD78P083(A) ORDERING INFORMATION Part Number Package Internal ROM 42-pin plastic shrink DIP (600 mil) One-Time PROM µ PD78P083GB(A)-3B4 44-pin plastic QFP (10 × 10 mm) One-Time PROM µ PD78P083GB(A)-3BS-MTXNote 44-pin plastic QFP (10 × 10 mm) One-Time PROM µ PD78P083CU(A) Note Under planning Caution µPD78P083GB(A) has two types of packages. (Refer to Chapter 7. PACKAGE DRAWINGS). Consult an NEC’s sales representative for suppliable packages. QUALITY GRADE Part Number Package Quality Grades µ PD78P083CU(A) 42-pin plastic shrink DIP (600 mil) Special µ PD78P083GB(A)-3B4 44-pin plastic QFP (10 × 10 mm) Special µ PD78P083GB(A)-3BS-MTXNote 44-pin plastic QFP (10 × 10 mm) Special Note Under planning Please refer to “Quality grades on NEC Semiconductor Devices” (Document number C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Deferences between µ PD78P083(A) and µPD78P083 µ PD78P083(A) Product µPD78P083 Item 2 Quality Grade Special Standard Package 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (10 × 10 mm) 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (10 × 10 mm) 42-pin ceramic shrink DIP (with window) (600 mil) µPD78P083(A) 78K/0 SERIES DEVELOPMENT The following shows the 78K/0 Series products development. Subseries names are shown inside frames. Mass-produced products Products under development Y Subseries supports the I2C bus specifications. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin µPD78075B µPD78078 µPD78070A µPD780018Note µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 µPD78075BY µPD78078Y µPD78070AY µPD780018YNote µPD780058YNote µPD78058FY µPD78054Y µPD780034Y µPD780024Y µPD78018FY µPD78014Y µPD78002Y Low EMI noise version of the µPD78078 Timer is added to the µPD78054 and its external interface is enhanced. ROM-less versions of the µPD78078 Serial I/O of the µPD78078 is enhanced and only selected functions are provided. Serial I/O-enhanced versions of the µPD78054; Low EMI noise version Low EMI noise version of the µPD78054 UART and D/A converter are added to the µPD78014 and I/O is enhanced. A/D-enhanced version of the µPD780024 Serial I/O-enhanced versions of the µPD78018F; Low EMI noise version Low EMI noise version of the µPD78018F Low-voltage (1.8 V) operation versions of the µPD78014 with several ROM and RAM capacities available. A/D converter and 16-bit timer are added to the µPD78002. A/D converter is added to the µPD78002. Basic subseries for control applications On-chip UART, and operable at low voltage (1.8 V). Inverter control 64-pin 64-pin A/D-enhanced version of the µPD780924 On-chip inverter control circuit and UART incorporated; Low EMI noise version µPD780964 µPD780924 FIP driving 78K/0 series 100-pin 100-pin 80-pin 80-pin µPD780208 µPD780228 µPD78044H µPD78044F I/O and FIP C/D of the µPD78044F are enhanced. Total display outputs : 53 pins I/O and FIP C/D of the µPD78044H are enhanced. Total display outputs : 48 pins N-ch open-drain I/O is added to the µPD78044F. Total display outputs : 34 pins Basic subseries for FIP driving. Total display outputs: 34 pins LCD driving 100-pin 100-pin 100-pin µPD780308 µPD78064B µPD78064 TM IEBus 80-pin µPD780308Y µPD78064Y SIO of the µPD78064 is enhanced, and ROM and RAM are expanded. Low EMI noise version of the µPD78064 Basic subseries for driving LCDs and with on-chip UART. supported µPD78098 IEBus controller is added to the µPD78054. LV 64-pin µPD78P0914 PWM output, LV digital code decoder and Hsync counter are incorporated. Note Under planning 3 µPD78P083(A) The following table shows the differences among subseries functions. Function ROM Timer 8-bit 10-bit 8-bit VDD MIN. External Serial interface Subseries name Control capacity 8-bit 16-bit Watch WDT A/D µ PD78075B 32K to 40K 4 ch 1 ch 1 ch 1 ch 8 ch µ PD78078 A/D — D/A value expansion 2 ch 3 ch (UART: 1 ch) 88 1.8 V Available 61 2.7 V 48K to 60K µ PD78070A — µ PD780018 48K to 60K µ PD780058 24K to 60K 2 ch µ PD78058F 48K to 60K µ PD78054 16K to 60K µ PD780034 8K to 32K — 2 ch 3 ch (Time division 68 UART: 1 ch) 1.8 V 3 ch (UART: 1 ch) 69 2.7 V — 8 ch 8 ch — — µ PD78014H 3 ch (UART: 1 ch, Time 51 division 3-wire: 1 ch) 2 ch µ PD78018F 8K to 60K µ PD78014 8K to 32K µ PD780001 8K µ PD78002 8K to 16K 1 ch — µ PD78083 — — 8 ch µ PD780964 8K to 32K — 3 ch Note — µ PD780924 8 ch — FIP driving µ PD780208 32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch — 48K to 60K 3 ch — — 1 ch 8 ch 1 ch 16K to 40K µ PD780308 48K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch — 53 Available — — 2 ch (UART: 2 ch) 47 2.7 V Available — 2 ch 74 2.7 V — 1 ch 72 4.5 V 68 2.7 V 3 ch (Time division 57 UART: 1 ch) 2.0 V — 2.7 V Available 4.5 V Available 2 ch — — µ PD78064B 32K 4 39 1.8 V — µ PD78044F 2 ch (UART: 1 ch) µ PD78064 16K to 32K IEBus supported µ PD78098 32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch LV µ PD78P0914 32K Note 10 bits timer: 1 channel 53 1 ch (UART: 1 ch) 33 µ PD78044H 32K to 48K 2 ch 1 ch 1 ch LCD driving 1.8 V 2.7 V — µ PD780228 2 ch (Time division 88 3-wire: 1 ch) 2.0 V µ PD780024 Inverter control I/O 6 ch — — 1 ch 8 ch — — 2 ch 3 ch (UART: 1 ch) 69 — 2 ch 54 µPD78P083(A) FUNCTION DESCRIPTION Item Function Internal memory • PROM: 24 Kbytes Note • RAM High-speed RAM: 512 bytes Note Memory space 64 Kbytes General register 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Instruction cycles Instruction execution time variable function is integrated. 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0-MHz operation with main system clock) Instruction set • 16-bit operation • Multiply/divide (8 bits x 8 bits, 16 bits ÷ 8 bits) • Bit manipulation (set, reset, test, Boolean operation) • BCD adjust, etc. I/O ports Total : 33 • CMOS input : 1 • CMOS input/output : 32 A/D converter • 8-bit resolution x 8 channels Serial interface • 3-wired serial I/O/UART mode selectable: 1 channel Timer • 8-bit timer/event counter: 2 channels • Watchdog timer: 1 channel Timer output 2 pins (8-bit PWM output enable) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and 5.0 MHz (@ 5.0-MHz operation with main system clock) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz (@ 5.0-MHz operation with main system clock) Vectored-interrupt source Maskable Internal : 8 Non-maskable Internal : 1 Software Internal : 1 Power supply voltage external : 3 VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85°C Packages • 42-pin plastic shrink DIP (600 mil) • 44-pin plastic QFP (10 × 10 mm) Note Internal PROM and high-speed RAM capacities can be changed by setting the memory size switching register (IMS). 5 µPD78P083(A) PIN CONFIGURATIONS (Top View) (1) Normal operating mode • 42-pin plastic shrink DIP (600 mil) µ PD78P083CU(A) P55 1 42 VSS P56 2 41 P54 P57 3 40 P53 P30 4 39 P52 P31 5 38 P51 P32 6 37 P50 P33 7 36 P100/TI5/TO5 P34 8 35 P101/TI6/TO6 P35/PCL 9 34 P70/RXD/SI2 P36/BUZ 10 33 P71/TXD/SO2 P37 11 32 P72/ASCK/SCK2 P00 12 31 P17/ANI7 P01/INTP1 13 30 P16/ANI6 P02/INTP2 14 29 P15/ANI5 P03/INTP3 15 28 P14/ANI4 RESET 16 27 P13/ANI3 VPP 17 26 P12/ANI2 X2 18 25 P11/ANI1 X1 19 24 P10/ANI0 VDD 20 23 AVSS AVDD 21 22 AVREF Cautions 1. Connect V PP pin directly to V SS. 2. Connect AVDD pin to VDD. 3. Connect AVSS pin to VSS . 6 µPD78P083(A) • 44-pin plastic QFP (10 x 10 mm) µPD78P083GB(A)-3B4, µPD78P083GB(A)-3BS-MTX Note NC RESET VPP X2 X1 VDD AVDD AVREF AVSS P10/ANI0 P11/ANI1 Note Under planning P12/ANI2 1 44 43 42 41 40 39 38 37 36 35 34 33 P03/INTP3 P13/ANI3 2 32 P02/INTP2 P14/ANI4 3 31 P01/INTP1 P15/ANI5 4 30 P00 P16/ANI6 5 29 P37 P33 P101/TI6/TO6 10 24 P32 P100/TI5/TO5 11 23 12 13 14 15 16 17 18 19 20 21 22 NC P31 P30 P70/RXD/SI2 P57 P34 25 P56 26 9 P55 8 VSS P71/TXD/SO2 P54 P35/PCL P53 P36/BUZ 27 P52 28 7 P51 6 P50 P17/ANI7 P72/ASCK/SCK2 Cautions 1. Connect V PP pin directly to VSS . 2. Connect AVDD pin to VDD. 3. Connect AVSS pin to VSS. 4. Connect NC pin to V SS for noise protection (It can be left open). 7 µPD78P083(A) ANI0 to ANI7 : Analog Input PCL : Programmable Clock ASCK : Asynchronous Serial Clock RESET : Reset AV DD : Analog Power Supply RXD : Receive Data AV REF : Analog Reference Voltage SCK2 : Serial Clock AV SS : Analog Ground SI2 : Serial Input BUZ : Buzzer Clock SO2 : Serial Output INTP1 to INTP3 : Interrupt from Peripherals TI5, TI6 : Timer Input NC : Non-connection TO5, TO6 : Timer Output P00 to P03 : Port 0 TXD : Transmit Data P10 to P17 : Port 1 VDD : Power Supply P30 to P37 : Port 3 VPP : Programming Power Supply P50 to P57 : Port 5 VSS : Ground P70 to P72 : Port 7 X1, X2 : Crystal (Main System Clock) P100, P101 : Port 10 8 µPD78P083(A) (2) PROM programming mode • 42-pin plastic shrink DIP (600 mil) µPD78P083CU(A) Cautions 1. (L): A5 1 42 VSS A6 2 41 A4 A7 3 40 A3 OE 4 39 A2 CE 5 38 A1 PGM 6 37 A0 A8 7 36 A10 (L) 8 35 A11 9 34 A12 10 33 A13 11 32 A14 A9 12 31 D7 (L) 13 30 D6 14 29 D5 15 28 D4 RESET 16 27 D3 VPP 17 26 D2 Open 18 25 D1 (L) 19 24 D0 VDD 20 23 VSS VDD 21 22 VSS Individually connect to VSS via a pull-down resistor. 2. VSS: Connect to GND. 3. RESET: Set to low level. 4. Open: Leave open. 9 µPD78P083(A) • 44-pin plastic QFP (10 x 10 mm) µPD78P083GB(A)-3B4, µPD78P083GB(A)-3BS-MTXNote RESET (L) VPP Open VDD (L) VDD VSS VSS D0 D1 Note Under planning A9 D6 5 29 D7 6 28 A14 7 27 A13 8 26 A12 9 25 A8 A11 10 24 PGM A10 11 23 12 13 14 15 16 17 18 19 20 21 22 Cautions 1. (L): (L) (L) (L) CE OE 30 A7 31 4 A6 3 D5 A5 D4 VSS 32 A4 2 A3 D3 A2 44 43 42 41 40 39 38 37 36 35 34 33 A1 1 A0 D2 Individually connect to VSS via a pull-down resistor. 2. V SS: Connect to GND. 3. RESET: Set to low level. 4. Open: Leave open. A0 to A14 : Address Bus RESET : Reset CE : Chip Enable VDD : Power Supply D0 to D7 : Data Bus VPP : Programming Power Supply OE : Output Enable VSS : Ground PGM : Program 10 µPD78P083(A) BLOCK DIAGRAM P00 P100/TI5/TO5 8-bit TIMER/ EVENT COUNTER 5 PORT 0 P101/TI6/TO6 8-bit TIMER/ EVENT COUNTER 6 PORT 1 P10-P17 PORT 3 P30-P37 SERIAL INTERFACE 2 PORT 5 P50-P57 A/D CONVERTER PORT 7 P70-P72 PORT 10 P100, P101 WATCHDOG TIMER SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP1/P01INTP3/P03 BUZ/P36 INTERRUPT CONTROL 78K/0 CPU CORE PROM (24 KBytes) DATA MEMORY (512 Bytes) BUZZER OUTPUT RESET SYSTEM CONTROL PCL/P35 CLOCK OUTPUT CONTROL P01-P03 VDD VSS VPP X1 X2 11 µPD78P083(A) CONTENTS 1. DIFFERENCES BETWEEN THE µPD78P083(A) AND MASK ROM VERSIONS ....................... 13 2. PIN FUNCTIONS ............................................................................................................................. 14 2.1 Pins in Normal Operating Mode ............................................................................................................ 14 2.2 Pins in PROM Programming Mode ....................................................................................................... 16 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins .................................. 16 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ........................................................ 18 4. PROM PROGRAMMING ................................................................................................................. 19 4.1 Operating Modes ..................................................................................................................................... 19 4.2 PROM Write Procedure .......................................................................................................................... 21 4.3 PROM Read Procedure .......................................................................................................................... 25 5. ONE-TIME PROM VERSION SCREENING ................................................................................... 26 6. ELECTRICAL SPECIFICATIONS ................................................................................................... 27 7. PACKAGE DRAWINGS .................................................................................................................. 45 8. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 48 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 49 APPENDIX B. RELATED DOCUMENTS ........................................................................................... 51 12 µPD78P083(A) 1. DIFFERENCES BETWEEN THE µPD78P083(A) AND MASK ROM VERSIONS The µ PD78P083(A) is a single-chip microcontroller with an on-chip one-time PROM. Setting the memory size switching register (IMS) makes the functions except the PROM specification identical to the mask ROM versions. Table 1-1 shows differences between the PROM version (µPD78P083(A)) and mask ROM versions (µ PD78081(A) and µ PD78082(A)). Table 1-1. Differences between the µPD78P083(A) and Mask ROM Versions µPD78P083(A) Parameter Mask ROM Versions Internal ROM type One-time PROM/EPROM Mask ROM Internal ROM capacity 24 Kbytes µPD78081(A) µPD78082(A) : 16 Kbytes Internal high-speed RAM capacity 512 bytes µPD78081(A) : 256 bytes µPD78082(A) : 384 bytes Internal ROM and internal high-speed Enable Note : 8 Kbytes Disable RAM capacity change by memory size switching register (IMS) IC pin No Yes VPP pin Yes No Electrical specifications Refer to a data sheet of each product Note The internal PROM becomes 24 Kbytes and the internal high-speed RAM becomes 512 bytes by the RESET input. 13 µPD78P083(A) 2. PIN FUNCTIONS 2.1 Pins in Normal Operating Mode (1) Port pins Pin Name Input/Output Function After Reset P00 Input Port 0 Input only Input P01 Input/output 4-bit input/output port Input/output is specifiable Input Alternate Function — INTP1 P02 bit-wise. When used as the INTP2 P03 input port, it is possible to INTP3 connect a pull-up resistor by software. P10 to P17 Input/output Port 1 Input ANI0 to ANI7 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. P30-P34 Input/output Note Port 3 Input — P35 8-bit input/output port PCL P36 Input/output is specifiable bit-wise. BUZ P37 When used as the input port, it is possible to connect — a pull-up resistor by software. P50 to P57 Input/output Port 5 Input — 8-bit input/output port Can drive up to seven LEDs directly. Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. P70 Input/output P71 P72 Port 7 Input SI2/RxD 3-bit input/output port SO2/TxD Input/output is specifiable bit-wise. SCK2/ASCK When used as the input port, it is possible to connect a pull-up resistor by software. P100 P101 Input/output Port 10 2-bit input/output port Input TI5/TO5 TI6/TO6 Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. Note When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the input mode. The on-chip pull-up resistor is automatically disabled. 14 µPD78P083(A) (2) Non-port pins Pin Name INTP1 Input/Output Input Function External interrupt input by which the active edge (rising edge, INTP2 After Reset Input P01 falling edge, or both rising and falling edges) can be specified. P02 INTP3 SI2 Alternate Function P03 Input Serial interface serial data input. Input P70/RxD SO2 Output Serial interface serial data output. Input P71/TxD SCK2 Input/Output Serial interface serial clock input/output. Input P72/ASCK RxD Input Asynchronous serial interface serial data input. Input P70/SI2 TxD Output Asynchronous serial interface serial data output. Input P71/SO2 ASCK Input Asynchronous serial interface serial clock input. Input P72/SCK2 TI5 Input External count clock input to 8-bit timer (TM5). Input P100/TO5 P100/TI5 TI6 TO5 External count clock input to 8-bit timer (TM6). P101/TO6 Output 8-bit timer output. Input Output Clock output. (for main system clock trimming) Input TO6 PCL P101/TI6 P35 BUZ Output Buzzer output. Input P36 ANI0 to ANI7 Input A/D converter analog input. Input P10 to P17 AVREF Input A/D converter reference voltage input. – – AVDD – A/D converter analog power supply. Connected to VDD. – – AVSS – A/D converter ground potential. Connected to VSS . – – System reset input. – – RESET Input X1 Input Main system clock oscillation crystal connection. X2 – VDD – VPP – – – – – Positive power supply. – – High-voltage applied during program write/verification. – – Connected directly to VSS in normal operating mode. VSS – Ground potential. – – NC – Does not internally connected. Connect to VSS . – – (It can be left open) 15 µPD78P083(A) 2.2 Pins in PROM Programming Mode Pin Name Input/Output Function RESET Input PROM programming mode setting When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, this chip is set in the PROM programming mode. VPP Input PROM programming mode setting and high-voltage applied during program write/verification. A0 to A14 Input Address bus D0-D7 Input/output Data bus CE Input PROM enable input/program pulse input OE Input Read strobe input to PROM PGM Input Program/program inhibit input in PROM programming mode. VDD — Positive power supply VSS — Ground potential 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins Types of input/output circuits of the pins and recommeded connection of unused pins are shown in Table 2-1. For the configuration of each type of input/output circuit, see Figure 2-1. Table 2-1. Type of Input/Output Circuit of Each Pin Pin Name Input/Output Input/Output Recommended Connection for Unused Pins Circuit Type P00 2 Input Connect to VSS . P01/INTP1 8-A Input/Output Independently connect to VSS via a resistor. P10/ANI0 to P17/ANI7 11 Input/Output Independently connect to VDD or VSS via P30 to P32 5-A P33, P34 8-A P35/PCL 5-A P02/INTP2 P03/INTP3 a resistor. P36/BUZ P37 P50 to P57 5-A P70/SI2/RxD 8-A P71/SO2/TxD 5-A P72/SCK2/ASCK 8-A P100/TI5/TO5 8-A P101/TI6/TO6 RESET AVREF 16 2 Input – – – Connect to VSS . AVDD Connect to VDD. AVSS Connect to VSS . VPP Connect directly to VSS . NC Connect to VSS (can leave open) µPD78P083(A) Figure 2-1. Types of Pin Input/Output Circuits Type 2 Type 8-A VDD pull-up enable P-ch IN VDD data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics VDD Type 5-A pull-up enable output disable N-ch VDD Type 11 pull-up enable P-ch P-ch VDD VDD data data IN/OUT P-ch IN/OUT output disable input enable P-ch output disable N-ch P-ch N-ch Comparator + – N-ch VREF (threshold voltage) input enable 17 µPD78P083(A) 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) This is a register to disable use of part of internal memories by software. By setting this memory size switching register (IMS), it is possible to get the same memory mapping as that of the mask ROM versions with a different internal memory (ROM, RAM). IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to 46H. Figure 3-1. Internal Memory Size Switching Register Format Symbol IMS 7 6 5 4 3 2 1 0 Address After Reset R/W RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 FFF0H 46H R/W ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity 0 0 1 0 8 Kbytes 0 1 0 0 16 Kbytes 0 1 1 0 24 Kbytes Other than above RAM2 RAM1 RAM0 Setting prohibited Selection of Internal High-Speed RAM Capacity 0 1 0 512 bytes 0 1 1 384 bytes 1 0 0 256 bytes Other than above Setting prohibited Table 3-1 shows the setting values of IMS which make the memory mapping the same as that of the mask ROM version. Table 3-1. Internal Memory Size Switching Register Setting Values Target Mask ROM Versions 18 IMS Setting Value µPD78081(A) 82H µPD78082(A) 64H µPD78P083(A) 4. PROM PROGRAMMING The µPD78P083(A) has an internal 24-Kbyte PROM as a program memory. For programming, set the PROM programming mode with the VPP and RESET pins. For the connection of unused pins, refer to “PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode.” Caution Programs must be written in addresses 0000H to 5FFFH (The last address 5FFFH must be specified). They cannot be written by a PROM programmer which cannot specify the write address. 4.1 Operating Modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 4-1 when the CE, OE, and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM. Table 4-1. Operating Modes of PROM Programming Pin RESET VPP VDD CE OE PGM D0 to D7 L +12.5 V +6.5 V H L H Data input H H L High-impedance Operating Mode Page data latch Page write Byte write L H L Data input Program verify L L H Data output High-impedance Program inhibit Read +5 V +5 V x H H x L L L L H Data output Output disable L H x High-impedance Standby H x x High-impedance x : L or H 19 µPD78P083(A) (1) Read mode Read mode is set if CE = L, OE = L is set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, if OE = H is set. Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µPD78P083(A)s are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data outputs become high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode. In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can be performed, if CE = L, OE = L are set. If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations should be executed repeatedly. (6) Byte write mode Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Then, program verification can be performed if OE = L is set. If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations should be executed repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if a write operation is performed correctly after the write. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin, and D0-D7 pins of multiple µPD78P083(A)s are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device which has the PGM pin driven high. 20 µPD78P083(A) 4.2 PROM Write Procedure Figure 4-1. Page Program Mode Flow Chart Start Address = G VDD = +6.5 V, VPP = +12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X=X+1 X = 10 ? 0.1-ms program pulse Verify 4 bytes Yes Fail Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass Write end Defective product G = Start address N = Program last address 21 µPD78P083(A) Figure 4-2. Page Program Mode Timing Page Data Latch Page Program Program Verify A2-A14 A0, A1 D0-D7 Data Input VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL 22 Data Output µPD78P083(A) Figure 4-3. Byte Program Mode Flow Chart Start Address = G VDD = +6.5 V, VPP = +12.5 V X=0 X=X+1 No X = 10 ? 0.1-ms program pulse Yes Address = Address + 1 Fail Verify Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass Write end Defective product G = Start address N = Program last address 23 µPD78P083(A) Figure 4-4. Byte Program Mode Timing Program Program Verify A0-A14 D0-D7 Data Input Data Output VPP VPP VDD VDD VDD + 1.5 VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. VDD should be applied before VPP and removed after VPP. 2. VPP must not exceed +13.5 V including overshoot. 3. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being applied to VPP. 24 µPD78P083(A) 4.3 PROM Read Procedure The contents of PROM are readable to the external data bus (D0-D7) according to the read procedure shown below. (1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in “PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode”. (2) Supply +5 V to the VDD and VPP pins. (3) Input address of read data into the A0 to A14 pins. (4) Read mode (5) Output data to D0 to D7 pins. The timings of the above steps (2) to (5) are shown in Figure 4-5. Figure 4-5. PROM Read Timings A0-A14 Address Input CE (Input) OE (Input) D0-D7 Hi-Z Data Output Hi-Z 25 µPD78P083(A) 5. ONE-TIME PROM VERSION SCREENING The one-time PROM version ( µPD78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTXNote) cannot be tested completely by NEC before it is shipped, because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and performing high-temperature storage under the condition below. Note Under planning Storage Temperature Storage Time 125°C 24 hours NEC offers for an additional fee one-time PROM writing to marking, screening, and verify for products designated as QTOP Microcontroller. A fee-charged service for the µ PD78P083(A) is under planning. Consult an NEC sales representative for details. 26 µPD78P083(A) 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A = 25°C) Parameter Symbol Ratings Unit Supply voltage VDD –0.3 to +7.0 V VPP –0.3 to +13.5 V AVDD –0.3 to VDD + 0.3 V AVREF –0.3 to VDD + 0.3 V AVSS –0.3 to +0.3 V VI1 –0.3 to VDD + 0.3 Input voltage VI2 Output voltage VO Analog input voltage VAN Output current, high I OH Test Conditions A9 PROM programming mode –0.3 to +13.5 V –0.3 to VDD + 0.3 V P10 to P17 Analog input pins AVSS – 0.3 to AVREF + 0.3 V Per pin –10 mA Total for P10 to P17, P50 to P54, –15 mA –15 mA Peak value 30 mA r.m.s. value 15 mA P70 to P72, P100, P101 Total for P01 to P03, P30 to P37, P55 to P57 Output current, low I OL Note Per pin Total for P50 to P54 Total for P55 to P57 Peak value 100 mA r.m.s. value 70 mA Peak value 100 mA r.m.s. value 70 mA Total for P10 to P17, Peak value 50 mA P70 to P72, P100, P101 r.m.s. value 20 mA Total for P01 to P03, Peak value 50 mA P30 to P37 r.m.s. value 20 mA Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value] × Duty Caution If the absolute maximum rating of even one of the above parameters is exceeded, the quality of the product may be degraded. The absolute maximum ratings are therefore the rated values that may, if exceeded, physically damage the product. Be sure to use the product with all the absolute maximum ratings observed. Remark Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. 27 µPD78P083(A) Capacitance (T A = 25°C, VDD = VSS = 0 V) Parameter Symbol Test Conditions MAX. Unit Input capacitance CIN f = 1 MHz, Unmeasured pins returned to 0 V. MIN. TYP. 15 pF I/O capacitance CIO f = 1 MHz, Unmeasured pins returned to 0 V. 15 pF P01 to P03, P10 to P17, P30 to P37, P50 to P57, P70 to P72, P100, P101 Remark Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Ceramic resonator VPP X2 X1 Parameter Test Conditions MIN. TYP. MAX. Unit Oscillation frequency VDD = Oscillation voltage range 1.0 5.0 MHz After VDD came to MIN. 4 ms 5.0 MHz 10 ms (fX) Note 1 C2 C1 Oscillation stabilization time Crystal resonator VPP X2 X1 C1 of oscillation voltage range Oscillation frequency (fX) C2 Note 2 1.0 Note 1 Oscillation stabilization VDD = 4.5 to 5.5 V time Note 2 External clock X2 X1 X1 input frequency (fX) µ PD74HCU04 30 1.0 5.0 MHz 85 500 ns Note 1 X1 input high- and low-level widths (tXH , tXL ) Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. 2. Time required for oscillation to stabilize after a reset or the STOP mode has been released. Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines in the figures as follows to avoid adverse influences on the wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring over other signal lines. • Do not route the wiring in the vicinity of lines through which a high fluctuating current flows. • Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS . • Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 28 µPD78P083(A) DC Characteristics (T A = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 Input voltage, low VIL1 VIL2 Test Conditions Output voltage, low TYP. MAX. Unit P10 to P17, P30 to P32, VDD = 2.7 to 5.5 V P35 to P37, P50 to P57, P71 0.7VDD VDD V 0.8VDD VDD V P00 to P03, P33, P34, P70, P72, P100, P101, RESET VDD = 2.7 to 5.5 V 0.8VDD VDD V 0.85VDD VDD V X1, X2 VDD = 2.7 to 5.5 V VDD – 0.5 VDD V VDD – 0.2 VDD V P10 to P17, P30 to P32, VDD = 2.7 to 5.5 V P35 to P37, P50 to P57, P71 0 0.3VDD V 0 0.2VDD V P00 to P03, P33, P34, P70, P72, P100, 0 0.2VDD V 0 0.15VDD V 0 0.4 V 0 0.2 V VDD = 2.7 to 5.5 V P101, RESET Output voltage, high MIN. VIL3 X1, X2 VOH VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V I OH = –100 µA VDD – 0.5 V VOL P50 to P57 VDD = 2.7 to 5.5 V VDD = 2.0 to 4.5 V, 0.8 V 2.0 V 0.4 V 0.5 V 3 µA X1, X2 20 µA P00 to P03, P10 to P17, –3 µA –20 µA 3 µA –3 µA 90 kΩ I OL = 10 mA VDD = 4.5 to 5.5 V, 0.4 I OL = 15 mA P01 to P03, P10 to P17, VDD = 4.5 to 5.5 V, P30 to P37, P70 to P72, I OL = 1.6 mA Input-leak current, high ILIH1 P100, P101 I OL = 400 µA VIN = VDD P00 to P03, P10 to P17, P30 to P37, P50 to P57, P70 to P72, P100, P101, RESET ILIH2 Input-leak current, low ILIL1 VIN = 0 V P30 to P37, P50 to P57, P70 to P72, P100, P101, RESET ILIL2 X1, X2 Output leak current, high ILOH VOUT = V DD Output leak current, low ILOL VOUT = 0 V Software pull-up resistor R VIN = 0 V P01 to P03, P10 to P17, 15 40 P30 to P37, P50 to P57, P70 to P72, P100, P101 Remark Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. 29 µPD78P083(A) DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Supply current Note 1 Symbol I DD1 Test Conditions MAX. Unit VDD = 5.0 V ± 10% 5.4 16.2 mA oscillation operating VDD = 3.0 V ± 10% Note 5 0.8 2.4 mA VDD = 2.0 V ± 10% Note 5 0.45 1.35 mA 5.0-MHz crystal oscillation VDD = 5.0 V ± 10% Note 4 9.5 28.5 mA VDD = 3.0 V ± 10% Note 5 1.0 3.0 mA 1.4 4.2 mA Note 2 operating mode (fXX = 5.0 MHz) Note 3 5.0-MHz crystal oscillation VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% 0.5 1.5 mA VDD = 2.0 V ± 10% 280 840 µA 5.0-MHz crystal oscillation VDD = 5.0 V ± 10% 1.6 4.8 mA VDD = 3.0 V ± 10% 0.65 1.95 mA VDD = 5.0 V ± 10% 0.1 30 µA VDD = 3.0 V ± 10% 0.05 10 µA VDD = 2.0 V ± 10% 0.05 10 µA HALT mode (fXX = 2.5 MHz) Note 2 HALT mode (fXX = 5.0 MHz) I DD3 TYP. 5.0-MHz crystal mode (fXX = 2.5 MHz) I DD2 MIN. Note 4 Note 3 STOP mode Notes 1. Not including AVREF , AVDD currents or port currents (including current flowing into internal pull-up resistors). 2. fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H). 3. fXX = fX operation (when oscillation mode selection register (OSMS) is set to 01H). 4. High-speed mode operation (when processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when processor clock control register (PCC) is set to 04H). Remark fXX: Main system clock frequency (f X or fX/2) fX: Main system clock oscillation frequency 30 µPD78P083(A) AC Characteristics (1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Cycle time Test Conditions TCY f XX = fX/2 Note1 MIN. MAX. Unit 0.8 64 µs 2.0 64 µs 3.5 V ≤ VDD ≤ 5.5 V 0.4 32 µs 2.7 V ≤ VDD < 3.5 V 0.8 32 µs 0 4 MHz 0 275 kHz VDD = 2.7 to 5.5 V (minimum instruction execution time) f XX = fX/ TI5, TI6 fTI Note2 VDD = 4.5 to 5.5 V input frequency TI5, TI6 input high-/ tTIH , VDD = 4.5 to 5.5 V low-level widths tTIL Interrupt input high-/ tINTH, low-level widths tINTL RESET low-level width tRSL TYP. 100 ns 1.8 µs 10 µs 20 µs 10 µs 20 µs VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V Notes 1. When oscillation mode selection register (OSMS) is set to 00H. 2. When OSMS is set to 01H. Remark fXX: Main system clock frequency (f X or fX/2) fX: Main system clock oscillation frequency TCY vs VDD T CY vs VDD (Main System Clock f XX = fX /2 Operation) (Main System Clock fXX = fX Operation) 60 10 Cycle Time TCY [µ s] Cycle Time TCY [µ s] 60 Operation Guaranteed Range 2.0 1.0 0.5 0.4 0 10 Operation Guaranteed Range 2.0 1.0 0.5 0.4 1 2 3 4 5 6 Power Supply Voltage VDD [V] 0 1 2 3 4 5 6 Power Supply Voltage VDD [V] 31 µPD78P083(A) (2) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (a) 3-wired serial I/O mode (SCK2 ··· internal clock output) Parameter SCK2 cycle time SCK2 high-/low-level width Symbol t KCY1 t KH1, Test Conditions t SIK1 t KSO1 MAX. Unit 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns tKCY1/2–50 ns t KCY1/2–100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.7 V ≤ VDD < 4.5 V 150 ns 2.0 V ≤ VDD < 2.7 V 300 ns 400 ns VDD = 4.5 to 5.5 V SI2 hold time (from SCK2 ↑) t KSI1 SCK2 ↓ → SO2 output delay time TYP. 4.5 V ≤ VDD ≤ 5.5 V t KL1 SI2 setup time (to SCK2 ↑) MIN. 400 ns C = 100 pFNote 300 ns MAX. Unit Note C is the SCK2, SO2 output line load capacitance. (b) 3-wired serial I/O mode (SCK2 ··· external clock input) Parameter SCK2 cycle time Symbol t KCY2 Test Conditions ns 2.7 V ≤ VDD < 4.5 V 1600 ns ns t KL2 2.7 V ≤ VDD < 4.5 V 800 ns t SIK2 VDD = 2.0 to 5.5 V t KSO2 C = 100 pFNote t R2, t F2 Note C is the SO2 output line load capacitance. 32 ns 400 output delay time SCK2 rise, fall time ns 4.5 V ≤ VDD ≤ 5.5 V SI2 hold time (from SCK2 ↑) t KSI2 SCK2 ↓ → SO2 3200 4800 t KH2, 2.0 V ≤ VDD < 2.7 V SI2 setup time (to SCK2 ↑) TYP. 800 2.0 V ≤ VDD < 2.7 V SCK2 high-/low-level width MIN. 4.5 V ≤ VDD ≤ 5.5 V VDD = 2.0 to 5.5 V 1600 ns 2400 ns 100 ns 150 ns 400 ns 300 ns 500 ns 1000 ns µPD78P083(A) (c) UART mode (Dedicated baud rate generator output) Parameter Symbol Transfer rate Test Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 78125 bps 2.7 V ≤ VDD < 4.5 V 39063 bps 2.0 V ≤ VDD < 2.7 V 19531 bps 9766 bps MAX. Unit (d) UART mode (External clock input) Parameter ASCK cycle time ASCK high-/low-level width Symbol t KCY3 MIN. TYP. 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns t KH3, 4.5 V ≤ VDD ≤ 5.5 V 400 ns t KL3 2.7 V ≤ VDD < 4.5 V 800 ns 2.0 V ≤ VDD < 2.7 V 1600 ns 2400 ns Transfer rate ASCK rise, fall time Test Conditions t R3, t F3 4.5 V ≤ VDD ≤ 5.5 V 39063 bps 2.7 V ≤ VDD < 4.5 V 19531 bps 2.0 V ≤ VDD < 2.7 V 9766 bps 6510 bps 1000 ns 33 µPD78P083(A) AC Timing Test Point (Excluding X1 Input) 0.8 VDD 0.2 VDD 0.8 VDD Test Points 0.2 VDD Clock Timing 1/fx tXL tXH VIH3 (MIN.) X1 Input VIL3 (MAX.) TI Timing 1/fTI tTIL TI5, TI6 34 tTIH µPD78P083(A) Serial Transfer Timing 3-wired serial I/O mode: tKCY1, 2 tKH1, 2 tKL1, 2 tR2 tF2 SCK2 tSIK1, 2 tKSI1, 2 Input Data SI2 tKSO1, 2 Output Data SO2 UART mode (external clock input): tKCY3 tKL3 tKH3 tR3 tF3 ASCK 35 µPD78P083(A) A/D Converter Characteristics (T A = –40 to +85°C, AVDD = VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions Resolution Total error MIN. TYP. MAX. Unit 8 8 8 bit 1.4 % 200 µs 2.7 V ≤ AVREF ≤ AVDD Note Conversion time t CONV 19.1 Sampling time t SAMP 12/f XX Analog input voltage VIAN AVSS AVREF V Reference voltage AVREF 2.7 AVDD V AVREF-AV SS resistance RAIREF 4 µs 14 Note Excluding quantization error (±1/2 LSB). Shown as a percentage of the full scale value. Remark fXX : Main system clock frequency (fX or fX /2) fX: Main system clock oscillation frequency 36 kΩ µPD78P083(A) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T A = –40 to +85°C) Parameter Symbol Test Conditions MIN. Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal set time t SREL Oscillation stabilization wait time tWAIT TYP. 1.8 VDDDR = 1.8 V 0.1 MAX. Unit 5.5 V 10 µA µs 0 Release by RESET 17 2 /f X ms Release by interrupt Note ms Note 2 12/fXX or 2 14/fXX to 217/f XX can be selected by bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time selection register (OSTS). Remark fXX : Main system clock frequency (fX or f X/2) fX : Main system clock oscillation frequency Data Retention Timing (STOP mode released by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby release signal: STOP mode released by interrupt request signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 37 µPD78P083(A) Interrupt Input Timing tINTH tINTL INTP1-INTP3 RESET Input Timing tRSL RESET 38 µPD78P083(A) PROM Programming Characteristics DC Characteristics (1) PROM Write Mode (T A = 25 ±5˚C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter Symbol Symbol Note Test Conditions MIN. TYP. MAX. Unit 0.7VDD VDD V 0 0.3VDD V Input voltage, high VIH VIH Input voltage, low VIL VIL Output voltage, high VOH VOH I OH = –1 mA Output voltage, low VOL VOL I OL = 1.6 mA Input leakage current ILI ILI 0 ≤ VIN ≤ VDD VPP supply voltage VPP VPP 12.2 12.5 VDD supply voltage VDD VCC 6.25 6.5 6.75 V VPP supply current IPP IPP 50 mA VDD supply current IDD ICC 50 mA MAX. Unit 0.7VDD VDD V 0 0.3VDD VDD – 1.0 V –10 PGM = VIL 0.4 V +10 µA 12.8 V (2) PROM Read Mode (T A = 25 ±5˚C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V) Parameter Symbol SymbolNote Test Conditions MIN. TYP. Input voltage, high VIH VIH Input voltage, low VIL VIL Output voltage, high VOH1 VOH1 IOH = –1 mA VDD – 1.0 V VOH2 VOH2 IOH = –100 µ A VDD – 0.5 V Output voltage, low VOL VOL IOL = 1.6 mA Input leakage current I LI I LI 0 ≤ VIN ≤ VDD Output leakage current I LO I LO 0 ≤ VOUT ≤ VDD, OE = VIH VPP supply voltage VPP VPP VDD supply voltage VDD VCC VPP supply current I PP I PP VPP = V DD VDD supply current I DD I CCA1 CE = VIL , V IN = V IH V 0.4 V –10 +10 µA –10 +10 µA VDD + 0.6 V VDD – 0.6 VDD 4.5 5.0 5.5 V 100 µA 50 mA Note Corresponding µPD27C1001A symbol. 39 µPD78P083(A) AC Characteristics (1) PROM Write Mode (a) Page program mode (TA = 25 ±5˚C, VDD = 6.5 ±0.25 V, V PP = 12.5 ±0.3 V) Parameter Symbol Symbol Note Test Conditions MIN. TYP. MAX. Unit Address setup time (to OE ↓) t AS tAS 2 µs OE setup time t OES tOES 2 µs CE setup time (to OE ↓) t CES t CES 2 µs Input data setup time (to OE ↓) t DS t DS 2 µs Address hold time (from OE ↑) t AH t AH 2 µs t AHL t AHL 2 µs t AHV t AHV 0 µs Input data hold time (from OE ↑) t DH tDH 2 µs OE ↑ → Data output float t DF tDF 0 VPP setup time (to OE ↓) t VPS tVPS 1.0 VDD setup time (to OE ↓) t VDS t VCS 1.0 Program pulse width t PW t PW 0.095 OE ↓ → Valid data delay time t OE tOE OE pulse width during data latching t LW t LW 1 µs PGM setup time t PGMS t PGMS 2 µs CE hold time t CEH tCEH 2 µs OE hold time t OEH t OEH 2 µs 250 ns delay time ms ms 0.1 0.105 ms 1 µs (b) Byte program mode (TA = 25 ±5˚C, VDD = 6.5 ±0.25 V, V PP = 12.5 ±0.3 V) Parameter Symbol Symbol Note Test Conditions MIN. TYP. MAX. Unit tAS t AS 2 µs OE setup time tOES t OES 2 µs CE setup time (to PGM ↓) tCES t CES 2 µs Input data setup time (to PGM ↓) tDS t DS 2 µs Address hold time (from OE ↑) tAH t AH 2 µs Input data hold time tDH t DH 2 µs OE ↑ → Data output float delay time tDF t DF 0 VPP setup time (to PGM ↓) tVPS t VPS 1.0 VDD setup time (to PGM ↓) tVDS t VCS 1.0 Program pulse width tPW t PW 0.095 OE ↓ → Valid data delay time tOE t OE OE hold time tOEH Address setup time (to PGM ↓) (from PGM ↑) — Note Corresponding µ PD27C1001A symbol. 40 2 250 ns ms ms 0.1 0.105 ms 1 µs µs µPD78P083(A) (2) PROM Read Mode (TA = 25 ±5˚C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V) Parameter Symbol Symbol Note Test Conditions MIN. TYP. MAX. Unit Address ↑ → Data output float delay time t ACC tACC CE = OE = VIL 800 ns CE ↓ → Valid output delay time t CE tCE OE = VIL 800 ns OE ↓ → Valid output delay time t OE tOE CE = VIL 200 ns OE ↓ → Data output float delay time t DF tDF CE = VIL 0 60 ns Address → Data hold time t OH tOH CE = OE = VIL 0 ns Note Corresponding µ PD27C1001A symbol. (3) PROM Programming Mode (T A = 25˚C, VSS = 0 V) Parameter PROM programming mode setup time Symbol tSMA Test Conditions MIN. 10 TYP. MAX. Unit µs 41 µPD78P083(A) PROM Write Mode Timing (page program mode) Page Data Latch Page Program Program Verify A2-A14 tAS tAHL tAHV tDS tDH tDF A0, A1 D0-D7 Hi-Z Hi-Z tVPS Data Input Hi-Z tPGMS Data tAH tOE Output VPP VPP VDD tVDS VDD+1.5 VDD VDD tOEH tCES VIH CE VIL tCEH tPW VIH PGM VIL tLW VIH OE VIL 42 tOES µPD78P083(A) PROM Write Mode Timing (byte program mode) Program Program Verify A0-A14 tDF tAS D0-D7 Hi-Z Hi-Z Data Input tDS Hi-Z Data Output tDH tAH VPP VPP VDD VDD+1.5 VDD VDD tVPS tVDS tOEH VIH CE VIL tCES tPW VIH PGM VIL tOES tOE VIH OE VIL Cautions 1. VDD should be applied before VPP, and removed after V PP. 2. VPP must not exceed +13.5 V including overshoot. 3. Reliability may be adversely affected if removal/reinsertion is performed while + 12.5 V is being applied to VPP. PROM Read Mode Timing Effective Address A0-A14 VIH CE VIL tCE VIH OE VIL tACCNote 1 D0-D7 Hi-Z tOENote 1 tDFNote 2 tOH Data Output Hi-Z Notes 1. If you want to read within the range of tACC, make the OE input delay time from the fall of CE a maximum of t ACC – tOE. 2. t DF is the time from when either OE or CE first reaches VIH. 43 µPD78P083(A) PROM Programming Mode Setting Timing VDD VDD 0 RESET VDD VPP 0 tSMA A0-A14 44 Effective Address µPD78P083(A) 7. PACKAGE DRAWINGS 42PIN PLASTIC SHRINK DIP (600 mil) 42 22 1 21 A K H G J I L F B D N R M C M NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 39.13 MAX. 1.541 MAX. B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K L 15.24 (T.P.) 13.2 0.600 (T.P.) 0.520 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P42C-70-600A-1 Remark The shape and material of ES versions are the same as those of mass-produced versions. 45 µPD78P083(A) µ PD78P083GB(A)-3B4 44 PIN PLASTIC QFP ( 10) A B 23 22 33 34 detail of lead end C D S R Q 12 11 44 1 F G J H I M K M P N L NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 13.6±0.4 0.535 +0.017 –0.016 B 10.0±0.2 0.394 +0.008 –0.009 C 10.0±0.2 0.394 +0.008 –0.009 D 13.6±0.4 0.535 +0.017 –0.016 F 1.0 0.039 G 1.0 0.039 H 0.35±0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N P Q R S 0.10 2.7 0.1±0.1 5°±5° 3.0 MAX. 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. P44GB-80-3B4-3 Remark The shape and material of ES versions are the same as those of mass-produced versions. 46 INCHES µPD78P083(A) µPD78P083GB(A)-3BS-MTX (Under planning) 44 PIN PLASTIC QFP ( 10) A B 23 22 33 34 detail of lead end C D S R Q 12 11 44 1 F J G H I M K M P N L NOTE Each lead centerline is located within 0.16 mm (0.007 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 13.2±0.2 0.520 +0.008 –0.009 B 10.0±0.2 0.394 +0.008 –0.009 C 10.0±0.2 0.394 +0.008 –0.009 D 13.2±0.2 0.520 +0.008 –0.009 F 1.0 0.039 G 1.0 0.039 H 0.37 +0.08 –0.07 0.015 +0.003 –0.004 I 0.16 0.007 J 0.8 (T.P.) 0.031 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.17 +0.06 –0.05 0.007 +0.002 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.125±0.075 R 3° +7° –3° 0.005±0.003 3° +7° –3° S 3.0 MAX. 0.119 MAX. S44GB-80-3BS Remark The shape and material of ES versions are the same as those of mass-produced versions. 47 µPD78P083(A) 8. RECOMMENDED SOLDERING CONDITIONS It is recommended that the µ PD78P083(A) be soldered under the following conditions. For details on the recommended soldering conditions, refer to information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. Table 8-1. Soldering Conditions for Surface Mount Types µ PD78P083GB(A)-3B4 : 44-pin plastic QFP (10 × 10 mm) Soldering Method Infrared ray reflow VPS Wave soldering Partial heating Soldering Conditions Package peak temperature: 235˚C, Reflow time: 30 seconds or less (at 210˚C or higher), Number of reflow processes: 3 or less Package peak temperature: 215˚C, Reflow time: 40 seconds or less (at 200˚C or higher), Number of reflow processes: 3 or less Solder temperature: 260˚C or below, Flow time: 10 seconds or less, Number of flow processes: 1, Preheating temperature: 120˚C max. (package surface temperature) Pin temperature: 300˚C or below, Flow time: 3 seconds or less (per pin row) Symbol IR35-00-3 VP15-00-3 WS60-00-1 — Cautions 1. Do not use different soldering methods together (except for partial heating method). 2. Soldering conditions for the µ PD78P083GB(A)-3BS-MTX is not fixed because this product is under planning. Table 8-2. Soldering Condition for Hole-Through Types µ PD78P083CU(A) : 42-pin plastic shrink DIP (600 mil) Soldering Method Wave Soldering (only pins) Partial heating Caution Soldering Conditions Solder temperature: 260°C or below, Flow time: 10 seconds or less Pin temperature: 300°C or below, Flow time: 3 seconds or less (per pin) Apply wave soldering only to the pins and be careful so as not to bring solder into direct contact with the package. 48 µPD78P083(A) APPENDIX A. DEVELOPMENT TOOLS The following development tools are available to support development of systems using the µ PD78P083(A). Language Processing Software RA78K/0 Notes 1, 2, 3, 4 Assembler package common to the 78K/0 Series CC78K/0 Notes 1, 2, 3, 4 C compiler package common to the 78K/0 Series DF78083 Device file used for the µPD78083 Subseries Notes 1, 2, 3, 4 CC78K/0–L Notes 1, 2, 3, 4 C compiler library source file common to the 78K/0 Series PROM Writing Tools PG-1500 PROM programmer PA-78P083CU PA-78P083GB Programmer adapter connected to the PG-1500 PG-1500 Controller Notes 1, 2 Control program for the PG-1500 Debugging Tools IE-78000-R In-circuit emulator common to the 78K/0 Series IE-78000-R-A In-circuit emulator common to the 78K/0 Series (for integrated debugger) IE-78000-R-BK Break board common to the 78K/0 Series IE-78078-R-EM Emulation board common to the µPD78078 Subseries EP-78083CU-R EP-78083GB-R Emulation probe for the µPD78083 Subseries EV-9200G-44 Socket mounted on the target system board prepared for 44-pin plastic QFP (GB-3B4, GB-3BS-MTX type) SM78K0 ID78K0 Notes 5, 6, 7 Notes 4, 5, 6, 7 SD78K/0 Notes 1, 2 DF78083 System simulator common to the 78K/0 Series Integrated debugger for IE-78000-R-A Screen debugger for the IE-78000-R Notes 1, 2, 4, 5, 6, 7 Device file used for the µPD78083 Subseries Notes 1. Based on PC-9800 series (MS-DOSTM ) 2. Based on IBM PC/AT TM and its compatibles (PC DOSTM /IBM DOSTM /MS-DOS) 3. Based on HP9000 series 300 TM (HP-UX TM) 4. Based on HP9000 series 700 TM (HP-UX), SPARCstationTM (SunOSTM), and EWS4800 series (EWS-UX/ V) 5. Based on PC-9800 series (MS-DOS + WindowsTM ) 6. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) 7. Based on NEWS TM (NEWS-OSTM) Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development tools. 2. Use the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0 in combination with the DF78083. 49 µPD78P083(A) OS MX78K/0 Notes 1, 3, 4 78K/0 Series common embedded OS Fuzzy Inference Development Support System FE9000 Note 1 /FE9200 Note 2 Fuzzy knowledge data creation tool FT9080 Note 1 /FT9085 Note 3 Translator FI78K0 Notes 1, 3 FD78K0 Notes 1, 3 Fuzzy inference module Fuzzy inference debugger Notes 1. Based on PC-9800 series (MS-DOS) 2. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS+Windows) 3. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) 4. Based on HP9000 series 300 and series 700 (HP-UX), SPARCstation (SunOS), and EWS4800 series (EWS-UX/V) Remark Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development tools. 50 µPD78P083(A) APPENDIX B. RELATED DOCUMENTS Documents Related to Devices Document Name Document No. Japanese English µPD78083 Subseries User’s Manual U12176J U12176E 78K/0 Series User’s Manual—Instructions IEU-849 IEU-1372 78K/0 Series Instruction Table U10903J — 78K/0 Series Instruction Set U10904J — µPD78083 Subseries Special Function Register Table IEM-5599 — IEA-767 U10182E 78K/0 Series Application Note Caution Basic (III) The contents of the documents listed above are subject to change without prior notice. Make sure to use the latest edition when starting design. 51 µPD78P083(A) Documents Related to Development Tools (User's Manual) Document Name RA78K Series Assembler Package RA78K0 Assembler Package Document No. Japanese English Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 Operation U11802J U11802E Assembly language U11801J U11801E Structured assembly language U11789J U11789E EEU-817 EEU-1402 RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Operation U11517J U11517E Language U11518J U11518E Programming know-how EEA-618 EEA-1208 CC78K Series Library Source File EEU-777 — PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller PC-9800 Series (MS-DOS) Based EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC DOS) Based EEU-5008 U10540E IE-78000-R EEU-810 U11376E IE-78000-R-BK EEU-867 EEU-1427 IE-78000-R-A U10057J U10057E IE-78078-R-EM U10775J EEU-1504 EEU-5003 EEU-1529 CC78K/0 C Compiler CC78K/0 C Compiler Application Note EP-78083 SM78K0 System Simulator Windows Based Reference U10181J U10181E SM78K Series System Simulator External parts user open interface specification U10092J U10092E ID78K0 Integrated Debugger EWS Based Reference U11151J — ID78K0 Integrated Debugger PC Based Reference U11539J U11539E ID78K0 Integrated Debugger Guides U11649J U11649E SD78K/0 Screen Debugger Introduction EEU-852 U10539E PC-9800 Series (MS-DOS) Based Reference U10952J — EEU-5024 EEU-1414 U11279J U11279E SD78K/0 Screen Debugger Introduction IBM PC/AT (PC DOS) Based Reference Caution The contents of the documents listed above are subject to change without prior notice. Make sure to use the latest edition when starting design. 52 µPD78P083(A) Documents Related to Embedded Software (User’s Manual) Document Name 78K/0 Series OS MX78K0 Document No. Japanese English Basic EEU-5010 — Fuzzy Knowledge Data Creation Tool EEU-829 EEU-1438 78K/0, 78K/II, and 87AD Series Fuzzy Inference Development Support System Translator EEU-862 EEU-1444 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU-858 EEU-1441 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-921 EEU-1458 Other Documents Document Name Document No. Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 — Guide to Quality Assurance for Semicoductor Devices C11893J MEI-1202 Microcontroller-Related Product Guide – Third Party Products – U11416J — Caution The contents of the documents listed above are subject to change without prior notice. Be sure to use the latest edition when starting design. 53 µPD78P083(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 54 µPD78P083(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 55 µPD78P083(A) FIP, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representive. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5