DATA SHEET MOS INTEGRATED CIRCUIT µPD78F9801 8-BIT SINGLE-CHIP MICROCONTROLLER The µPD78F9801 is a µPD789800 subseries product (for a USB keyboard (for a PC)) of the 78K/0S series. The µPD78F9801 replaces the internal masked ROM of the µPD789800 with flash memory, which enables the writing/erasing of a program while the device is mounted on the board. Because the device can be programmed by the user, it is ideally suited to the evaluation stages of system development, the manufacture of small batches of multiple products, and the rapid development of new products. The functions of this microcontroller are described in the following user’s manuals. Refer to these manuals when designing a system based on this microcontroller. µPD789800 Subseries User’s Manual : U12978E 78K/0S Series User's Manual - Instruction: U11047E FEATURES • Pin-compatible with masked ROM version (excluding VPP pin) • Flash memory: 16K bytes • Internal high-speed RAM: 256 bytes • Operable on the same supply voltage as masked ROM version (VDD = 4.0 to 5.5 V) Remark The differences between the flash memory and masked ROM versions are summarized in Chapter 3. APPLICATIONS USB keyboards ORDERING INFORMATION Part Number µPD78F9801GB-8ES Package 44-pin plastic QFP (10 × 10 mm) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12626EJ2V0DS00 (2nd edition) Date Published November 2001 J CP(K) Printed in Japan The mark shows major revised points. © 1997, 1999 µPD78F9801 78K/0S SERIES DEVELOPMENT The 78K/0S series products are shown below. The sub-series names are indicated in frames. Products in mass production Products under development Y subseries products support SMB. Small-scale package, general-purpose applications µ PD789074 with added subsystem clock µ PD789014 with enhanced timer and increased ROM, RAM capacity µ PD789074 with enhanced timer and increased ROM, RAM capacity µ PD789026 with enhanced timer µ PD789046 44-pin 42/44-pin µ PD789026 µ PD789088 µ PD789074 µ PD789014 30-pin 30-pin 28-pin On-chip UART and capable of low voltage (1.8 V) operation Small-scale package, general-purpose applications and A/D converter µ PD789177 µ PD789167 µ PD789156 µ PD789146 µ PD789134A µ PD789124A µ PD789114A µ PD789104A 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin µ PD789177Y µ PD789167Y µ PD789167 with enhanced 10-bit A/D converter µ PD789104A with enhanced timer µ PD789146 with enhanced 10-bit A/D converter µ PD789104A with added EEPROMTM µ PD789124A with enhanced 10-bit A/D converter RC oscillation version of the µ PD789104A µ PD789104A with enhanced 10-bit A/D converter µ PD789026 with added 8-bit A/D converter and multiplier LCD drive 78K/0S Series 144-pin µ PD789835 UART, 8-bit A/D converter, and dot LCD (Total display outputs: 96) 88-pin µ PD789830 UART and dot LCD (40 × 16) 80-pin µ PD789488 80-pin 80-pin µ PD789477 µ PD789417A µ PD789407A µ PD789456 µ PD789446 µ PD789436 µ PD789426 µ PD789316 µ PD789306 µ PD789467 SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4) SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4) µ PD789407A with enhanced 10-bit A/D converter SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4) µ PD789446 with enhanced 10-bit A/D converter SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (15 × 4) µPD789426 with enhanced 10-bit A/D converter SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (5 × 4) RC oscillation version of the µPD789306 SIO and on-chip voltage booster type LCD (24 × 4) 8-bit A/D converter and on-chip voltage booster type LCD (23 × 4) 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 52-pin 52-pin µ PD789327 SIO and resistance division type LCD (24 × 4) µ PD789803 For PC keyboard, on-chip USB HUB function For PC keyboard, on-chip USB function USB 64-pin 44-pin µ PD789800 Inverter control 44-pin µ PD789842 On-chip inverter controller and UART On-chip bus controller 30-pin µ PD789850 On-chip CAN controller Keyless entry 20-pin 20-pin µ PD789861 RC oscillation version of the µPD789860 On-chip POC and key return circuit µ PD789860 VFD drive 52-pin µ PD789871 On-chip VFD controller (Total display outputs: 25) Meter control 64-pin Remark µ PD789881 UART and resistance division type LCD (26 × 4) The vacuum fluorescent display (VFD) is a typical name. In some documents, however, it is described TM as the fluorescent indicator panel (FIP ). The VFD and FIP have identical functions. 2 Data Sheet U12626EJ2V0DS µPD78F9801 The major functional differences among the subseries are listed below. Series for General-Purpose Applications and LCD Drive Function Subseries Name Small scale, generalpurpose applications Smallscale, generalpurpose applications + A/D function ROM Capacity (Bytes) Timer 8-Bit 16Watch WDT Bit 1 ch 1 ch µPD789046 16 K µPD789026 4 K to 16 K µPD789088 16 K to 32 K 3 ch µPD789074 2 K to 8 K 1 ch µPD789014 2 K to 4 K 2 ch µPD789177 16 K to 24 K 3 ch 1 ch 1 ch A/D A/D − − 1 ch 1 ch 1ch − 1 ch (UART: 1 ch) 34 1.8 V − 1.8 V − 8 ch 1 ch (UART: 1 ch) 4 ch 4 ch − − 4 ch µPD789124A 4 ch − µPD789114A − 4 ch µPD789104A 4 ch − 3 ch − − 1 ch µPD789146 µPD789134A 2 K to 8 K 24 K to 60 K 6 ch µPD789830 24 K 1 ch µPD789488 32 K 3 ch µPD789477 24 K − 1 ch 1 ch 1 ch − µPD789407A − 1 ch (UART: 1 ch) 45 7 ch 1 ch (UART: 1 ch) − 6 ch µPD789446 6 ch − µPD789436 − 6 ch µPD789426 6 ch − 1.8 V − − 43 30 40 2 ch (UART: 1 ch) 23 µPD789306 µPD789467 1.8 VNote Dot LCD support 2.7 V − − 8 K to 16 K 37 30 7 ch 12 K to 16 K 2 ch On-chip EEPROM RC oscillation version − 8 ch 31 20 8 ch 2 ch (UART: 1 ch) µPD789417A 12 K to 24 K µPD789316 Remark 22 − µPD789456 MIN. Value − − LCD drive µPD789835 I/O 24 8 ch 8 K to 16 K Serial Interface − µPD789167 µPD789156 VDD 8-Bit 10-Bit RC oscillation version − 4 K to 24 K µPD789327 − − 1 ch − 1 ch 18 21 Note Flash memory version: 3.0 V Data Sheet U12626EJ2V0DS 3 µPD78F9801 Series for ASSP Function Timer ROM Capacity (Bytes) 8-Bit µPD789803 8 K to 16 K 2 ch µPD789800 8K µPD789842 8 K to 16 K 3 ch Note 1 1 ch On-chip bus µPD789850 controller 16 K 1 ch 1 ch Keyless entry 4K 2 ch − Subseries Name USB Inverter control µPD789861 16Watch WDT Bit − − VDD 8-Bit 10-Bit 1 ch A/D A/D − − Serial Interface I/O MIN. Value Remark 2 ch (USB: 1 ch) 41 3.6 V − 31 4.0 V 1 ch 8 ch − 1 ch (UART: 1 ch) 30 4.0 V − − 1 ch 4 ch − 2 ch (UART: 1 ch) 18 4.0 V − − 1 ch − − − 14 1.8 V RC oscillation version, onchip EEPROM On-chip EEPROM µPD789860 VFD drive µPD789871 Meter control µPD789881 4 K to 8 K 16 K − 1 ch 1 ch − 3 ch 2 ch 1 ch − − 1 ch − − Notes 1. 10-bit timer: 1 channel 2. Flash memory version: 3.0 V 4 Data Sheet U12626EJ2V0DS 1 ch 1 ch (UART: 1 ch) 33 28 2.7 V Note 2 2.7 V − µPD78F9801 FUNCTIONS Item Internal memory Function Flash memory 16K bytes High-speed RAM 256 bytes Minimum instruction execution time 0.33 µs/1.33 µs (when the system clock operates at 6.0 MHz) General-purpose register 8 bits × 8 registers Instruction set • 16-bit operation • Bit manipulation (set, reset, and test) etc. I/O ports CMOS I/O: 31 pins (Of these, 18 pins can be switched to N-ch open-drain I/O pins.) Serial interface • USB (Universal Serial Bus) function : 1 channel • Three-wire serial I/O mode : 1 channel Timer • 8-bit timer 00 : 1 channel • 8-bit timer/event counter 01 : 1 channel • Watchdog timer : 1 channel Regulator Incorporated (VREG = 3.3 ±0.3 V) Vector interrupt source Maskable Internal: 9, external: 2 Nonmaskable Internal: 1 Power supply voltage VDD = 4.0 to 5.5 V Operating ambient temperature • TA = -40 to +85 °C (when the USB is not operating) • TA = 0 to +70 °C (when the USB is operating) • TA = 10 to 40 °C (when a flash memory is written) Package 44-pin plastic QFP (10 × 10 mm) Data Sheet U12626EJ2V0DS 5 µPD78F9801 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................7 2. BLOCK DIAGRAM ............................................................................................................................8 3. DIFFERENCES BETWEEN µPD78F9801 AND MASKED ROM VERSION ....................................9 4. PIN FUNCTIONS ..............................................................................................................................10 4.1 Port Pins................................................................................................................................................ 10 4.2 Non-Port Pins........................................................................................................................................ 11 4.3 Pin Input/Output Circuits and Handling of Unused Pins .................................................................. 12 5. MEMORY SPACE ............................................................................................................................14 6. FLASH MEMORY PROGRAMMING................................................................................................15 7. 6.1 Selecting Communication Mode ......................................................................................................... 15 6.2 Function of Flash Memory Programming........................................................................................... 16 6.3 Flashpro III Connection........................................................................................................................ 16 6.4 Example of Settings for Flashpro III (PG-FP3) ................................................................................... 18 INSTRUCTION SET OVERVIEW .....................................................................................................19 7.1 7.2 Legend................................................................................................................................................... 19 7.1.1 Operand formats and descriptions ............................................................................................ 19 7.1.2 Descriptions of the operation field............................................................................................. 20 7.1.3 Description of the flag operation field........................................................................................ 20 Operations............................................................................................................................................. 21 8. ELECTRICAL CHARACTERISTICS................................................................................................26 9. PACKAGE DRAWING .....................................................................................................................34 10. RECOMMENDED SOLDERING CONDITIONS...............................................................................35 APPENDIX A DEVELOPMENT TOOLS...............................................................................................36 APPENDIX B RELATED DOCUMENTS ..............................................................................................38 6 Data Sheet U12626EJ2V0DS µPD78F9801 1. PIN CONFIGURATION (TOP VIEW) • 44-pin plastic QFP (10 x 10) P26/TI01/TO01/INTP0 P25 P24 NC P23 P22/SI10 P21/SO10 P20/SCK10 P07 P01 4 30 REGC P00 5 29 VDD0 VDD1 6 28 VSS0 VSS1 7 27 X1 P17 8 26 X2 P16 9 25 RESET P15 10 24 P40/KR00 P14 11 23 12 13 14 15 16 17 18 19 20 21 22 P41/KR01 P42/KR02 VPP P43/KR03 31 P44/KR04 3 P45/KR05 USBDM P02 P46/KR06 32 P10 2 P47/KR07 USBDP P03 P11 44 43 42 41 40 39 38 37 36 35 34 33 P12 1 P13 P04 NC Caution P06 P05 µPD78F9801GB-8ES In normal operation mode, connect the VPP pin directly to the VSS0 or VSS1 pin. INTP0 : Interrupt from peripherals KR00 - KR07 : Key return SI10 : Serial data input SO10 : Serial data output NC : No connection TI01 : Timer input P00-P07 : Port 0 TO01 : Timer output P10-P17 : Port 1 USBDM, USBDP : Universal serial bus data P20-P26 : Port 2 VDD0, VDD1 : Power supply P40-P47 RESET : Port 4 VPP : Programming power supply : Reset VSS0, VSS1 : Ground : Voltage regulator for USB function X1, X2 : Crystal REGC SCK10 : Serial clock input/output Data Sheet U12626EJ2V0DS 7 µPD78F9801 2. BLOCK DIAGRAM KR00/P40-KR07/P47 KEY RETURN0 8-bit TIMER00 TI01/TO01/P26/INTP0 8-bit TIMER/ EVENT COUNTER01 78K/0S CPU CORE PORT 0 P00-P07 PORT 1 P10-P17 PORT 2 P20-P26 PORT 4 P40-P47 SYSTEM CONTROL RESET X1 X2 FLASH MEMORY WATCHDOG TIMER REGC REGULATOR VREG USBDM USBDP SCK10/P20 SO10/P21 SI10/P22 INTP0/P26/TI01/TO01 8 USB FUNCTION0 RAM SERIAL INTERFACE10 INTERRUPT CONTROL VDD0 VDD1 VSS0 VSS1 VPP Data Sheet U12626EJ2V0DS µPD78F9801 3. DIFFERENCES BETWEEN µPD78F9801 AND MASKED ROM VERSION The µPD78F9801 is a product that substitutes flash memory for the internal ROM of the masked ROM version (µPD789800). The differences between the µPD78F9801 and the masked ROM versions are shown in Table 3-1. Table 3-1. Differences between µPD78F9801 and Masked ROM Version Flash Memory Version Masked ROM Version µPD78F9801 µPD789800 Item Internal memory ROM 16 Kbytes (Flash memory) High-speed RAM 256 bytes 8 Kbytes IC0 pin Not provided Provided VPP pin Provided Not provided Electric characteristics See the relevant data sheet. Caution There are differences in the amount of noise tolerance and noise radiation between flash memory versions and masked ROM versions. When considering changing from a flash memory version to a masked ROM version during process from experimental manufacturing to mass production, make sure to sufficiently evaluate the masked ROM versions using commercial samples (CS) (not engineering samples (ES)). Data Sheet U12626EJ2V0DS 9 µPD78F9801 4. PIN FUNCTIONS 4.1 Port Pins Pin Name P00-P07 I/O I/O Function Port 0 When Reset Also Used as Input - Input - 8-bit input/output port Input or output is specifiable bit by bit. When used as an input port, the use of on-chip pull-up resistors can be specified by software. CMOS output or N-ch open-drain output is specifiable in 8-bit units. P10-P17 I/O Port 1 8-bit input/output port Input or output is specifiable bit by bit. When used as an input port, the use of on-chip pull-up resistors can be specified by software. CMOS output or N-ch open-drain output is specifiable in 8-bit units. P20 I/O Port 2 Input 7-bit input/output port P21 SCK10 SO10 Input or output is specifiable bit by bit. P22 P23-P25 I/O Port 4 INTP0/TI01/TO01 Input 8-bit input/output port Input or output is specifiable bit by bit. When used as an input port, the use of on-chip pull-up resistors can be specified by software. 10 - Only for P25 and P26, CMOS output or N-ch open-drain output is specifiable bit by bit. P26 P40-P47 SI10 When used as an input port, the use of on-chip pull-up resistors can be specified by software. Data Sheet U12626EJ2V0DS KR00 - KR07 µPD78F9801 4.2 Non-Port Pins Pin Name I/O Function When Reset Also Used as INTP0 Input External interrupt request input for which effective edges (rising and/or falling edges) can be specified Input P26/TI01/TO01 KR00 - KR07 Input Input for detecting key return signals Input P40-P47 REGC - - Internally generated power supply for driving USB driver/receiver. Connect this pin to VSS through a 220-Ω resistor and a 0.1-µF capacitor. - RESET Input System reset input Input - SCK10 I/O Serial clock input/output for serial interface Input P20 SI10 Input Serial data input for serial interface Input P22 SO10 Output Serial data output for serial interface Input P21 TI01 Input External count clock input to 8-bit timer/event counter 01 Input P26/INTP0/TO01 TO01 Output Timer output from 8-bit timer/event counter 01 Input P26/INTP0/TI01 USBDM I/O Serial data input/output (negative side) for USB function. The pull-up resistor (1.5 kΩ) for the USBDM pin must be connected to the REGC pin. Input - USBDP I/O Serial data input/output (positive side) for USB function Input - X1 Input Connected to crystal for system clock oscillator Input X2 - VDD0 - Positive supply voltage for ports - - VDD1 - Positive supply voltage for circuits other than ports - - VSS0 - Ground potential for ports - - VSS1 - Ground potential for circuits other than ports - - VPP - Flash memory programming mode setting. High-voltage application for program write/verify. Connect directly to VSS0 or VSS1 in normal operation mode. - - NC - Not internally connected. Leave this pin open. - - - Data Sheet U12626EJ2V0DS 11 µPD78F9801 4.3 Pin Input/Output Circuits and Handling of Unused Pins Table 4-1 lists the types of input/output circuits for each pin and explains how unused pins are handled. Figure 4-1 shows the configuration of each type of input/output circuit. Table 4-1. Type of Input/Output Circuit for Each Pin Pin Name P00-P07 I/O Circuit Type 5-R I/O I/O : Connect these pins separately to VDD0, VDD1, VSS0, or VSS1 via respective resistors. Output : Leave these pins open. Input P10-P17 P20/ SCK10 Recommended Connection of Unused Pins 8-C P21/SO10 P22/SI10 P23, P24 P25 8-F P26/INTP0/TI01/TO01 P40/ KR00 -P47/ KR07 8-C USBDM 24-A Connect this pin to the REGC pin. Connect this pin to VSS0 or VSS1 via resistors. USBDP RESET 2 VPP - - Connect this pin directly to VSS0 or VSS1. NC - - Leave this pin open. REGC - - Connect this pin to the USBDM pin. 12 Input - Data Sheet U12626EJ2V0DS µPD78F9801 Figure 4-1. Pin Input/Output Circuits Type 8-F Type 2 VDD0 Pull-up enable P-ch cut IN P-ch VDD0 Output data P-ch IN/OUT Schmitt trigger input with hysteresis Output disable N-ch VSS0 Type 5-R Pull-up enable P-ch cut Type 24-A VDD0 P-ch VREG VDD0 Output data TXDXP P-ch P-ch IN/OUT RXDX IN/OUT TXDXN Output disable N-ch N-ch VSS0 VSS0 Input enable Type 8-C VDD0 Pull-up enable P-ch VDD0 Output data P-ch IN/OUT Output disable N-ch VSS0 Data Sheet U12626EJ2V0DS 13 µPD78F9801 5. MEMORY SPACE Figure 5-1 shows the memory map of the µPD78F9801. Figure 5-1. Memory Map FFFFH Special function register 256 × 8 bits FF00H FEFFH Internal high-speed RAM 256 × 8 bits FE00H FDFFH Data memory space Unusable 3FFFH 4000H 3FFFH Program area Program memory space Flash memory 16,384 × 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 001AH 0019H Vector table area 0000H 14 0000H Data Sheet U12626EJ2V0DS µPD78F9801 6. FLASH MEMORY PROGRAMMING The on-chip program memory in the µPD78F9801 is a flash memory. The flash memory can be written with the µPD78F9801 mounted on the target system (on-board). Connect the dedicated flash programmer (Flashpro III (model number: FL-PR3, PG-FP3)) to the host machine and target system to write to the flash memory. Remark 6.1 FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd. Selecting Communication Mode The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 6-1. To select a communication mode, the format shown in Figure 6-1 is used. Each communication mode is selected by the number of VPP pulses shown in Table 6-1. Table 6-1. Communication Mode List Communication Mode Pins UsedNote 1 Number of VPP Pulses 3-wired serial I/O mode SCK10/P20 SO10/P21 SI10/P22 0 Pseudo 3-wire modeNote 2 P10 (Serial clock input) P11 (Serial data output) P12 (Serial data input) 12 Notes 1. When changed to flash programming mode, all pins unused for flash memory programming enter the same state as that immediately upon a reset. Therefore, when the external device connected to the port does not recognize the state of the port immediately upon a reset, connect these pins to the VDD pin via a resistor or to the VSS0 or VSS1 pin via a resistor. 2. Serial transfer is performed by controlling a port by software. Caution Be sure to select a communication mode depending on the VPP pulse number shown in Table 6-1. Figure 6-1. Communication Mode Selection Format 10 V VPP VDD 1 2 n VSS VDD RESET VSS Data Sheet U12626EJ2V0DS 15 µPD78F9801 6.2 Function of Flash Memory Programming By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 6-2 shows the major functions of flash memory programming. Table 6-2. Functions of Flash Memory Programming Function Description Batch erase Erases all contents of memory. Batch blank check Checks erased state of entire memory. Data write Writes to flash memory based on write start address and number of data written (number of bytes). Batch verify Compares all contents of memory with input data. 6.3 Flashpro III Connection How the Flashpro III is connected to the µPD78F9801 differs depending on the communication mode (3-wired serial I/O or pseudo 3-wire mode). Figures 6-2 and 6-3 show the connection in the respective mode. Figure 6-2. Flashpro III Connection in 3-Wired Serial I/O Mode µ PD78F9801 Flashpro III VPPnNote 1 VPP VDD VDD0, VDD1 RESET RESET CLKNote 2 X1 SCK SCK10 SO SI10 SI SO10 VSS0, VSS1 GND Notes 1. n = 1, 2 2. Connect the CLK pin when the system clock is input from the Flashpro III. When the resonator has already been connected to the X1 pin, there is no need to connect the CLK pin to the X1 pin. 16 Data Sheet U12626EJ2V0DS µPD78F9801 Figure 6-3. Flashpro III Connection in Pseudo 3-Wire Mode µ PD78F9801 Flashpro III VPPnNote 1 VPP VDD VDD0, VDD1 RESET RESET CLKNote 2 X1 SCK P10 (Serial clock) SO P12 (Serial input) SI P11 (Serial output) GND VSS0, VSS1 Notes 1. n = 1, 2 2. Connect the CLK pin when the system clock is input from the Flashpro III. When the resonator has already been connected to the X1 pin, there is no need to connect the CLK pin to the X1 pin. Data Sheet U12626EJ2V0DS 17 µPD78F9801 6.4 Example of Settings for Flashpro III (PG-FP3) Set as follows when writing to flash memory using the Flashpro III (PG-FP3). <1> Download the parameter file. <2> Select the serial mode and the serial clock using the type command. <3> The following is a setting example using the PG-FP3. Table 6-3. Example Using PG-FP3 Communication Mode 3-wired serial I/O mode Number of VPP PulsesNote Setting Example Using PG-FP3 COMM PORT CPU CLK SIO ch-0 0 On target board In Flashpro Pseudo 3-wire mode On target board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz COMM PORT Port A CPU CLK On target board 12 In Flashpro On target board 4.1943 MHz SIO CLK 1 kHz In Flashpro 4.0 MHz SIO CLK 1 kHz Note The number of VPP pulses supplied from the Flashpro III during serial communication initialization. The pins to be used in communication are determined by this number of pulses. Remark 18 COMM PORT: Selection of serial port SIO CLK : Selection of serial clock frequency CPU CLK : Selection of CPU clock source to be input Data Sheet U12626EJ2V0DS µPD78F9801 7. INSTRUCTION SET OVERVIEW The instruction set for the µPD78F9801 is listed later. 7.1 Legend 7.1.1 Operand formats and descriptions The description made in the operand field of each instruction conforms to the operand format for the instructions listed below (the details conform with the assembly specification). If more than one operand format is listed for an instruction, one is selected. Uppercase letters, #, !, $, and a pair of [ and ] are used to specify keywords, which must be written exactly as they appear. The meanings of these special characters are as follows: • #: Immediate data specification • $: Relative address specification • !: Absolute address specification • [ and ]: Indirect address specification Immediate data should be described using appropriate values or labels. The specification of values and labels must be accompanied by #, !, $, or a pair of [ and ]. Operand registers, expressed as r or rp in the formats, can be described using both functional names (X, A, C, etc.) and absolute names (R0, R1, R2, and other parenthesized names listed in Table 7-1). Table 7-1. Operand Formats and Descriptions Format Description r rp sfr X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr saddrp FE20H to FF1FH: Immediate data or label FE20H to FF1FH: Immediate data or label (even addresses only) addr16 addr5 0000H to FFFFH: Immediate data or label (only even address for 16-bit data transfer instructions) 0040H to 007FH: Immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label Data Sheet U12626EJ2V0DS 19 µPD78F9801 7.1.2 Descriptions of the operation field A : A register (8-bit accumulator) X : X register B : B register C : C register D : D register E : E register H : H register L : L register AX : AX register pair (16-bit accumulator) BC : BC register pair DE : DE register pair HL : HL register pair PC : Program counter SP : Stack pointer PSW : Program status word CY : Carry flag AC : Auxiliary carry flag Z : Zero flag IE : Interrupt request enable flag NMIS : Flag to indicate that a nonmaskable interrupt is being handled () : Contents of a memory location indicated by a parenthesized address or register name XH, XL : Upper and lower 8 bits of a 16-bit register ∧ : Logical product (AND) ∨ ∨ : Logical sum (OR) : Inverted data : Exclusive OR addr16 : 16-bit immediate data or label jdisp8 : Signed 8-bit data (displacement value) 7.1.3 Description of the flag operation field (Blank) : No change 20 0 : To be cleared to 0 1 : To be set to 1 × : To be set or cleared according to the result R : To be restored to the previous value Data Sheet U12626EJ2V0DS µPD78F9801 7.2 Operations Flag Mnemonic Operand Byte Clock Operation Z MOV XCH r, #byte 3 6 r ← byte saddr, #byte 3 6 (saddr) ← byte sfr, #byte 3 6 sfr ← byte A, r Note 1 2 4 A←r r, A Note 1 2 4 r←A A, saddr 2 4 A ← (saddr) saddr, A 2 4 (saddr) ← A A, sfr 2 4 A ← sfr sfr, A 2 4 sfr ← A A, !addr16 3 8 A ← (addr16) !addr16, A 3 8 (addr16) ← A PSW, #byte 3 6 PSW ← byte A, PSW 2 4 A ← PSW PSW, A 2 4 PSW ← A A, [DE] 1 6 A ← (DE) [DE], A 1 6 (DE) ← A A, [HL] 1 6 A ← (HL) [HL], A 1 6 (HL) ← A A, [HL + byte] 2 6 A ← (HL + byte) [HL + byte], A 2 6 (HL + byte) ← A A, X 1 4 A↔X 2 6 A↔r A, saddr 2 6 A ↔ (saddr) A, sfr 2 6 A ↔ (sfr) A, [DE] 1 8 A ↔ (DE) A, [HL] 1 8 A ↔ (HL) A, [HL + byte] 2 8 A ↔ (HL + byte) rp, #word 3 6 rp ← word AX, saddrp 2 6 AX ← (saddrp) saddrp, AX 2 8 (saddrp) ← AX A, r MOVW Note 2 AX, rp Note 3 1 4 AX ← rp rp, AX Note 3 1 4 rp ← AX AC CY × × × × × × Notes 1. Except when r = A. 2. Except when r = A or X. 3. Only when rp = BC, DE, or HL. Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control register (PCC). Data Sheet U12626EJ2V0DS 21 µPD78F9801 Flag Mnemonic Operand Byte Clock Operation Z AC CY XCHW AX, rp 1 8 AX ↔ rp ADD A, #byte 2 4 A, CY ← A + byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte × × × A, r 2 4 A, CY ← A + r × × × ADDC SUB SUBC AND Note A, saddr 2 4 A, CY ← A + (saddr) × × × A, !addr16 3 8 A, CY ← A + (addr16) × × × A, [HL] 1 6 A, CY ← A + (HL) × × × A, [HL + byte] 2 6 A, CY ← A + (HL + byte) × × × A, #byte 2 4 A, CY ← A + byte + CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY × × × A, r 2 4 A, CY ← A + r + CY × × × A, saddr 2 4 A, CY ← A + (saddr) + CY × × × A, !addr16 3 8 A, CY ← A + (addr16) + CY × × × A, [HL] 1 6 A, CY ← A + (HL) + CY × × × A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY × × × A, #byte 2 4 A, CY ← A − byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) − byte × × × A, r 2 4 A, CY ← A − r × × × A, saddr 2 4 A, CY ← A − (saddr) × × × A, !addr16 3 8 A, CY ← A − (addr16) × × × A, [HL] 1 6 A, CY ← A − (HL) × × × A, [HL + byte] 2 6 A, CY ← A − (HL + byte) × × × A, #byte 2 4 A, CY ← A − byte − CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY × × × A, r 2 4 A, CY ← A − r − CY × × × A, saddr 2 4 A, CY ← A − (saddr) − CY × × × A, !addr16 3 8 A, CY ← A − (addr16) − CY × × × A, [HL] 1 6 A, CY ← A − (HL) − CY × × × × × A, [HL + byte] 2 6 A, CY ← A − (HL + byte) − CY × A, #byte 2 4 A ← A ∧ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte × A, r 2 4 A←A∧r × A, saddr 2 4 A ← A ∧ (saddr) × A, !addr16 3 8 A ← A ∧ (addr16) × A, [HL] 1 6 A ← A ∧ (HL) × A, [HL + byte] 2 6 A ← A ∧ (HL + byte) × Note Only when rp = BC, DE, or HL. Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control register (PCC). 22 Data Sheet U12626EJ2V0DS µPD78F9801 Flag Mnemonic Operand Byte Clock Operation Z AC CY A, #byte 2 4 A ← A ∨ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte × A, r 2 4 A←A∨r × A, saddr 2 4 A ← A ∨ (saddr) × A, !addr16 3 8 A ← A ∨ (addr16) × A, [HL] 1 6 A ← A ∨ (HL) × A, [HL + byte] 2 6 A ← A ∨ (HL + byte) × A, #byte 2 4 A ← A ∨ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte × A, r 2 4 A←A∨ r × A, saddr 2 4 A ← A ∨ (saddr) × A, !addr16 3 8 A ← A ∨ (addr16) × A, [HL] 1 6 A ← A ∨ (HL) × A, [HL + byte] 2 6 A ← A ∨ (HL + byte) × A, #byte 2 4 A − byte × × × saddr, #byte 3 6 (saddr) − byte × × × A, r 2 4 A−r × × × A, saddr 2 4 A − (saddr) × × × A, !addr16 3 8 A − (addr16) × × × A, [HL] 1 6 A − (HL) × × × A, [HL + byte] 2 6 A − (HL + byte) × × × ADDW AX, #word 3 6 AX, CY ← AX + word × × × SUBW AX, #word 3 6 AX, CY ← AX − word × × × CMPW AX, #word 3 6 AX − word × × × INC r 2 4 r←r+1 × × saddr 2 4 (saddr) ← (saddr) + 1 × × r 2 4 r←r−1 × × saddr 2 4 (saddr) ← (saddr) − 1 × × INCW rp 1 4 rp ← rp + 1 DECW rp 1 4 rp ← rp − 1 ROR A, 1 1 2 (CY, A7 ← A0, Am−1 ← Am) × 1 × ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 × RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am−1 ← Am) × 1 × ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 × OR XOR CMP DEC Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control register (PCC). Data Sheet U12626EJ2V0DS 23 µPD78F9801 Flag Mnemonic Operand Byte Clock Operation Z AC CY saddr. bit 3 6 (saddr. bit) ← 1 sfr. bit 3 6 sfr. bit ← 1 A. bit 2 4 A. bit ← 1 PSW. bit 3 6 PSW. bit ← 1 [HL]. bit 2 10 (HL). bit ← 1 saddr. bit 3 6 (saddr. bit) ← 0 sfr. bit 3 6 sfr. bit ← 0 A. bit 2 4 A. bit ← 0 PSW. bit 3 6 PSW. bit ← 0 [HL]. bit 2 10 (HL). bit ← 0 SET1 CY 1 2 CY ← 1 1 CLR1 CY 1 2 CY ← 0 0 NOT1 CY 1 2 CY ← CY × CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L, PC ← addr16, SP ← SP − 2 CALLT [addr5] 1 8 (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1), PCL ← (00000000, addr5), SP ← SP − 2 RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2 RETI 1 8 PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0 PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1 rp 1 4 (SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2 PSW 1 4 PSW ← (SP), SP ← SP + 1 rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2 SP, AX 2 8 SP ← AX AX, SP 2 6 AX ← SP !addr16 3 6 PC ← addr16 $addr16 2 6 PC ← PC + 2 + jdisp8 AX 1 6 PCH ← A, PCL ← X SET1 CLR1 PUSH POP MOVW BR × × × × × × R R R R R R Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control register (PCC). 24 Data Sheet U12626EJ2V0DS µPD78F9801 Flag Mnemonic Operand Byte Clock Operation Z BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0 BT saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 1 A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 1 PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 1 saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 0 A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 0 PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 0 B, $addr16 2 6 B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0 C, $addr16 2 6 C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0 saddr, $addr16 3 8 (saddr) ← (saddr) − 1, then PC ← PC + 3 + jdisp8 if (saddr) ≠ 0 NOP 1 2 No Operation EI 3 6 IE ← 1 (Enable Interrupt) DI 3 6 IE ← 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode BF DBNZ AC CY Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control register (PCC). Data Sheet U12626EJ2V0DS 25 µPD78F9801 8. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Supply voltage Symbol Conditions Rated Value Unit VDD -0.3 to +6.5 V VPP -0.3 to +10.5 V Input voltage VI -0.3 to VDD + 0.3 V Output voltage VO -0.3 to VDD + 0.3 V Output high current IOH Each pin -10 mA Total for all pins -30 mA Each pin 30 mA Total for all pins 160 mA -40 to +85 °C 10 to 40 °C -40 to +125 °C Output low current Operating ambient temperature IOL TA In normal operation mode During flash memory programming Storage temperature Caution Tstg Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark The characteristics of a dual-function pin do not differ between the port function and the secondary function, unless otherwise stated. 26 Data Sheet U12626EJ2V0DS µPD78F9801 CHARACTERISTICS OF THE SYSTEM CLOCK OSCILLATION CIRCUIT (TA = -40 to +85 °C, VDD = 4.0 to 5.5 V) Recommended Circuit Resonator Crystal VPP X1 C1 External clock X1 Parameter Conditions MIN. TYP. MAX. Unit 6.0 6.0 6.0 MHz 10 ms 6.0 MHz 83 ns Oscillator frequency (fX)Note 1 X2 Oscillation settling timeNote 2 C2 X2 X1 input frequency (fX)Note 1 6.0 X1 input high/low level width (tXH, tXL) 71 OPEN 6.0 Notes 1. Only the characteristics of the oscillator are indicated. See the description of the AC characteristics for the instruction execution time. 2. Time required for oscillation to settle once a reset sequence ends or STOP mode is deselected. Use a resonator that can settle oscillation before the oscillation settling time expires. Caution When using the system clock oscillator, observe the following conditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. • Keep the wiring as short as possible. • Do not allow signal wires to cross one another. • Keep the wiring away from wires that carry a high, non-stable current. • Keep the grounding point of the capacitors at the same level as VSS0. • Do not connect the grounding point to a grounding wire that carries a high current. • Do not extract a signal from the oscillator. FLASH MEMORY WRITE/DELETE CHARACTERISTICS (TA = 10 to 40 °C, VDD = 4.0 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note mA Write current (VDD pin) IDDW When VPP supply voltage = VPP1 (in 6.0-MHz operation mode) Write current (VPP pin) IPPW When VPP supply voltage = VPP1 7.5 mA Delete current (VDD pin) IDDE When VPP supply voltage = VPP1 (in 6.0-MHz operation mode) 18Note mA Delete current (VPP pin) IPPE When VPP supply voltage = VPP1 100 mA Unit delete time ter 1 s Total delete time tera Write count VPP supply voltage 18 1 1 Delete/write are regarded as 1 cycle. VPP0 In normal operation VPP1 During flash memory programming 0 9.7 10.0 20 s 1 Times 0.2VDD V 10.3 V Note The current flowing to the ports (including the current flowing through the on-chip pull-up resistors) is not included. Data Sheet U12626EJ2V0DS 27 µPD78F9801 DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 4.0 to 5.5 V) Parameter Symbol MAX. Unit Each pin Conditions MIN. TYP. -1 mA Total for all pins -15 mA Each pin 10 mA 80 mA VDD V Output high current IOH Output low current IOL Input high voltage VIH1 P00-P07, P10-P17 0.7VDD VIH2 RESET, P20-P26, P40-P47 0.8VDD VDD V VIH3 X1 VDD - 0.1 VDD V VIH4 USBDM, USBDP TA = 0 to +70 °C 2.0 3.6 V VIL1 P00-P07, P10-P17 0 0.3VDD V VIL2 RESET, P20, P22, P40-P47 0 0.2VDD V VIL3 X1 0 0.1 V VIL4 USBDM, USBDP TA = 0 to +70 °C 0 0.8 V VOH1 Pins other than USBDM and IO = -1 mA USBDP VOH2 USBDM, USBDP TA = 0 to +70 °C, RL = 15 kΩ (connected to VSS)Note 1 VOL1 Pins other than USBDM and IO = 10 mA USBDP 1.0 V VOL2 USBDM, USBDP TA = 0 to +70 °C, RL = 15 kΩ (connected to VDD)Note 1 0.3 V ILIH1 Pins other than X1, X2, USBDM, and USBDP VI = VDD 3 µA Total for all pins Input low voltage Output high voltage Output low voltage High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current Software pull-up resistor Regulator output voltage Supply currentNote 2 VDD - 1.0 V 2.8 V ILIH2 X1, X2 VI = VDD 20 ILIH3 USBDM, USBDP TA = 0 to +70 °C 0 V ≤ VI ≤ VREG 10 µA µA ILIL1 Pins other than X1, X2, USBDM, and USBDP VI = 0 V -3 µA ILIL2 X1, X2 VI = 0 V -20 ILIL3 USBDM, USBDP TA = 0 to +70 °C 0 V ≤ VI ≤ VREG -10 µA µA ILOH VO = 0 V 3 µA ILOL VO = 0 V -3 µA R VI = 0 V 50 100 200 kΩ VREG IO = 0 to -3 mA 3.0 3.3 3.6 V IDD1 6.0-MHz crystal oscillation (operating mode)Note 3 5.0 10.0 mA IDD2 6.0-MHz crystal oscillation (HALT mode)Note 3 1.5 3.5 mA IDD3 STOP mode When the USB function is disabled 10 30 µA When the USB function is enabled (TA = 0 to +70 °C) 50 100 µA Notes 1. RL is a resistor connected to a bus line. 2. The power supply current does not include the current flowing through the on-chip pull-up resistor. 3. During high-speed mode operation (when the processor clock control register (PCC) is cleared to 00H) Remark The characteristics of a dual-function pin do not differ between the port function and the secondary function, unless otherwise stated. 28 Data Sheet U12626EJ2V0DS µPD78F9801 AC CHARACTERISTICS (1) Basic operations (TA = -40 to +85 °C, VDD = 4.0 to 5.5 V) Parameter Symbol Cycle time (minimum TCY Conditions MIN. TYP. MAX. Unit When PCC = 00H (fX = 6.0 MHz) 0.333 0.333 0.333 µs When PCC = 02H (fX = 6.0 MHz) 1.333 1.333 1.333 µs 4.0 MHz instruction execution time) TI01 input frequency fTI 0 TI01 input high/low tTIH, tTIL level width 0.1 µs Interrupt input high/low level width tINTH, tINTL INTP0 10 µs RESET input low tRSL 10 µs level width (2) Serial interface (a) USB function (TA = 0 to +70 °C, VDD = 4.0 to 5.5 V) Parameter USBDM and USBDP rise time Symbol tR Conditions Note CL = 50 pF MIN. 300 Note CL = 50 pF tR and tF matching tRFM Differential output signal cross-over point 75 VCRS Data transfer rate tDRATE When the microcontroller operates at the system clock (fX) of 6.0 MHz 1.5 Transmission differential signal jitter tUDJ1 Upon transferring the next bit tUDJ2 Upon transferring the bit following the next bit Transmission EOP tEOPT1 width tEOPR1 EOP width to be eliminated tEOPR2 EOP width to be detected tURES1 USB reset width to be eliminated tURES2 USB reset width to be detected ns ns CL = 350 pFNote tR/tF Unit ns CL = 350 pF tF Reception USB reset width MAX. 75 Note USBDM and USBDP fall time Reception EOP width TYP. 300 ns 80 120 % 1.3 2.0 V 1.5 1.5 Mbps -95 0 95 ns -150 0 150 ns 1.25 1.33 1.50 µs 300 µs µs 675 2.5 5.5 µs µs Note CL is the capacitance of the USBDM and USBDP output lines. Data Sheet U12626EJ2V0DS 29 µPD78F9801 (b) Three-wire serial I/O mode (TA = -40 to +85 °C, VDD = 4.0 to 5.5 V) (i) SCK10 ...Internal clock output (when fX = 6.0 MHz) Parameter SCK10 cycle time Symbol tKCY1 Conditions MIN. TYP. MAX. Unit =0 667 667 667 ns =1 1,333 1,333 1,333 ns =0 283 333 ns When TPS100Note 1 = 1 617 667 ns Note 1 Note 1 Note 1 When TPS100 When TPS100 SCK10 high/low tKH1, tKL1 When TPS100 level width SI10 setup time tSIK1 Relative to SCK10 ↑ tKSI1 Relative to SCK10 ↑ SI10 hold time Note 1 Note 1 When TPS100 When TPS100 SO10 output dalay tKSO1 150 ns =0 333 ns =1 667 ns Relative to SCK10 ↓, CL = 100 pF Note 2 0 200 ns MAX. Unit Notes 1. Bit 4 of serial operation mode register 10 (CSIM10) 2. CL is the capacitance of the SO output line. (ii) SCK10 ...External clock output Parameter Symbol Conditions MIN. TYP. SCK10 cycle time tKCY2 667 ns SCK10 high/low 283 ns level width tKH2, tKL2 SI10 setup time tSIK2 100 ns SI10 hold time tKSI2 333 ns SO10 output delay tKSO2 Relative to SCK10 ↓, CL = 100 pF Note Note CL is the capacitance of the SO output line. 30 Data Sheet U12626EJ2V0DS 0 250 ns µPD78F9801 AC TIMING MEASUREMENT POINTS (except the X1 input and USB function) 0.8VDD 0.8VDD Measurement points 0.2VDD 0.2VDD CLOCK TIMING 1/fX tXH tXL VIH3 (MIN.) X1 input VIL3 (MAX.) TI TIMING 1/fTI tTIL tTIH tINTL tINTH TI01 INTERRUPT INPUT TIMING INTP0 RESET INPUT TIMING tRSL RESET Data Sheet U12626EJ2V0DS 31 µPD78F9801 SERIAL TRANSFER TIMING USB Function: USBDM and USBDP rise/fall time 0.9VDD USBDM, USBDP 0.1VDD tR tF Transmission differential signal jitter 1,333 ns 667 ns Bit following the next bit Next bit USBDM, USBDP tUDJ2 tUDJ1 Differential output signal cross-over point, transmission EOP width, reception EOP width, and reception USB reset width USBDM, USBDP VCRS tEOPT1, tEOPRm, tURESm m = 1, 2 Three-Wire Serial I/O Mode: tKCYm tKLm tKHm 0.8VDD SCK10 0.2VDD tSIKm SI10 tKSIm Input data tKSOm SO10 Output data m = 1, 2 32 Data Sheet U12626EJ2V0DS µPD78F9801 DATA HOLD CHARACTERISTICS OF DATA MEMORY AT LOW VOLTAGE IN STOP MODE (TA = -40 to +85 °C) Item Symbol Conditions MIN. Data hold supply voltage VDDDR 4.0 Release signal set time tSREL 0 Oscillation settling timeNote 1 tWAIT Notes 1. TYP. MAX. Unit 5.5 V µs Release by RESET Release by interrupt request 215/fX ms Note 2 ms During the oscillation settling time, CPU operations are disabled to prevent them from becoming unstable upon the start of oscillation. 2. 12 15 17 2 /fX, 2 /fX, or 2 /fX can be selected according to the setting of bits 0 to 2 (OSTS0 to OSTS2) of the oscillation settling time selection register. Remark fX: System clock oscillation frequency DATA HOLD TIMING (STOP mode release by RESET ) Internal reset operation HALT mode STOP mode Operating mode Data hold mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA HOLD TIMING (standby release signal: STOP mode release by interrupt signal) HALT mode STOP mode Operating mode Data hold mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Data Sheet U12626EJ2V0DS 33 µPD78F9801 9. PACKAGE DRAWINGS 44 PIN PLASTIC QFP (10x10) A B detail of lead end 23 22 33 34 S P C T D R 12 11 44 1 L U Q F J G H I M K M N S S NOTE ITEM Each lead centerline is located within 0.16 mm of its true position (T.P.) at maximum material condition. A Data Sheet U12626EJ2V0DS 12.0±0.2 B 10.0±0.2 C 10.0±0.2 D 12.0±0.2 F 1.0 G 1.0 H 0.37 +0.08 −0.07 I 0.2 J 0.8 (T.P.) K 1.0±0.2 L 0.5 M 0.17 +0.03 −0.06 N 0.10 P Q 1.4±0.05 0.1±0.05 R 3° +4° −3° S 1.6 MAX. U 34 MILLIMETERS 0.6±0.15 S44GB-80-8ES-1 µPD78F9801 10. RECOMMENDED SOLDERING CONDITIONS The µPD78F9801 should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our sales representatives. Table 10-1. Surface Mounting Type Soldering Conditions µPD78F9801GB-8ES: 44-pin plastic QFP (10 x 10) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235 °C Duration: 30 sec. max. (at 210 °C or above) Maximum allowable number of reflow processes: 2 IR35-00-2 VPS Package peak temperature: 215 °C Duration: 40 sec. max. (at 200 °C or above) Maximum allowable number of reflow processes: 2 VP15-00-2 Wave soldering Solder bath temperature: 260 °C max. Duration: 10 sec. max. Number of times: Once Preliminary heat temperature: 120 °C max. (Package surface temperature) WS60-00-1 Partial heating method Terminal temperature: 300 °C max. Duration: 3 sec. max. (per device side) - Caution Use of more than one soldering method should be avoided (except for partial heating method). Data Sheet U12626EJ2V0DS 35 µPD78F9801 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for developing systems using the µPD78F9801. LANGUAGE PROCESSING SOFTWARE RA78K0SNotes 1, 2, 3 Assembler package common to the 78K/0S series Notes 1, 2, 3 C compiler package common to the 78K/0S series CC78K0S DF789801Notes 1, 2, 3 Device file for the µPD789800 sub-series CC78K0S-LNotes 1, 2, 3 C compiler library source file common to the 78K/0S series FLASH MEMORY WRITE TOOLS Dedicated flash writer Flashpro Ill (Model number: FL-PR3Note 4, PG-FP3) FA-44GB-8ESNote 4 Flash memory write adapter (GB-8ES type) DEBUGGING TOOLS (1/2) IE-78K0S-NS In-circuit Emulator In-circuit emulator for debugging hardware and software of application system using 78K/0S Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-78K0S-NS-A In-circuit Emulator A coverage function is added to the IE-78K0S-NS, and the tracer and timer functions are improved to enhance debugging. IE-70000-MC-PS-B AC Adapter This is the adapter for supplying power from outlet of 100 to 240 VAC. IE-70000-98-IF-C Interface Adapter This adapter is needed when PC-9800 series (excluding notebook models) is used as a host machine of IE-78K0S-NS. (Compatible with C bus) IE-70000-CD-IF-A PC Card Interface This PC card and interface cable are needed when a notebook-type personal computer is used as a host machine of IE-78K0S-NS. (Compatible with a PCMCIA socket) IE-70000-PC-IF-C Interface Adapter This adapter is needed when IBM PC/ATTM and compatibles are used as a host machine of IE-78K0S-NS. (Compatible with ISA bus) IE-70000-PCI-IF-A Interface Adapter This adapter is needed when a personal computer with a built-in PCI bus is used as a host machine of IE-78K0S-NS. IE-789801-NS-EM1 Emulation Board Emulation board for emulating the peripheral hardware inherent to the device. Used in combination with in-circuit emulator. TM Notes 1. Based on the PC-9800 series (Japanese Windows ) 2. Based on the IBM PC/AT and compatibles (Japanese/English Windows) 3. Based on the HP9000 series 700 TM TM TM (HP-UX ), and SPARCstation TM 4. Product manufactured by Naito Densei Machida Mfg. Co., Ltd. (045-475-4191). Remark 36 The RA78K0S and CC78K0S can be used in combination with the DF789801. Data Sheet U12626EJ2V0DS TM (SunOS , Solaris ) µPD78F9801 DEBUGGING TOOLS (2/2) NP-44GB-TQNote 1 Emulation Probe TGB-044SAPNote 2 Conversion Socket This probe is used to connect the in-circuit emulator to the target system and is designed for 44-pin plastic QFP. Used in combination with TGB-044SAP. This conversion socket connects the NP-44GB-TQ to the target system board designed to mount a 44-pin plastic QFP (GB-8ES type). SM78K0SNotes 3, 4 System simulator common to the 78K/0S series ID78K0S-NSNotes 3, 4 Integrated debugger common to the 78K/0S series Notes 3, 4 DF789801 Device file for the µPD789800 sub-series Notes 1. Product manufactured by Naito Densei Machida Mfg. Co., Ltd. (045-475-4191). Contact an NEC sales representative for purchase. 2. Product manufactured by TOKYO ELETEC Corporation For further information, consult: Tokyo Electronic Div. (TEL (03) 3820-7112), or Osaka Electronic Div. (TEL (06) 6244-6672) Daimaru Kogyo Corporation. 3. Based on the PC-9800 series (Japanese Windows) 4. Based on the IBM PC/AT and compatibles (Japanese/English Windows) Remark The SM78K0S can be used in combination with the DF789801. Data Sheet U12626EJ2V0DS 37 µPD78F9801 APPENDIX B RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µPD789800 Data Sheet U12627E µPD78F9801 Data Sheet This document µPD789800 Subseries User’s Manual U12978E 78K/0S Series User’s Manual, Instruction U11047E Documents Related to Development Tools (Software) (User’s Manuals) Document Name RA78K0S Assembler Package Document No. Operation U14876E Language U14877E Structured Assembly Language U11623E Operation U14871E Language U14872E SM78K0S, SM78K0 System Simulator Ver.2.10 or Later Operation (Windows Based) U14611E SM78K Series System Simulator Ver.2.10 or Later External Part User Open Interface U15006E Specifications ID78K0-NS, ID78K0S-NS Integrated Debugger Ver.2.20 or Later Operation (Windows Based) CC78K0S C Compiler Project Manager Ver.3.12 or Later (Windows Based) U14910E U14610E Documents Related To Development Tools (Hardware) (User’s Manual) Document Name Document No. IE-78K0S-NS In-circuit Emulator U13549E IE-78K0S-NS-A In-circuit Emulator U15207E IE-789801-NS-EM1 Emulation Board U13390E Documents Related to Flash Memory Writing Document Name PG-FP3 Flash Memory Programmer User’s Manual Caution U13502E The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 38 Document No. Data Sheet U12626EJ2V0DS µPD78F9801 Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U12626EJ2V0DS 39 µPD78F9801 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. FIP and EEPROM are trademarks of NEC Corporation. Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. 40 Data Sheet U12626EJ2V0DS µPD78F9801 [MEMO] Data Sheet U12626EJ2V0DS 41 µPD78F9801 [MEMO] 42 Data Sheet U12626EJ2V0DS µPD78F9801 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U12626EJ2V0DS 43 µPD78F9801 • The information in this document is current as of October, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4