DATA SHEET MOS INTEGRATED CIRCUIT µPD78011H, 78012H, 78013H, 78014H 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78011H, 78012H, 78013H, and 78014H are the products in the µPD78014H subseries within the 78K/0 series. Compared with the older µPD78018F subseries, this subseries reduces the EMI (Electro Magnetic Interface) noise generated from the microcontroller. Functions are described in detail in the following User's Manual, which should be read when carring out design work. µPD78014H Subseries User's Manual: Planned to publish 78K/0 Series User’s Manual – Instruction: IEU-1372 FEATURES • Low EMI noise model • Large on-chip ROM & RAM Item Product Name • • • • • • • Program Memory (ROM) µPD78011H 8K bytes µPD78012H 16K bytes µPD78013H 24K bytes µPD78014H 32K bytes Data Memory Internal HighSpeed RAM 512 bytes Internal Buffer RAM 32 bytes Package • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 14 mm) 1024 bytes • 64-pin plastic LQFP (12 × 12 mm) External memory expansion space : 64K bytes Instruction execution time can be varied from high-speed (0.4 µs) to ultra-low-speed (122 µs) I/O ports: 53 (N-ch open-drain : 4) 8-bit resolution A/D converter : 8 channels Serial interface : 2 channels Timer : 5 channels Supply voltage : VDD = 1.8 to 5.5 V APPLICATION FIELD Cellular phone, pager, VCR, audio, camera, home appliances, etc. The information in this document is subject to change without notice. Document No. U11898EJ1V0DS00 (1st edition) Date Published January 1997 N Printed in Japan © 1997 µPD78011H, 78012H, 78013H, 78014H ORDERING INFORMATION Part Number µPD78011HCW-××× µPD78011HGC-×××-AB8 µPD78011HGK-×××-8A8 µPD78012HCW-××× µPD78012HGC-×××-AB8 µPD78012HGK-×××-8A8 µPD78013HCW-××× µPD78013HGC-×××-AB8 µPD78013HGK-×××-8A8 µPD78014HCW-××× µPD78014HGC-×××-AB8 µPD78014HGK-×××-8A8 Remark ××× indicates ROM code No. 2 Package 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic shrink DIP (750 mil) QFP (14 × 14 mm) LQFP (12 × 12 mm) shrink DIP (750 mil) QFP (14 × 14 mm) LQFP (12 × 12 mm) shrink DIP (750 mil) QFP (14 × 14 mm) LQFP (12 × 12 mm) shrink DIP (750 mil) QFP (14 × 14 mm) LQFP (12 × 12 mm) µPD78011H, 78012H, 78013H, 78014H DEVELOPMENT OF 78K/0 SERIES The following products are available in the 78K/0 series. The parts numbers enclosed in a frame are subseries names. Products under mass production Products under development The Y subseries supports the I2C bus. For control applications µ PD78078Y µ PD78078 100 pins µ PD78070A 100 pins µ PD780018 Note 100 pins µ PD78070AY µ PD780018Y Note Adds timer to µ PD78054 and reinforces external interface function ROM-less model of µ PD78078 Reinforces serial I/O of µ PD78078 and limits functions 80 pins µ PD78058F µ PD78058FY Low EMI noise model of µ PD78054 80 pins µ PD78054 µ PD780034 µ PD78054Y µ PD780034Y Adds UART and D/A to µ PD78014 and reinforces I/O 64 pins 64 pins µ PD780024 µ PD780024Y Reinforces serial I/O of µ PD78018F. Low EMI noise model 64 pins µ PD780964 Reinforces A/D of µ PD780924 64 pins µ PD780924 UART as inverter control circuit. Low EMI noise model 64 pins µ PD78014H 64 pins µ PD78018F 64 pins µ PD78014 64 pins µ PD780001 64 pins µ PD78002 42/44 pins µ PD78083 Reinforces A/D of µ PD780024 Low EMI noise model of µ PD78018F µ PD78018FY µ PD78014Y Low voltage (1.8 V) model of µ PD78014 with many variations of ROM and RAM Adds A/D and 16-bit timer to µ PD78002 Adds A/D to µ PD78002 µ PD78002Y Basic subseries for control applications UART. Low voltage (1.8 V) model For FIPTM driving 78K/0 series 100 pins µ PD780208 80 pins µ PD78044F Adds 6-bit U/D counter to µ PD78024. Total display outputs : 34 pins 64 pins µ PD78024 Basic subseries for FIP driving. Total display outputs : 26 pins Reinforces I/O and FIP C/D of µ PD78044F. Total display outputs : 53 pins For LCD driving 100 pins µ PD780308 µ PD780308Y Reinforces SIO of µ PD78064 with expanded ROM and RAM 100 pins µ PD78064B µ PD78064 µ PD78064Y Basic subseries for LCD driving. UART 100 pins Low EMI noise model of µ PD78064 Supporting IEBusTM µ PD78098 80 pins Adds IEBus controller to µ PD78054 For LV 64 pins µ PD78P0914 PWM output, LV digital code decoder, and Hsync counter Note Under planning 3 µPD78011H, 78012H, 78013H, 78014H The major differences between the respective subseries are shown below. Functions Subseries For Control For FIP driving For LCD driving IEBus support For LV ROM Capacity µPD78078 µPD78070A µPD780018 32 K-60 K – 48 K-60 K µPD78058F µPD78054 µPD780034 µPD780024 16 K-60 K 8 K-32 K µPD780964 µPD780924 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 µPD780208 µPD78044F µPD78024 µPD780308 µPD78064B µPD78064 µPD78098 8-bit 16-bit Watch WDT 4ch 1ch 1ch 1ch 8-bit 10-bit 8-bit A/D A/D D/A 8ch — 3ch 2ch 8 8 8 8 K-60 K K-32 K K K-16 K 32 16 24 48 K-60 K-40 K-32 K-60 K K K K 32 K 16 K-32 K 32 K-60 K µPD78P0914 32 K 2ch — 2ch Note 10-bit timer: 1 channel 4 Timer 2ch Note — — 8ch 8ch — — 8ch 8ch — — Serial Interface I/O 3ch (UART: 1ch) 88 61 2chs 88 (time-division 3-wire: 1 ch) 3ch (UART: 1ch) 69 pins pins pins VDD MIN. Value External Expansion 1.8 V 2.7 V pins 3chs 51 pins (UART: 1 ch, time-division 3-wire: 1 ch) 2ch (UART: 2ch) 47 pins 1ch 1ch 2ch 53 pins — 1ch pins pins pins pins pins pins pins 2.0 V 1.8 V 2.7 V 1.8 V 2.7 V 2ch 1ch — 1ch — 1ch 2ch 1ch 1ch 1ch — 8ch 8ch — — 1ch 8ch — — 2ch 1ch 1ch 1ch 8ch — 2ch 6ch — — 1ch 8ch — — 39 53 1ch (UART: 1ch) 33 2ch 74 68 54 3ch 57 (time-division UART: 1 ch) 2ch (UART: 1ch) — 1.8 V 2.7 V — — 1.8 V — 2.0 V 3ch (UART: 1ch) 69 pins 2.7 V 2ch 4.5 V 54 pins µPD78011H, 78012H, 78013H, 78014H OVERVIEW OF FUNCTION Item µPD78011H Product Name ROM High-speed RAM Buffer RAM Internal memory 8K bytes µPD78012H µPD78013H µPD78014H 16K bytes 24K bytes 32K bytes 512 bytes 1024 bytes 32 bytes Memory space 64K bytes General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Instruction cycle On-chip instruction execution time cycle modification function When main system clock selected When subsystem clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 10.0 MHz operation) 122 µs (at 32.768 kHz operation) Instruction set • • • • I/O ports Total • CMOS input • CMOS I/O • N-channel open-drain I/O (15 V withstand voltage) 16-bit operation Multiplication/division (8 bits × 8 bits,16 bits ÷ 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD correction, etc. : 53 : 02 : 47 : 04 A/D converter • 8-bit resolution × 8 channels • Operable over a wide power supply voltage range: AVDD = 1.8 to 5.5 V Serial interface • 3-wire serial I/O/SBI /2-wire serial I/O mode selectable: 1 channel • 3-wire serial I/O mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel Timer • • • • Timer output 3 (14-bit PWM output × 1) Clock output 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock: 10.0 MHz operation), 32.768 kHz (at subsystem clock: 32.768 kHz operation) Buzzer output 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: 10.0 MHz operation) 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer Vectored Maskable Internal : 8, External : 4 interrupt Non-maskable Internal :1 sources Software 1 Test input Internal Supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package : : : : 1 2 1 1 channel channels channel channel : 1, External : 1 • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 14 mm) • 64-pin plastic LQFP (12 × 12 mm) 5 µPD78011H, 78012H, 78013H, 78014H TABLE OF CONTENTS 1. PIN CONFIGURATION (Top View) ......................................................................................................... 7 2. BLOCK DIAGRAM ................................................................................................................................... 10 3. PIN FUNCTIONS ...................................................................................................................................... 11 3.1 PORT PINS ........................................................................................................................................................ 11 3.2 OTHER PORTS ................................................................................................................................................. 12 3.3 PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS ................................................ 14 4. MEMORY SPACE .................................................................................................................................... 16 5. PERIPHEL HARDWARE FUNCTION FEATURES ................................................................................ 17 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6. PORTS ............................................................................................................................................................... CLOCK GENERATOR ....................................................................................................................................... TIMER/EVENT COUNTER ................................................................................................................................ CLOCK OUTPUT CONTROL CIRCUIT ............................................................................................................ BUZZER OUTPUT CONTROL CIRCUIT ........................................................................................................... A/D CONVERTER .............................................................................................................................................. SERIAL INTERFACES ...................................................................................................................................... 17 18 19 21 21 22 23 INTERRUPT FUNCTIONS AND TEST FUNCTIONS .............................................................................. 25 6.1 INTERRUPT FUNCTIONS ................................................................................................................................. 25 6.2 TEST FUNCTIONS ............................................................................................................................................ 28 7. EXTERNAL DEVICE EXPANTION FUNCTIONS ................................................................................... 29 8. STANDBY FUNCTIONS ........................................................................................................................... 29 9. RESET FUNCTIONS ................................................................................................................................ 29 10. INSTRUCTION SET ................................................................................................................................. 30 11. ELECTRICAL SPECIFICATIONS ............................................................................................................ 33 12. PACKAGE DRAWINGS ........................................................................................................................... 57 13. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 60 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 62 APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 64 6 µPD78011H, 78012H, 78013H, 78014H 1. PIN CONFIGURATION (Top View) • 64-Pin Plastic Shrink DIP (750 mil) µPD78011HCW-×××, 78012HCW-×××, 78013HCW-×××, 78014HCW-××× P20/SI1 1 64 AV REF P21/SO1 2 63 AV DD P22/SCK1 3 62 P17/ANI7 P23/STB 4 61 P16/ANI6 P24/BUSY 5 60 P15/ANI5 P25/SI0/SB0 6 59 P14/ANI4 P26/SO0/SB1 7 58 P13/ANI3 P27/SCK0 8 57 P12/ANI2 P30/TO0 9 56 P11/ANI1 10 55 P10/ANI0 P32/TO2 11 54 AV SS P33/TI1 12 53 P04/XT1 P31/TO1 P34/TI2 13 52 XT2 P35/PCL 14 51 IC P36/BUZ 15 50 X1 P37 16 49 X2 V SS 17 48 V DD P40/AD0 18 47 P03/INTP3 P41/AD1 19 46 P02/INTP2 P42/AD2 20 45 P01/INTP1 P43/AD3 21 44 P00/INTP0/TI0 P44/AD4 22 43 RESET P45/AD5 23 42 P67/ASTB P46/AD6 24 41 P66/WAIT P47/AD7 25 40 P65/WR P50/A8 26 39 P64/RD P51/A9 27 38 P63 P52/A10 28 37 P62 P53/A11 29 36 P61 P54/A12 30 35 P60 P55/A13 31 34 P57/A15 V SS 32 33 P56/A14 Cautions 1. Always connect the IC (Internally Connected) pin to VSS directly. 2. The AVDD pin is multiplexed with an A/D converter power pin and a port power pin. In an application where the noise generated from the microcontroller must be reduced, connect the AVDD pin to a power supply of the same voltage as VDD. 3. The AVSS pin is multiplexed with an A/D converter ground pin and a port ground pin. In an application where the noise generated from the microcontroller must be reduced, connect AVSS pin to a ground line separate from VSS. 7 µPD78011H, 78012H, 78013H, 78014H • 64-Pin Plastic QFP (14 × 14 mm) µPD78011HGC-×××-AB8, 78012HGC-×××-AB8, 78013HGC-×××-AB8, 78014HGC-×××-AB8 P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P24/BUSY P23/STB P22/SCK1 P21/SO1 P20/SI1 AV REF AV DD P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 • 64-Pin Plastic LQFP (12 × 12 mm) µPD78011HGK-×××-8A8, 78012HGK-×××-8A8, 78013HGK-×××-8A8, 78014HGK-×××-8A8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 P30/TO0 1 P11/ANI1 P31/TO1 2 47 P10/ANI0 P32/TO2 3 46 AV SS P33/TI1 4 45 P04/XT1 P34/TI2 5 44 XT2 P35/PCL 6 43 IC P36/BUZ 7 42 X1 P37 8 41 X2 V SS P44/AD4 14 35 RESET P45/AD5 15 34 P67/ASTB P46/AD6 16 17 P66/WAIT 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 32 P65/WR P00/INTP0/TI0 P64/RD 36 P63 13 P62 P43/AD3 P61 P01/INTP1 P60 37 P57/A15 12 P56/A14 P42/AD2 V SS P02/INTP2 P55/A13 38 P54/A12 11 P53/A11 P41/AD1 P52/A10 P03/INTP3 P51/A9 V DD 39 P50/A8 40 10 P47/AD7 9 P40/AD0 Cautions 1. Always connect the IC (Internally Connected) pin to VSS directly. 2. The AVDD pin is multiplexed with an A/D converter power pin and a port power pin. In an application where the noise generated from the microcontroller must be reduced, connect the AVDD pin to a power supply of the same voltage as VDD. 3. The AVSS pin is multiplexed with an A/D converter ground pin and a port ground pin. In an application where the noise generated from the microcontroller must be reduced, connect AVSS pin to a ground line separate from VSS. 8 µPD78011H, 78012H, 78013H, 78014H A8-A15 AD0-AD7 ANI0-ANI7 : Address Bus : Address/Data Bus : Analog Input ASTB AVDD : Address Strobe : Analog Power Supply AVREF AVSS : Analog Reference Voltage : Analog Ground BUSY BUZ : Busy : Buzzer Clock IC INTP0-INTP3 : Internally Connected : Interrupt from Peripherals P00-P04 P10-P17 : Port 0 : Port 1 P20-P27 P30-P37 : Port 2 : Port 3 P40-P47 P50-P57 : Port 4 : Port 5 P60-P67 PCL : Port 6 : Programmable Clock RD RESET : Read Strobe : Reset SB0, SB1 SCK0, SCK1 : Serial Bus : Serial Clock SI0, SI1 SO0, SO1 : Serial Input : Serial Output STB TI0-TI2 : Strobe : Timer Input TO0-TO2 VDD : Timer Output : Power Supply VSS WAIT : Ground : Wait WR X1, X2 : Write Strobe : Crystal (Main System Clock) XT1, XT2 : Crystal (Subsystem Clock) 9 µPD78011H, 78012H, 78013H, 78014H 2. BLOCK DIAGRAM TO0/P30 TI0/INTP0/P00 P00 16-bit TIMER/ EVENT COUNTER PORT0 P01-P03 P04 TO1/P31 TI1/P33 TO2/P32 TI2/P34 8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2 WATCHDOG TIMER WATCH TIMER 78K/0 CPU CORE SI0/SB0/P25 SO0/SB1/P26 PORT1 P10-P17 PORT2 P20-P27 PORT3 P30-P37 PORT4 P40-P47 PORT5 P50-P57 PORT6 P60-P67 ROM SERIAL INTERFACE 0 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 AD0/P40AD7/P47 SERIAL INTERFACE 1 STB/P23 A8/P50A15/P57 BUSY/P24 RAM ANI0/P10ANI7/P17 EXTERNAL ACCESS RD/P64 WR/P65 WAIT/P66 A/D CONVERTER ASTB/P67 AVREF RESET INTP0/P00INTP3/P03 INTERRUPT CONTROL X1 SYSTEM CONTROL X2 XT1 BUZ/P36 BUZZER OUTPUT PCL/P35 CLOCK OUTPUT CONTROL XT2 VDD VSS AVDD AVSS IC Remark Internal ROM & RAM capacity varies depending on the product. 10 µPD78011H, 78012H, 78013H, 78014H 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Name I/O Input P00 Input/ output P01 P02 Function Port 0 5-bit I/O port On Reset DualFunction Pin Input only Input INTP0/TI0 Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input INTP1 INTP2 P03 INTP3 P04Note 1 Input Input only P10 to P17 Input/ output Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.Note 2 P20 Input/ output Port 2 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. P21 P22 P23 Input XT1 Input ANI0 to ANI7 Input SI1 SO1 SCK1 STB P24 BUSY P25 SI0/SB0 P26 SO0/SB1 P27 SCK0 Input/ output P30 P31 P32 P33 Port 3 8-bit input/output port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistor can be used by software. Input TO0 TO1 TO2 TI1 P34 TI2 P35 PCL P36 BUZ P37 — P40 to P47 Input/ output Port 4 8-bit input/output port. Input/output can be specified in 8-bit unit. When used as an input port, on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection. Input AD0 to AD7 Notes 1. When using the P04/XT1 pin as an input port pin, set bit 6 (FRC) of the processor clock control register (PCC) to 1 (do not use the internal feedback resistor of the subsystem clock oscillation circuit). 2. When using the P10/ANI0 through P17/ANI7 pins as the analog input pins of the A/D converter, the internal pull-up resistors are automatically not used. 11 µPD78011H, 78012H, 78013H, 78014H 3.1 PORT PINS (2/2) Pin Name I/O Function P50 to P57 Input/ output Port 5 8-bit input/output port. LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input P60 Input/ output Port 6 8-bit input/output port. Input/output can be specified bit-wise. Input P61 P62 N-ch open-drain input/output port. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. P63 On Reset P64 P66 A8 to A15 RD When used as an input port, on-chip pull-up resistor can be used by software. P65 DualFunction Pin WR WAIT P67 ASTB Caution Do not manipulate the pins multiplexed with a port pin as follows during A/D conversion; otherwise, the rated total error during A/D conversion may not be satisfied. <1> Rewriting the contents of the output latch when the pin is used as an output port pin. <2> Changing the output level of the pin used as an output pin even when the pin is not used as a port pin. 3.2 OTHER PORTS (1/2) Pin Name INTP0 I/O Input INTP1 INTP2 INTP3 Function External interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. On Reset DualFunction Pin Input P00/TI0 P01 P02 P03 Falling edge detection external interrupt request input. Serial interface serial data input. Input Serial interface serial data output. Input Input /output Serial interface serial data input/output. Input Input /output Serial interface serial clock input/output. STB Output Serial interface automatic transmit/receive strobe output. Input P23 BUSY Input Serial interface automatic transmit/receive busy input. Input P24 SI0 Input P20 SI1 SO0 Output SO1 SB0 SB1 SCK0 SCK1 12 P25/SB0 P26/SB1 P21 P25/SI0 P26/SO0 Input P27 P22 µPD78011H, 78012H, 78013H, 78014H 3.2 OTHER PORTS (2/2) Pin Name TI0 I/O Input Function External count clock input to 16-bit timer (TM0). TI1 External count clock input to 8-bit timer (TM1). TI2 External count clock input to 8-bit timer (TM2). TO0 Output 16-bit timer (TM0) output (multiplexed with 14-bit PWM output). TO1 8-bit timer (TM1) output. TO2 8-bit timer (TM2) output. PCL BUZ Output Output On Reset Input DualFunction Pin P00/INTP0 P33 P34 Input P30 P31 P32 Clock output (for main system clock, subsystem clock trimming). Input P35 Buzzer output. Input P36 P40 to P47 AD0 to AD7 Input /output Low-order address/data bus at external memory expansion. Input A8 to A15 Output High-order address bus at external memory expansion. Input P50 to P57 RD Output External memory read operation strobe signal output. Input P64 WR External memory write operation strobe signal output. P65 Input Wait insertion at external memory access. Input P66 ASTB Output Strobe output which latches the address information output at port 4 and port 5 to access external memory. Input P67 ANI0 to ANI7 Input A/D converter analog input. Input P10 to P17 AVREF Input A/D converter reference voltage input. — — AVDD — A/D converter analog power supply (multiplexed with a port power pin). — — AVSS — A/D converter ground potential (multiplexed with a port ground pin). — — RESET Input System reset input. — — X1 Input Main system clock oscillation crystal connection. — — X2 — — — XT1 Input Input P04 XT2 — — — VDD — Positive power supply (except port pins). — — VSS — Ground potential (except port pins). — — IC — Internal connection. Connected to VSS directly. — — WAIT Subsystem clock oscillation crystal connection. Cautions 1. The AVDD pin is multiplexed with an A/D converter power pin and a port power pin. In an application where the noise generated from the microcontroller must be reduced, connect the AVDD pin to a power supply of the same voltage as VDD. 2. The AVSS pin is multiplexed with an A/D converter ground pin and a port ground pin. In an application where the noise generated from the microcontroller must be reduced, connect AVSS pin to a ground line separate from VSS. 13 µPD78011H, 78012H, 78013H, 78014H 3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Figure 3-1. Table 3-1. Input/Output Circuit Type of Each Pin Pin Name Input/output Circuit Type I/O Recommended Connection when Not Used P00/INTP0/TI0 2 Input Connected to VSS . P01/INTP1 8-D Input/output Individually connected to VSS via resistor. P04/XT1 16 Input Connected to VDD or VSS. P10/ANI0 to P17/ANI7 11-C Input/output Individually connected to VDD or VSS via resisitor. P20/SI1 8-D P21/SO1 5-J P22/SCK1 8-D P23/STB 5-J P24/BUSY 8-D P25/SI0/SB0 10-C P02/INTP2 P03/INTP3 P26/SO0/SB1 P27/SCK0 P30/TO0 5-J P31/TO1 P32/TO2 P33/TI1 8-D P34/TI2 P35/PCL 5-J P36/BUZ P37 P40/AD0 to P47/AD7 5-O Individually connected to VDD via resistor. P50/A8 to P57/A15 5-J Individually connected to VDD or VSS via resistor. P60 to P63 13-I Individually connected to VDD via resistor. P64/RD 5-J Individually connected to VDD or VSS via resistor. P65/WR P66/WAIT P67/ASTB RESET 2 Input XT2 16 — AVREF — — Leave open. Connected to VSS . AVDD Connected to VDD . AVSS Connected to VSS . IC Connected to VSS directly. 14 µPD78011H, 78012H, 78013H, 78014H Figure 3-1. Pin Input/Output Circuits Type 10-C Type 2 AV DD pullup enable P-ch IN AVDD data P-ch IN / OUT Schmitt-Triggered Input with Hysteresis Characteristic open drain output disable N-ch AVSS Type 5-J Type 11-C AVDD pullup enable AV DD pullup enable P-ch P-ch AVDD P-ch data AVDD IN / OUT data output disable Comparator P-ch IN / OUT output disable N-ch N-ch P-ch AVSS + – N-ch AVSS VREF (Threshold Voltage) AVSS input enable input enable Type 5-O Type 13-I AV DD Mask Option AVDD pullup enable data P-ch data output disable AVDD IN / OUT N-ch AVSS AV DD P-ch IN / OUT output disable RD N-ch P-ch AVSS Middle-High Voltage Input Buffer Type 8-D Type 16 AVDD feedback cut-off pullup enable P-ch P-ch AV DD data P-ch IN / OUT output disable N-ch AVSS XT1 XT2 15 µPD78011H, 78012H, 78013H, 78014H 4. MEMORY SPACE The memory map of the µPD78011H, 78012H, 78013H, 78014H is shown in Figure 4-1. Figure 4-1. Memory Map FFFFH Special Function Registers (SFR) 256 × 8 Bits FF00H FEFFH General-Purpose Registers 32 × 8 Bits FEE0H FEDFH Internal High-Speed RAMNote mmmmH mmmmH–1 nnnnH Use Prohibited Program Area FAE0H Data Memory Space FADFH FAC0H FABFH 1000H 0FFFH Buffer RAM 32 × 8 Bits CALLF Entry Area Use Prohibited 0800H 07FFH FA80H FA7FH Program Area Program Memory Space nnnnH+1 nnnnH 0080H 007FH External Memory CALLT Table Area 0040H 003FH Internal ROMNote Vector Table Area 0000H 0000H Note Internal ROM and internal high-speed RAM capacities vary depending on the product (see the table below). Product Name 16 Intenal ROM End Address nnnnH µPD78011H 1FFFH µPD78012H 3FFFH µPD78013H 5FFFH µPD78014H 7FFFH Internal High-Speed RAM Start Address mmmmH FD00H FB00H µPD78011H, 78012H, 78013H, 78014H 5. PERIPHERAL HARDWARE FUNCTION FEATURES 5.1 PORTS The I/O port has the following three types • CMOS input (P00, P04) : • CMOS input/output (P01 to P03, port 1 to port 5, P64 to P67) • N-ch open-drain input/output(15V withstand voltage) (P60 to P63) : 47 : 4 Total 2 : 53 Table 5-1. Functions of Ports Port Name Port 0 Pin Name Function P00, P04 Dedicated Input port P01 to P03 Input/output ports. Input/output can be specified bit-wise. Port 1 P10 to P17 Port 2 P20 to P27 Port 3 P30 to P37 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P60 to P63 P64 to P67 When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified in 8-bit units. When used as an input port, pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. LED can be driven directly. N-ch open-drain input/output port. Input/output can be specified bit-wise. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. 17 µPD78011H, 78012H, 78013H, 78014H 5.2 CLOCK GENERATOR There are two types of clock generator: main system clock and subsystem clock. The instruction exection time can be changed. • 0.4µs/0.8µs/1.6µs/3.2µs/6.4µs (Main system clock: at 10.0 MHz operation) • 122µs (Subsystem clock: at 32.768 KHz operation) Figure 5-1. Clock Generator Block Diagram XT1/P04 XT2 Subsystem Clock Osicillator Watch Timer Clock Output Function fXT Prescaler X1 X2 Main System Clock Osicillator fX Clock to Peripheral Hardware Prescaler fX fX fX fX 2 22 23 24 STOP Selector Standby Control Circuit Wait Control Circuit INTP0 Sampling Clock 18 CPU Clock (fCPU) µPD78011H, 78012H, 78013H, 78014H 5.3 TIMER/EVENT COUNTER The following five channels are incorporated in the timer/event counter. • 16-bit timer/event counter : 1 channel • 8-bit timer/event counter • Watch timer : 2 channels : 1 channel • Watchdog timer : 1 channel Table 5-2. Types and Functions of Timer/Event Counter 16-bit Timer/Event Counter Type Functions 8-bit Timer/Event Counter Watch Timer Watchdog Timer Interval timer 1 channel 2 channels 1 channel 1 channel Externanal event counter 1 channel 2 channels – – Timer output 1 output 2 outputs – – PWM output 1 output – – – 1 input – – – 1 output 2 outputs – – Interrupt request 2 2 1 1 Test input – – 1 – Pulse width mesurement Sqare wave output Figure 5-2. 16-bit Timer/Enent Counter Block Diagram Internal Bus 16-Bit Compare Register (CR00) PWM Pulse Output Control Circuit Match fX/2 fX/22 fX/23 TI0/INTP0/P00 Selector Edge Detection Circuit INTTM0 Output Control Circuit TO0/P30 16-Bit Timer Register (TM0) Clear Selector INTP0 16-Bit Capture Register (CR01) Internal Bus 19 µPD78011H, 78012H, 78013H, 78014H Figure 5-3. 8-bit Timer/Enent Counter Block Diagram Internal Bus INTIM1 8-Bit Compare Register (CR10) 8-Bit Compare Register (CR20) Selector Match Output Control Circuit INTTM2 fX/22–fX/210 fX/212 TO2/P32 Selector 8-Bit Timer Register 1 (TM1) TI1/P33 Clear 8-Bit Timer Register 2 (TM2) Selector Clear fX/22–fX/210 Selector fX/212 Selector TI2/P34 Output Control Circuit TO1/P31 Internal Bus Figure 5-4. Watch Timer Block Diagram Selector fX/28 Selector fW Selector Prescaler fXT fW 24 fW 25 fW 26 fW 27 fW 28 INTWT fW 213 fW 29 Selector 20 5-Bit Counter fW 214 INTTM3 µPD78011H, 78012H, 78013H, 78014H Figure 5-5. Watchdog Timer Block Diagram fX 24 Prescaler fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 fX 212 INTWDT Maskable Interrupt Request Selector Control Circuit 8-Bit Counter RESET INTWDT Non-Maskable Interrupt Request 5.4 CLOCK OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for clock output. • 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation) • 32.768 kHz (Subsystem clock: at 32.768 kHz operation) Figure 5-6. Clock Output Control Block Diagram fX/23 fX/24 fX/25 Selector fX/26 Synchronization Circuit Output Control Circuit PCL/P35 fX/27 fX/28 fXT 5.5 BUZZER OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for buzzer output. • 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation) Figure 5-7. Buzzer Output Control Block Diagram fX/210 fX/211 Selector Output Control Circuit BUZ/P36 fX/212 21 µPD78011H, 78012H, 78013H, 78014H 5.6 A/D CONVERTER The A/D converter has on-chip eight 8-bit resolution channels. There are the following two method to start A/D conversion. • Hardware starting • Software starting Figure 5-8. A/D Converter Block Diagram Series Resistor String AVDD Sample & Hold Circuit ANI0/P10 AVREF ANI1/P11 Voltage Comparator ANI2/P12 ANI3/P13 Tap Selector Selector ANI4/P14 ANI5/P15 ANI6/P16 Succesive Approximation Register (SAR) ANI7/P17 INTP3/P03 Falling Edge Detector Control Circuit AVSS INTAD INTP3 A/D Conversion Result Register (ADCR) Internal Bus Caution Do not manipulate the pins multiplexed with a port pin (refer to 3.1 PORT PINS) during A/D conversion; otherwise, the rated total error during A/D conversion may not be satisfied. <1> Rewriting the contents of the output latch when the pin is used as an output port pin. <2> Changing the output level of the pin used as an output pin even when the pin is not used as a port pin. 22 µPD78011H, 78012H, 78013H, 78014H 5.7 SERIAL INTERFACES There are two on-chip clocked serial interfaces as follows. • Serial Interface channel 0 • Serial Interface channel 1 Table 5-3. Type and Function of Serial Interface Function Serial Interface Channel 0 Serial Interface Channel 1 3-wire serial I/O mode O (MSB/LSB-first switchable) O (MSB/LSB-first switchable) 3-wire serial I/O mode with automatic data transmit/ – O (MSB/LSB-first switchable) SBI (Serial Bus Interface) mode O (MSB-first) – 2-wire serial I/O mode O (MSB-first) – receive function Figure 5-9. Serial Interface Channel 0 Block Diagram Internal Bus SI0/SB0/P25 Selector SO0/SB1/P26 Selector SCK0/P27 Serial I/O Shift Register 0 (SIO0) Bus Release/Command/ Acknowledge Detection Circuit Serial Clock Counter Output Latch Busy/Acknowledge Output Circuit Interrupt Request Signal Generator INTCSI0 fx/22–fx/29 Serial Clock Control Circuit Selector TO2 23 µPD78011H, 78012H, 78013H, 78014H Figure 5-10. Serial Interface Channel 1 Block Diagram Internal Bus Automatic Data Transmit/ Receive Address Pointer (ADTP) SI1/P20 Buffer RAM Serial I/O Shift Register 1 (SIO1) SO1/P21 STB/P23 BUSY/P24 SCK/P22 Handshake Control Circuit Serial Clock Counter Interrupt Request Signal Generator INTCSI1 fX/22 – fX/29 Serial Clock Control Circuit 24 Selector TO2 µPD78011H, 78012H, 78013FH, 78014H 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 INTERRUPT FUNCTIONS There are the 14 interrupt sources of 3 different kind as shown below. • Non-maskable : • Maskable • Software : 12 : 1 1 Table 6-1. Interrupt Source List Interrupt Type Default Priority Note 1 Interrupt Source Name Trigger Non-maskable ––– INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (with interval timer mode selected) 1 INTP0 2 Software Pin input edge detection Internal/ External Vector Table Address Basic Configuratin Type Note 2 Internal 0004H (A) (B) 0006H (C) INTP1 0008H (D) 3 INTP2 000AH 4 INTP3 000CH 5 INTCSI0 Serial interface channel 0 transfer end 6 INTCSI1 Serial interface channel 1 transfer end 0010H 7 INTTM3 Reference time interval signal from watch timer 0012H 8 INTTM0 16 bit timer/event counter match signal generation 0014H 9 INTTM1 8-bit timer/event counter 1 match signal generation 0016H 10 INTTM2 8-bit timer/event counter 2 match signal generation 0018H 11 INTAD A/D converter conversion end 001AH ––– BRK BRK instruction execution External Internal – 000EH 003EH (B) (E) Notes 1. The default pririty is the priority applicable when more than one maskable interrupt is generated. 0 is the highest priority and 11, the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) on the next page. 25 µPD78011H, 78012H, 78013H, 78014H Figure 6-1. Basic Interrupt Function Configuration (1/2) (A) Internal Non-Maskable Interrupt Internal Bus Interrupt Request Vector Table Address Generator Priority Control Circuit Standby Release Signal (B) Internal Maskable Interrupt Internal Bus MK Interrupt Request PR IE ISP Vector Table Address Generator Priority Control Circuit IF Standby Release Signal (C) External Maskable Interrupt (INTP0) Internal Bus Sampling Clock Select Register (SCS) Interrupt Request Sampling Clock External Interrupt Mode Register (INTM0) Edge Detector MK IF IE PR Priority Control Circuit ISP Vector Table Address Generator Standby Release Signal 26 µPD78011H, 78012H, 78013FH, 78014H Figure 6-1. Basic Interrupt Function Configuration (2/2) (D) External Maskable Interrupt (Except INTP0) Internal Bus External Interrupt Mode Register (INTM0) Interrupt Request Edge Detector MK IE PR Priority Control Circuit IF ISP Vector Table Address Generator Standby Release Signal (E) Software Interrupt Internal Bus Interrupt Request IF IE ISP MK PR Priority Control Circuit Vector Table Address Generator : Interrupt request flag : Interrupt enable flag : In-service priority flag : Interrupt mask flag : Priority spcification flag 27 µPD78011H, 78012H, 78013H, 78014H 6.2 TEST FUNCTIONS There are two test functions as shown in Table 6-2. Table 6-2. Test Source List Test Source Internal/External Name Trigger INTWT Watch timer overflow Internal INTPT4 Port 4 falling edge detection External Figure 6-2. Test Function Basic Configuration Internal Bus MK Test Input IF : Test input flag MK : Test mask flag 28 IF Standby Release Signal µPD78011H, 78012H, 78013FH, 78014H 7. EXTERNAL DEVICE EXPANSION FUNCTIONS The external device expansion function is used to connect external devices to areas other than the internal ROM, RAM and SFR. Ports 4 to 6 are used for connection with external devices. 8. STANDBY FUNCTIONS There are the following two standby functions to reduce the current dissipation. • HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operat ing mode. • STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates withultra-low power consumption using only the subsystem clock. Figure 8-1. Standby Functions CSS=1 Main System Clock Operation Interrupt Request CSS=0 HALT Instruction STOP Instruction Interrupt Request STOP Mode (Main system clock oscillation stopped) HALT Mode (Clock supply to CPU is stopped, oscillation) Subsystem Clock OperationNote Interrupt Request HALT Instruction HALT ModeNote (Clock supply to CPU is stopped, oscillation) Note The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set the MCC to stop the main system clock. The STOP instruction cannot be used. Caution When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program by the program. 9. RESET FUNCTIONS There are the following two reset methods. • External reset input by RESET pin. • Internal reset by watchdog timer runaway time detection. 29 µPD78011H, 78012H, 78013H, 78014H 10. INSTRUCTION SET (1) 8-Bit Instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ 2nd Operand #byte A r Note sfr saddr !addr16 MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP PSW [DE] [HL] MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV [HL+byte] [HL+B] $adder16 [HL+C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP 1 None ROR ROL RORC ROLC MOV ADD ADDC SUB SUBC AND OR XOR INC DEC CMP r1 DBNZ sfr MOV sadder MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !adder16 PSW MOV DBNZ INC DEC MOV MOV MOV [DE] MOV [HL] MOV [HL+byte] [HL+B] [HL+C] MOV PUSH POP ROR4 ROL4 X MULU C DIVUW Note Except r=A 30 µPD78011H, 78012H, 78013FH, 78014H (2) 16-Bit Instruction MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand 1st Operand AX #byte AX rp Note ADDW MOVW SUBW XCHW saddrp MOVW !addr16 MOVW SP MOVW None MOVW CMPW rp MOVW MOVWNote sfrp MOVW MOVW sadderp MOVW MOVW MOVW MOVW !adder16 SP INCW, DECW PUSH, POP MOVW Note Only when rp=BC, DE, HL. (3) Bit Manipulation Instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR 2nd Operand A.bit sfr.bit saddr.bit PWS.bit [HL].bit CY $addr16 None 1st Operand A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 31 µPD78011H, 78012H, 78013H, 78014H (4) Call Instruction/Branch Instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd Operand AX !addr16 !addr11 [addr5] $addr16 1st Operand Basic instruction Compound instruction BR CALL, BR CALLF CALLT BR, BC, BNC, BZ, BNZ BT, BF, BTCLR, DBNZ (5) Other Instruction ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 32 µPD78011H, 78012H, 78013H, 78014H 11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C) Parameter Supply voltage Input voltage Symbol Rating Unit VDD –0.3 to + 7.0 V AVDD –0.3 to VDD + 0.3 V AVREF –0.3 to VDD + 0.3 V AVSS –0.3 to + 0.3 V –0.3 to VDD + 0.3 V –0.3 to +16 V –0.3 to VDD + 0.3 V AV SS –0.3 to AVREF + 0.3 V 1 pin –10 mA P10 to P17, P20 to P27, P30 to P37 total –15 mA P01 to P03, P40 to P47, P50 to P57, P60 to P67 total –15 mA Peak value 30 mA rms 15 mA Peak value 100 mA rms 70 mA 100 mA VI1 Test Conditions P00 to P04, P10 to P17, P20 to P27, P30 to P37 P40 toP47, P50 to P57, P64 to P67, X1, X2, XT2 VI2 Output voltage VO Analog input voltage VAN Output current high IOH Output current low P60 to P67 P10 to P17 1 pin P40 to P47, P50 to P55 total IOLNote Open-drain Analog input pin P01 to P03, P56, P57, Peak value P60 to P67 total rms 70 mA P01 to P03, Peak value 50 mA P64 to P67 total rms 20 mA P10 to P17, P20 to P27, P30 to P37 Peak value 50 mA total 20 mA rms Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note rms should be calculated as follows: [rms] = [peak value] × √duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. 33 µPD78011H, 78012H, 78013H, 78014H Capacitance ( TA = 25 °C, VDD = VSS = 0 V ) Parameter Symbol Input capacitance CIN Test Conditions MIN. TYP. f = 1 MHz Unmeasured pins returned to 0 V I/O capacitance MAX. Unit 15 pF 15 pF 20 pF P01 to P03, P10 to P17, f = 1 MHz Unmeasured P20 to P27, P30 toP37, CIO pins returned to 0 V P40 toP47, P50 to P57, P64 to P67 P60 to P63 Remark The characteristics of a dual-function pin and a port pin are the same unless specified otherwise. Main System Clock Oscillation Circuit Characteristics ( TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Resonator Ceramic resonator Recommended Circuit X1 X2 IC Parameter Oscillator frequency (fX) Note 1 R1 C1 Crystal resonator X1 C1 C2 X2 IC C2 Test Conditions MIN. TYP. MAX. 2.7 V ≤ VDD ≤ 5.5 V 1 10 1.8 V ≤ VDD < 2.7 V 1 5 Unit MHz Oscillation stabilization time Note 2 After VDD reaches oscillator voltage range MIN. Oscillator frequency (fX) Note 1 2.7 V ≤ VDD ≤ 5.5 V 1 10 1.8 V ≤ VDD < 2.7 V 1 5 Oscillation stabilization time Note 2 VDD = 4.5 to 5.5 V 4 ms MHz 10 ms 30 External clock X1 X2 µ PD74HCU04 X1 input frequency (fX) Note 1 1.0 10.0 MHz X1 input high/low level width (tXH , tXL) 45 500 ns Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wirinin the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ● Wiring should be as short as possible. ● Wiring should not cross other signal lines. ● Wiring should not be placed close to a varying high current. ● The potential of the oscillator capacitor ground should be the same as VSS. ● Do not ground wiring to a ground pattern in which a high current flows. ● Do not fetch a signal from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. 34 µPD78011H, 78012H, 78013H, 78014H Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Resonator Crystal resonator Recommended Circuit XT1 XT2 IC Parameter Test Conditions Oscillator frequency (fXT) Note 1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 R2 C3 External clock XT1 C4 XT2 Oscillation stabilization time Note 2 V DD = 4.5 to 5.5 V s 10 XT1 input frequency (fXT) Note 1 32 100 kHz XT1 input high/low level width (tXTH , tXTL) 5 15 µs Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN. Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ● Wiring should be as short as possible. ● Wiring should not cross other signal lines. ● Wiring should not be placed close to a varying high current. ● The potential of the oscillator capacitor ground should be the same as VSS. ● Do not ground wiring to a ground pattern in which a high current flows. ● Do not fetch a signal from the oscillator. 2. The subsystem clock oscillation circuit is a circuit with a low amplification level,more prone to misoperation due to noise than the main system clock. Particular care is therefore required with the wiring method when the subsystem clock is used. 35 µPD78011H, 78012H, 78013H, 78014H DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Input voltage Symbol VIH1 high Test Conditions MAX. Unit 0.7 VDD VDD V 0.8 VDD VDD V P00-P03, P20, P22, P24-P27, P33, VDD = 2.7 to 5.5 V 0.8 VDD VDD V P34, RESET 0.85 VDD VDD V VDD = 2.7 to 5.5 V 0.7 VDD 15 V 0.8 VDD 15 V VDD = 2.7 to 5.5 V VDD – 0.5 VDD V VDD – 0.2 VDD V P10-P17, P21, P23, P30-P32, VDD = 2.7 to 5.5 V MIN. TYP. P35-P37, P40-P47, P50-P57, P64-67 VIH2 VIH3 P60-P63 (N-ch open-drain) VIH4 VIH5 Input voltage VIL1 low X1, X2 4.5 V ≤ VDD ≤ 5.5 V 0.8 VDD VDD V 2.7 V ≤ VDD < 4.5 V 0.9 VDD VDD V 1.8 V ≤ VDD < 2.7 V Note 0.9 VDD VDD V 0 0.3 VDD V P64-67 0 0.2 VDD V P00-P03, P20, P22, P24-P27, P33, VDD = 2.7 to 5.5 V 0 0.2 VDD V XT1/P04, XT2 P10-P17, P21, P23, P30-P32, VDD = 2.7 to 5.5 V P35-P37, P40-P47, P50-P57, VIL2 P34, RESET VIL3 VIL4 VIL5 Output VOH1 voltage high Output VOL1 P60-P63 X1, X2 XT1/P04, XT2 0 0.15 VDD V 4.5 V ≤ VDD ≤ 5.5 V 0 0.3 VDD V 2.7 V ≤ VDD < 4.5 V 0 0.2 VDD V 0 0.1 VDD V 0 0.4 V 0 0.2 V 0 0.2 VDD V VDD = 2.7 to 5.5 V 4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD < 4.5 V 0 0.1 VDD V 1.8 V ≤ VDD < 2.7 V Note 0 0.1 VDD V VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V IOH = –100 µA VDD – 0.5 V P50 to P57, P60 to P63 voltage low VDD = 4.5 to 5.5 V, 0.4 2.0 V 0.4 V 0.2 VDD V 0.5 V IOL = 15 mA P01 to P03, P10 to P17, P20 to P27 VOL2 VDD = 4.5 to 5.5 V, P30 to P37, P40 to P47, P64 to P67 IOL = 1.6 mA SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, open-drain pulled-up (R = 1 KΩ) VOL3 Note When using XT1/P04 as P04, input the inverse of P04 to XT2 using an inverter. Remark 36 IOL = 400 µA The characteristics of a dual-function pin and a port pin are the same unless specified otherwise. µPD78011H, 78012H, 78013H, 78014H DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Symbol Input leakage ILIH1 Test Conditions MAX. Unit 3 µA X1, X2, XT1/P04, XT2 20 µA VIN = 15 V P60 to P63 80 µA VIN = 0 V P00 to P03, P10 to P17, –3 µA –20 µA –3 Note µA VOUT = VDD 3 µA VOUT = 0 V –3 µA VIN = VDD current high MIN. TYP. P00 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, RESET ILIH2 ILIH3 Input leakege ILIL1 current low P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, RESET ILIL2 X1, X2, XT1/P04, XT2 ILIL3 P60 to P63 Output leakage ILOH1 current high Output leakage ILOL current low Mask option R1 VIN = 0 V, P60 to P63 20 40 90 kΩ R2 VIN = 0 V, P01 to P03, P10 to P17, P20 to P27, P30 to P37, 15 40 90 kΩ pull-up resister Software pull-up resister P40 to P47, P50 to P57, P60 to P67 Note For P60-P63, if pull-up resistor is not provided (specifiable by mask option) a low-level input leak current of –200 µA (MAX.) flows only during the 3 clocks (no-wait time) after an instruction has been executed to read out port 6 (P6) or port mode register 6 (PM6). Outside the period of 3 clocks following execution a read-out instruction, the current is –3 µA (MAX.). Remark The characteristics of a dual-function pin and a port pin are the same unless specified otherwise. 37 µPD78011H, 78012H, 78013H, 78014H DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Supply current Symbol IDD1 Note 1 IDD2 IDD3 Test Conditions IDD5 IDD6 TYP. MAX. Unit 10.00 MHz crystal VDD = 5.0 V ± 10 % Note 2 9.0 18.0 mA oscillation operation mode VDD = 3.0 V ± 10 % Note 3 1.3 2.6 mA 10.00 MHz crystal VDD = 5.0 V ± 10 % Note 2 2.0 4.0 mA oscillation HALT mode VDD = 3.0 V ± 10 % Note 3 1.0 2.0 mA VDD = 5.0 V ± 10 % Note 3 60 120 µA VDD = 3.0 V ± 10 % Note 3 35 70 µA VDD = 2.0 V ± 10 % Note 4 24 48 µA 32.768 kHz crystal VDD = 5.0 V ± 10 % Note 3 25 50 µA oscillation HALT mode VDD = 3.0 V ± 10 % Note 3 5 15 µA VDD = 2.0 V ± 10 % Note 4 2 10 µA 1 30 µA 0.5 10 µA 0.3 10 µA 32.768 kHz crystal oscillation operation mode IDD4 MIN. Note 4 XT1 = VDD VDD = 5.0 V ± 10 % STOP mode when using feedback VDD = 3.0 V ± 10 % resistor VDD = 2.0 V ± 10 % XT1 = VDD VDD = 5.0 V ± 10 % 0.1 30 µA STOP mode when not using VDD = 3.0 V ± 10 % 0.05 10 µA feedback resistor VDD = 2.0 V ± 10 % 0.05 10 µA Note 4 Note 4 Notes 1. Current flowing into the VDD and AVDD pins. However, the current flowing into the A/D converter and internal pullup resistors is not included. 2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H) 3. When operating at low-speed mode (when the PCC is set to 04H) 4. When main system clock stopped. 38 µPD78011H, 78012H, 78013H, 78014H AC Characteristics (1) Basic Operation (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 3.5 V ≤ VDD ≤ 5.5 V 0.4 64 µs (Min. instruction 2.7 V ≤ VDD < 3.5 V 0.8 64 µs execution time) 1.8 V ≤ VDD < 2.7 V 2.0 64 µs 125 µs Cycle time TCY Operating on main system clock Operating on subsystem clock TI0 input frequency TI1, TI2 input 40 2/fsam+0.1 µs Note µs µs tTIH0 3.5 V ≤ VDD ≤ 5.5 V tTIL0 2.7 V ≤ VDD < 3.5 V 2/fsam+0.2 1.8 V ≤ VDD < 2.7 V 2/fsam+0.5 Note fTI1 VDD = 4.5 to 5.5 V frequency TI1, TI2 input 122 Note tTIH1 VDD = 4.5 to 5.5 V 0 4 MHz 0 275 kHz 100 ns 1.8 µs 3.5 V ≤ VDD ≤ 5.5 V 2/fsam+0.1 Note µs 2.7 V ≤ VDD < 3.5 V 2/fsam+0.2 Note µs 1.8 V ≤ VDD < 2.7 V Note µs high/low-level tTIL1 width Interrupt input tINTH high/low-level INTP0 tINTL width INTP1-INTP3, KR0-KR7 RESET low tRSL VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V level width 2/fsam+0.5 10 µs 20 µs 10 µs 20 µs Note In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of fsam is possible between fX/2N+1, fX/64 and fx/128 (when N= 0 to 4). 39 µPD78011H, 78012H, 78013H, 78014H TCY vs VDD (At main system clock operation) 60.0 Operation Guaranteed Range Cycle Time TCY [ µ S] 10.0 5.0 1.0 0.5 0.1 0 1.0 3.0 3.5 4.0 2.0 1.8 2.7 Supply voltage VDD [V] 40 5.0 5.5 6.0 µPD78011H, 78012H, 78013H, 78014H (2) Read/Write Operation (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.5tCY ns Address setup time tADS 0.5tCY–30 ns Address hold time tADH 50 ns Data input time from address Data input time from RD↓ tADD1 (2.5+2n)tCY–50 ns tADD2 (3+2n)tCY–100 ns tRDD1 (1+2n)tCY–25 ns (2.5+2n)tCY–100 ns tRDD2 Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5+2n)tCY–20 ns tRDL2 (2.5+2n) tCY–20 ns WAIT↓ input time from RD↓ tRDWT1 0.5tCY ns tRDWT2 1.5tCY ns WAIT↓ input time from WR↓ tWRWT 0.5tCY ns WAIT low-level width tWTL (0.5+2n)tCY+10 (2+2n)tCY ns Write data setup time tWDS 100 ns Write data hold time tWDH 20 ns WR low-level width tWRL1 (2.5+2n) tCY –20 ns RD↓ delay time from ASTB↓ tASTRD 0.5tCY–30 ns WR↓ delay time from ASTB↓ tASTWR 1.5tCY–30 ns ASTB↑ delay time from RD↑ in external fetch tRDAST tCY–10 tCY+40 ns Address hold time from RD↑ in external fetch tRDADH tCY tCY+50 ns Write data output time from RD↑ tRDWD 0.5tCY+5 0.5tCY+30 ns 0.5tCY+15 0.5tCY+90 ns 30 ns Load resistor ≥ 5 kΩ VDD = 4.5 to 5.5 V Write data output time from WR↓ tWRWD VDD = 4.5 to 5.5 V 5 15 90 ns Address hold time from WR↑ tWRADH VDD = 4.5 to 5.5 V tCY tCY+60 ns tCY tCY+100 ns RD↑ delay time from WAIT↑ tWTRD 0.5tCY 2.5tCY+80 ns WR↑ delay time from WAIT↑ tWTWR 0.5tCY 2.5tCY+80 ns Remarks 1. tCY = TCY/4 2. n indicates number of waits. 41 µPD78011H, 78012H, 78013H, 78014H (3) Serial Interface (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) (a) Serial Interface Channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output) Parameter SCK0 cycle time Symbol tKCY1 SCK0 high/low-level tKH1 width tKL1 SI0 setup time tSIK1 (to SCK0↑) SI0 hold time Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns tKCY1/2–50 ns VDD = 4.5 to 5.5 V tKCY1/2–100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.7 V ≤ VDD < 4.5 V 150 ns 2.0 V ≤ VDD < 2.7 V 300 ns 400 ns 400 ns tKSI1 (from SCK0↑) SO0 output delay time tKSO1 C = 100 pF Note 300 ns MAX. Unit from SCK0↓ Note C is the load capacitance of SCK0 and SO0 output line. (ii) 3-wire serial I/O mode (SCK0... External clock input) Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. TYP. 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns SCK0 high/low-level tKH2 4.5 V ≤ VDD ≤ 5.5 V 400 ns width tKL2 2.7 V ≤ VDD < 4.5 V 800 ns 2.0 V ≤ VDD < 2.7 V 1600 ns 2400 ns 100 ns 150 ns 400 ns SI0 setup time tSIK2 VDD = 2.0 to 5.5 V (to SCK0↑) SI0 hold time tKSI2 (from SCK0↑) SO0 output delay time tKSO2 C = 100 pF Note VDD = 2.0 to 5.5 V tR2 When external device tF2 expansion function is used from SCK0↓ SCK0 rise, fall time When external When 16-bit timer 300 ns 500 ns 160 ns 700 ns 1000 ns device expansion output function is function is not used used When 16-bit timer output function is not used Note C is the load capacitance of SO0 output line. 42 µPD78011H, 78012H, 78013H, 78014H (iii) SBI mode (SCK0... Internal clock output) Parameter SCK0 cycle time Symbol tKCY3 SCK0 high/low-level tKH3 width tKL3 SB0, SB1 setup time tSIK3 (to SCK0↑) SB0, SB1 hold time Test Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.0 V ≤ VDD < 4.5 V 3200 ns 4800 ns VDD = 4.5 to 6.0 V tKCY3/2–50 ns tKCY3/2–150 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.0 V ≤ VDD < 4.5 V 300 ns 400 ns tKCY3/2 ns tKSI3 (from SCK0↑) SB0, SB1output delay tKSO3 R = 1 kΩ, C = 100 pF Note time from SCK0↓ VDD = 4.5 to 5.5 V 0 250 ns 0 1000 ns SB0, SB1↓ from SCK0↑ tKSB tKCY3 ns SCK0↓ from SB0, SB1↓ tSBK tKCY3 ns SB0, SB1 high-level tSBH tKCY3 ns tSBL tKCY3 ns width SB0, SB1 low-level width Note R and C are the load resistors and load capacitance of the SB0, SB1 and SCK0 output line. 43 µPD78011H, 78012H, 78013H, 78014H (iv) SBI mode (SCK0... External clock input) Parameter SCK0 cycle time Symbol tKCY4 Test Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.0 V ≤ VDD < 4.5 V 3200 ns 4800 ns SCK0 high/low-level tKH4 4.5 V ≤ VDD ≤ 5.5 V 400 ns width tKL4 2.0 V ≤ VDD < 4.5 V 1600 ns 2400 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.0 V ≤ VDD < 4.5 V 300 ns 400 ns tKCY4/2 ns SB0, SB1 setup time tSIK4 (to SCK0↑) SB0, SB1 hold time tKSI4 (from SCK0↑) SB0, SB1 output delay tKSO4 time from SCK0↓ R = 1 kΩ, C = 100 pF VDD = 4.5 to 5.5 V Note 0 300 ns 0 1000 ns SB0, SB1↓ from SCK0↑ tKSB tKCY4 ns SCK0↓ from SB0, SB1↓ tSBK tKCY4 ns SB0, SB1 high-level tSBH tKCY4 ns tSBL tKCY4 ns width SB0, SB1 low-level width SCK0 rise, fall time tR4 When external device tF4 expansion function is used When external When 16-bit timer 160 ns 700 ns 1000 ns device expansion output function is function is not used used When 16-bit timer output function is not used Note R and C are the load resistors and load capacitance of the SB0 and SB1 output line. 44 µPD78011H, 78012H, 78013H, 78014H (v) 2-wire serial I/O mode (SCK0... Internal clock output) Parameter SCK0 cycle time SCK0 high-level width Symbol tKCY5 tKH5 Test Conditions MIN. TYP. MAX. Unit 2.7 V ≤ VDD ≤ 5.5 V 1600 ns C = 100 pF Note 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns R = 1 kΩ, VDD = 2.7 to 5.5 V tKCY5/2–160 ns tKCY5/2–190 ns tKCY5/2–50 ns SCK0 low-level width tKL5 VDD = 4.5 to 5.5 V tKCY5/2–100 ns SB0, SB1 setup time tSIK5 4.5 V ≤ VDD ≤ 5.5 V 300 ns 2.7 V ≤ VDD < 4.5 V 350 ns 2.0 V ≤ VDD < 2.7 V 400 ns (to SCK0↑) SB0, SB1 hold time 500 ns tKSI5 600 ns tKSO5 0 (from SCK0↑) SB0, SB1 output delay 300 ns time from SCK0↓ Note R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line. 45 µPD78011H, 78012H, 78013H, 78014H (vi) 2-wire serial I/O mode (SCK0... External clock input) Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time Symbol tKCY6 tKH6 tKL6 tSIK6 Test Conditions TYP. MAX. Unit 2.7 V ≤ VDD ≤ 5.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns 2.7 V ≤ VDD ≤ 5.5 V 650 ns 2.0 V ≤ VDD < 2.7 V 1300 ns 2100 ns 2.7 V ≤ VDD ≤ 5.5 V 800 ns 2.0 V ≤ VDD < 2.7 V 1600 ns 2400 ns 100 ns VDD = 2.0 to 5.5 V (to SCK0↑) SB0, SB1 hold time MIN. tKSI6 150 ns tKCY6/2 ns (from SCK0↑) SB0, SB1 output delay tKSO6 time from SCK0↓ SCK0 rise, fall time 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns C = 100 pF Note 2.0 V ≤ VDD < 4.5 V 0 500 ns 0 800 ns 160 ns 700 ns 1000 ns R = 1 kΩ, tR6 When external device tF6 expansion function is used When external When 16-bit timer device expansion output function is function is not used used When 16-bit timer output function is not used Note R and C are the load resistors and load capacitance of the SB0 and SB1 output line. 46 µPD78011H, 78012H, 78013H, 78014H (b) Serial Interface Channel 1 (i) 3-wire serial I/O mode (SCK1... Internal clock output) Parameter SCK1 cycle time Symbol tKCY7 SCK1 high/low-level tKH7 width tKL7 SI1 setup time tSIK7 (to SCK1↑) SI1 hold time Test Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns VDD = 4.5 to 5.5 V tKCY7/2–50 ns tKCY7/2–100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.7 V ≤ VDD < 4.5 V 150 ns 2.0 V ≤ VDD < 2.7 V 300 ns 400 ns 400 ns tKSI7 (from SCK1↑) SO1 output delay time tKSO7 C = 100 pF Note 300 ns MAX. Unit from SCK1↓ Note C is the load capacitance of SCK1 and SO1 output line. (ii) 3-wire serial I/O mode (SCK1... External clock input) Parameter SCK1 cycle time Symbol tKCY8 Test Conditions MIN. TYP. 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns 400 ns SCK1 high/low-level tKH8 4.5 V ≤ VDD ≤ 5.5 V width tKL8 2.7 V ≤ VDD < 4.5 V 800 ns 2.0 V ≤ VDD < 2.7 V 1600 ns 2400 ns SI1 setup time tSIK8 VDD = 2.0 to 5.5 V (to SCK1↑) SI1 hold time tKSI8 100 ns 150 ns 400 ns (from SCK1↑) SO0 output delay time tKSO8 C = 100 pF Note VDD = 2.0 to 5.5 V from SCK1↓ SCK1 rise, fall time tR8 When external device tF8 expansion function is used When external When 16-bit timer 300 ns 500 ns 160 ns 700 ns 1000 ns device expansion output function is function is not used used When 16-bit timer output function is not used Note C is the load capacitance of SO1 output line. 47 µPD78011H, 78012H, 78013H, 78014H (iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... Internal clock output) Parameter SCK1 cycle time Symbol tKCY9 SCK1 high/low-level tKH9 width tKL9 SI1 setup time tSIK9 (to SCK1↑) SI1 hold time Test Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns tKCY9/2–50 ns tKCY9/2–100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.7 V ≤ VDD < 4.5 V 150 ns 2.0 V ≤ VDD < 2.7 V 300 ns 400 ns 400 ns VDD = 4.5 to 5.5 V tKSI9 (from SCK1↑) SO1 output delay time tKSO9 C = 100 pF Note 300 ns tKCY9/2–100 tKCY9/2+100 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY9–30 tKCY9+30 ns 2.0 V ≤ VDD < 2.7 V tKCY9–60 tKCY9+60 ns tKCY9–90 tKCY9+90 ns from SCK1↓ STB↑ from SCK1↑ tSBD Strobe signal tSBW high-level width Busy signal setup time tBYS 100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns (from busy signal 2.7 V ≤ VDD < 4.5 V 150 ns detection timing) 2.0 V ≤ VDD < 2.7 V 200 ns 300 ns (to busy signal detection timing) Busy signal hold time SCK1↓ from busy tBYH tSPS inactive Note C is the load capacitance of SCK1 and SO1 output line. 48 2tKCY9 ns µPD78011H, 78012H, 78013H, 78014H (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... External clock input) Parameter SCK1 cycle time Symbol tKCY10 Test Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns SCK1 high/low-level tKH10, 4.5 V ≤ VDD ≤ 5.5 V 400 ns width tKL10 2.7 V ≤ VDD < 4.5 V 800 ns 2.0 V ≤ VDD < 2.7 V 1600 ns 2400 ns 100 ns 150 ns 400 ns SI1 setup time tSIK10 VDD = 2.0 to 5.5 V (to SCK1↑) SI1 hold time tKSI10 (from SCK1↑) SO1 output delay time tKSO10 C = 100 pF Note VDD = 2.0 to 5.5 V tR10, tF10 When external device expansion from SCK1↓ SCK1 rise, fall time 300 ns 500 ns 160 ns 1000 ns function is used When external device expansion function is not used Note C is the load capacitance of the SO1 output line. 49 µPD78011H, 78012H, 78013H, 78014H AC Timing Test Point (Excluding X1, XT1 Input) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 Input VIL4 (MAX.) 1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.) XT1 Input TI Timing tTIH0 tTIL0 TI0 1/fTI1 tTIL1 TI1,TI2 50 tTIH1 µPD78011H, 78012H, 78013H, 78014H Read/Write Operation External fetch (No wait): A8-A15 Higher 8-Bit Address tADD1 Hi-Z Lower 8-Bit AD0-AD7 Address tADS tADH Operation Code tRDD1 tRDADH tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH External fetch (Wait insertion): A8-A15 Higher 8-Bit Address tADD1 Lower 8-Bit Address AD0-AD7 tADS tADH Hi-Z Operation Code tRDADH tRDD1 tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH WAIT tRDWT1 tWTL tWTRD 51 µPD78011H, 78012H, 78013H, 78014H External data access (No wait): A8-A15 Higher 8-Bit Address tADD2 Lower 8-Bit Address AD0-AD7 tADS Hi-Z Read Data Hi-Z Hi-Z Write Data tRDD2 tADH tASTH tRDH ASTB RD tASTRD tRDWD tRDL2 tWDS tWDH tWRWD tWRADH WR tASTWR tWRL1 External data access (Wait insertion): A8-A15 Higher 8-Bit Address tADD2 Lower 8-Bit Address AD0-AD7 Hi-Z Read Data Hi-Z Hi-Z Write Data tADS tADH tASTH tRDD2 tRDH ASTB tASTRD RD tRDL2 tRDWD tWDH tWDS tWRWD WR tASTWR tWRL1 tWRADH WAIT tRDWT2 tWTL tWTRD tWTL tWRWT 52 tWTWR µPD78011H, 78012H, 78013H, 78014H Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm tFn tRn SCK0,SCK1 tSIKm SI0,SI1 tKSIm Input Data tKSOm Output Data SO0,SO1 m = 1, 2, 7, 8 n = 2, 8 SBI mode (Bus release signal transfer): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBL tSBH tSIK3, 4 tSBK tKSI3, 4 SB0, SB1 tKSO3, 4 SBI Mode (command signal transfer): tKCY3, 4 tKL3, 4 tR4 tKH3, 4 tF4 SCK0 tKSB tSIK3, 4 tSBK tKSI3, 4 SB0, SB1 tKSO3, 4 53 µPD78011H, 78012H, 78013H, 78014H 2-wire serial I/O mode: tKCY5,6 tKL5,6 tR6 tKH5,6 tF6 SCK0 tSIK5,6 tKSO5,6 tKSI5,6 SB0, SB1 3-wire serial I/O mode with automatic transmit/receive function: SO1 SI1 D2 D1 D2 D7 D0 D1 D7 D0 tSIK9,10 tKSI9,10 tKSO9,10 tKH9,10 tF10 SCK1 tKL9,10 tKCY9,10 tR10 tSBD tSBW STB 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCK1 7 8 9 Note 10 tBYS Note Note tBYH BUSY (Active High) Note The signal is not actually driven low here; it is shown as such to indicate the timing. 54 1 10 + n tSPS µPD78011H, 78012H, 78013H, 78014H A/D converter characteristics (TA = –40 to +85 °C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 8 8 8 bit 2.7 V ≤ AVREF ≤ AVDD 0.6 % 1.8 V ≤ AVREF ≤ 2.7 V 1.4 % Resolution Overall error Note Conversion time tCONV Sampling time 2.0 V ≤ AVDD < 5.5 V 19.1 200 µs 1.8 V ≤ AVDD < 2.0 V 38.2 200 µs µs tSAMP 24/fX Analog input voltage VIAN AVSS AVREF V Reference voltage AVREF 1.8 AVDD V AVREF–AVSS resistance RAIREF 4 14 kΩ Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C) Parameter Symbol Data retention supply Test Conditions VDDDR MIN. TYP. 1.8 MAX. Unit 5.5 V 10 µA voltage Data retention supply IDDDR current VDDDR = 1.8 V 0.1 Subsystem clock stop and feedback resister disconnected Release signal set time Oscillation stabilization wait time tSREL tWAIT µs 0 18 Release by RESET 2 /fX ms Release by interrupt Note ms Note In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 213/ fX and 215/fX to 218/fX is possible. Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retension Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT 55 µPD78011H, 78012H, 78013H, 78014H Data Retention Timing (Standby Release Signal : STOP Mode Release by Interrupt Signal) HALT Mode Operating Mode STOP Mode Data Retension Mode VDD VDDDR tSREL STOP Instruction Execition Standby Release Signal (Interrupt Request) tWAIT Interrupt Input Timing tINTL INTP0-INTP2 tINTL INTP3 RESET Input Timing tRSL RESET 56 tINTH µPD78011H, 78012H, 78013H, 78014H 12. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE B C M ITEM MILLIMETERS R INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 Remark Dimensions and materials of ES products are the same as those of mass-production products. 57 µPD78011H, 78012H, 78013H, 78014H 64 PIN PLASTIC QFP ( 14) A B 33 32 48 49 F Q 5°±5° S D C detail of lead end 64 1 G 17 16 H I M J M P K N L P64GC-80-AB8-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. Remark 58 ITEM MILLIMETERS INCHES A 17.6 ± 0.4 0.693 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 1.0 0.039 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.55 0.100 Q 0.1 ± 0.1 0.004 ± 0.004 S 2.85 MAX. 0.112 MAX. Dimensions and materials of ES products are the same as those of mass-production products. µPD78011H, 78012H, 78013H, 78014H 64 PIN PLASTIC LQFP ( 12) A B 33 32 detail of lead end Q R D C S 48 49 F 64 17 16 1 H I M J K M P G N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 14.8±0.4 0.583±0.016 B 12.0±0.2 0.472 +0.009 –0.008 C 12.0±0.2 0.472 +0.009 –0.008 D 14.8±0.4 0.583±0.016 F 1.125 0.044 G 1.125 0.044 H 0.30±0.10 0.012 +0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.4±0.2 0.055±0.008 L 0.6±0.2 0.024 +0.008 –0.009 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 1.4 0.055 Q R 0.125±0.075 5°±5° 0.005±0.003 5°±5° S 1.7 MAX. 0.067 MAX. P64GK-65-8A8-1 Remark Dimensions and materials of ES products are the same as those of mass-production products. 59 µPD78011H, 78012H, 78013H, 78014H 13. RECOMMENDED SOLDERING CONDITIONS The µPD78011F/78012F/78013F/78014F/78015F/78016F should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our salespersonnel. Table 14-1. Surface Mounting Type Soldering Conditions (1/2) (1) µPD78011HGC-×××-AB8 : µPD78012HGC-×××-AB8 : 64-Pin Plastic QFP (14 × 14 mm) 64-Pin Plastic QFP (14 × 14 mm) µPD78013HGC-×××-AB8 : µPD78014HGC-×××-AB8 : 64-Pin Plastic QFP (14 × 14 mm) 64-Pin Plastic QFP (14 × 14 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Thrice max. IR35-00-3 VPS Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above), Number of times: Thrice max. VP15-00-3 Wave soldering Solder bath temperature: 260 °C max. Duration: 10 sec. max. WS60-00-1 Number of times: Once Preliminary heat temperature: 120 °C max. (Package surface temperature) Partial heating Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side) — Caution Use more than one soldering method should be avoided (except in the case of partial heating). 60 µPD78011H, 78012H, 78013H, 78014H Table 14-1. Surface Mounting Type Soldering Conditions (2/2) (2) µPD78011HGK-×××-8A8 : 64-Pin Plastic LQFP (12 × 12 mm) µPD78012HGK-×××-8A8 : 64-Pin Plastic LQFP (12 × 12 mm) µPD78013HGK-×××-8A8 : 64-Pin Plastic LQFP (12 × 12 mm) µPD78014HGK-×××-8A8 : 64-Pin Plastic LQFP (12 × 12 mm) Soldering Conditions Soldering Method Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Twice max., Number of days: 7 days Note (after that, 125 °C prebaking for 10 hours is necessary.) < Points to note > Products packed in packing materials other than heat-resistant trays (such as magazines, taping, and non-heat resistance tray) cannot be baked while packed. IR35-107-2 VPS Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above), Number of times: Twice max., Number of days: 7 days Note (after that, 125 °C prebaking for 10 hours is necessary.) < Points to note > Products packed in packing materials other than heat-resistant trays (such as magazines, taping, and non-heat resistance tray) cannot be baked while packed. VP15-107-2 Wave soldering Solder bath temperature: 260 °C max. Duration: 10 sec. max. Number of times: Once, Preliminary heat temperature: 120 °C max. (Package surface temperature), Number of days: 7 days Note (after that, 125 °C prebaking for 10 hours is necessary.) WS60-107-1 Partial heating Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side) — Note The number of days the device can be stored at 25 °C, 65% RH MAX. after the dry pack has been opend. Caution Use more than one soldering method should be avoided (except in the case of partial heating). Table 14-2. Insertion Type Soldering Conditions µPD78011HCW-××× : µPD78012HCW-××× : µPD78013HCW-××× : µPD78014HCW-××× : Soldering Method Caution 64-Pin Plastic Shrink DIP (750 mil) 64-Pin Plastic Shrink DIP (750 mil) 64-Pin Plastic Shrink DIP (750 mil) 64-Pin Plastic Shrink DIP (750 mil) Soldering Conditions Wave soldering (pin only) Solder bath temperature: 260°C max., Duration: 10 sec. max. Partial heating Pin temperature: 300°C max., Duration: 3 sec. max. (per pin) Wave soldering is only for the lead part in order that jet solder can not contact with the chip directly. 61 µPD78011H, 78012H, 78013H, 78014H APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for the development of systems using the µPD78014H subseries. Language processor software RA78K/0 Notes 1, 2, 3, 4 Assembler package common to 78K/0 series CC78K0 Notes 1, 2, 3, 4 C compiler package common to 78K/0 series DF78014 Notes 1, 2, 3, 4, 6 Device file common to µPD78014 subseries CC78K0-L Notes 1, 2, 3, 4 C compiler library source file common to 78K/0 series Debugging tools IE-78000-R In-circuit emulator common to 78K/0 series IE-78000R-A Notes 8 In-circuit emulator common to 78K/0 series (for integrated debugger) IE-78000-R-BK Break board common to 78K/0 series IE-78014-R-EM-A Emulation board common to µPD78018F and 78018FY subseries (VDD = 3.0 to 6.0 V) EP-78240CW-R EP-78240GK-R Emulation probe common to µPD78244 subseries EP-78012GK-R Emulation probe common to µPD78018F subseries EV-9200GC-64 Socket mounted on printed wiring board of target system created for 64-pin plastic QFP (GC-AB8 type) TGK-064SBW Adapter mounted on printed wiring board of target system created for 64-pin plastic QFP (GK-8A8 type). This is a product of TOKYO ELETECH Corp. Consult NEC when purchasing this product. SM78K0 Notes 5, 6, 7 ID78K0 Notes 4, 5, 6, 7 System emulator common to 78K/0 series Integrated debugger common to 78K/0 series SD78K/0 Notes 1, 2 Screen debugger for IE-78000-R DF78014 Notes 1, 2, 3, 4, 5, 6, 7 Device file common to µPD78014 subseries Real-Time OS RX78K/0 Notes 1, 2 Real-time OS for 78K/0 series MX78K0 Notes 1, 2 OS for 78K/0 series 62 µPD78011H, 78012H, 78013H, 78014H Fuzzy Inference Devleopment Support System FE9000 Note 1/FE9200 Note 6 Fuzzy knowledge data creation tool FT9080 Note 1/FT9085 Note 2 Translator FI78K0 Notes 1, 2 Fuzzy inference module FD78K0 Notes 1, 2 Fuzzy inference debugger Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM and compatible machine (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 series 300TM (HP-UXTM) based 4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWS-UX/V) based 5. PC-9800 series (MS-DOS + WindowsTM) based 6. IBM PC/AT and compatible machine (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based 8. Under development. Remarks 1. For development tools manufactured by a third party, refer to the 78K/0 Series Selection Guide (U11126E). 2. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78014. 63 µPD78011H, 78012H, 78013H, 78014H APPENDIX B. RELATED DOCUMENTS Device Related Documents Document No. Document Name Japanese µPD78014H Subseries User's Manual English Planned to publish Planned to publish µPD78014 Data Sheet U11898J This manual 78K/0 Series User's Manual - Instruction IEU-849 IEU-1372 78K/0 Series Instruction List U10903J — 78K/0 Series Instruction Set U10904J — Planned to publish — µPD78014H Subseries Special Function Register List Development Tools Documents (User's Manual) Document No. Document Name Japanese English Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 EEU-817 EEU-1402 Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Programming Know-how EEA-618 EEA-1208 CC78K Series Library Source File EEU-777 — IE-78000-R EEU-810 U11376E IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-78014-R-EM-A EEU-962 U10418E EP-78240 EEU-986 EEU-1513 EP-78012GK-R EEU-5012 EEU-1538 RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler CC78K/0 C Compiler Application Note SM78K0 System Simulator Windows Based Reference U10181J U10181E SM78K Series System Simulator External Components User Open U10092J U10092E Interface ID78K0 Integrated Debugger EWS Based Reference U11151J — ID78K0 Integrated Debugger PC Based Reference U11539J — ID78K0 Integrated Debugger Windows Based Guide U11649J — SD78K/0 Screen Debugger Introduction EEU-852 — PC-9800 Series (MS-DOS) Based Reference EEU-816 — SD78K/0 Screen Deb Introduction EEU-5024 EEU-1414 IBM PC/AT (PC DOS) Based Reference EEU-993 EEU-1413 Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 64 µPD78011H, 78012H, 78013H, 78014H Embedded Software Documents (User's Manual) Document No. Document Name Japanese English Fundamental U11537J — Installation U11536J — Technical U11538J — EEU-5010 — Fuzzy Knowledge Data Creation Tool EEU-829 EEU-1438 78K/0, 78K/II, 87AD Series EEU-862 EEU-1444 EEU-858 EEU-1441 EEU-921 EEU-1458 78K/0 Series Real-Time OS 78K/0 Series OS MX78K0 Fundamental Fuzzy Inference Development Support System - Translator 78K/0 Series Fuzzy Inference Development Suport System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Other Documents Document Name Document No. Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device C11531J IEI-1209 NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 — Guide to Quality Assurance for Semiconductor Device MEI-603 MEI-1202 Guide for Products Related to Micro-Computer: Other Companies U11416J — Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 65 µPD78011H, 78012H, 78013H, 78014H NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 66 µPD78011H, 78012H, 78013H, 78014H Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 67 µPD78011H, 78012H, 78013H, 78014H FIP and IEBus are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM-DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a tradmark of SPARC International, Inc. SunOS is a tradmark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. Some related decuments are preliminary versions. This document, however, is not indicated as preliminary. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 68