0.5 Ω CMOS, Dual 2:1 MUX/SPDT Audio Switch ADG884 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V to 5.5 V operation Ultralow on resistance 0.34 Ω typ 0.38 Ω max at 5 V supply Excellent audio performance, ultralow distortion 0.1 Ω typ 0.15 Ω max RON flatness High current carrying capability 400 mA continuous 600 mA peak current at 5 V supply Rail-to-rail switching operation Typical power consumption (<0.1 μW) ADG884 S1A D1 S1B IN1 IN2 S2A D2 SWITCHES SHOWN FOR A LOGIC 1 INPUT 05028-001 S2B Figure 1. APPLICATIONS Cellular phones PDAs MP3 players Power routing Battery-powered systems PCMCIA cards Modems Audio and video signal routing Communications systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG884 is a low voltage CMOS device containing two independently selectable single-pole, double-throw (SPDT) switches. This device offers ultralow on resistance of less than 0.4 Ω over the full temperature range, making the part an ideal solution for applications that require minimal distortion through the switch. The ADG884 also has the capability of carrying large amounts of current, typically 600 mA at 5 V operation. 1. Single 1.8 V to 5.5 V operation. 2. High current handling capability (400 mA continuous current at 3.3 V). 3. 1.8 V logic-compatible. 4. Low THD + N (0.01% typ). 5. Tiny 2 mm × 1.5 mm WLCSP package, 3 mm × 3 mm 10-lead LFCSP package, and 10-lead MSOP package. The ADG884 is available in a 10 bump, 2.0 mm × 1.50 mm WLCSP package, a 10-lead LFCSP package, and a 10-lead MSOP package. These tiny packages make the ADG884 the ideal solution for space-constrained applications. When on, each switch conducts equally well in both directions and has an input signal range that extends to the supplies. The ADG884 exhibits break-before-make switching action. Table 1. ADG884 Truth Table Logic (IN1/IN2) 0 1 Switch 1A/2A Off On Switch 1B/2B On Off Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADG884 TABLE OF CONTENTS Specifications..................................................................................... 3 Terminology .................................................................................... 11 Absolute Maximum Ratings............................................................ 6 Test Circuits..................................................................................... 12 ESD Caution.................................................................................. 6 Outline Dimensions ....................................................................... 14 Pin Configurations and Function Descriptions ........................... 7 Ordering Guide .......................................................................... 15 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 6/05—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 10/04—Revision 0: Initial Version Rev. A | Page 2 of 16 ADG884 SPECIFICATIONS VDD = 5 V ± 10%, GND = 0 V, unless otherwise noted. 1 Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 0.28 0.34 0.01 0.035 0.1 0.13 −40°C to +85°C Unit 0 V to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 0.38 0.05 0.15 ±0.2 ±0.2 nA typ nA typ 2.0 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 tON 2 Break-Before-Make Time Delay, tBBM 42 50 15 20 16 Charge Injection Off Isolation 125 −60 ns typ ns max ns typ ns max ns typ ns min pC typ dB typ Channel-to-Channel Crosstalk −120 dB typ −60 dB typ 0.017 % −0.03 18 103 295 dB typ MHz typ pF typ pF typ 0.003 μA typ μA max tOFF 53 21 10 Total Harmonic Distortion, THD + N Insertion Loss −3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 1 1 2 V min V max μA typ μA max pF typ Temperature range of the B version is −40°C to +85°C. Guaranteed by design, not subject to production test. Rev. A | Page 3 of 16 Test Conditions/Comments VDD = 4.5 V, VS = 0 V to VDD, IS = 100 mA See Figure 18 VDD = 4.5 V, VS = 2 V, IS = 100 mA VDD = 4.5 V, VS = 0 V to VDD IS = 100 mA VDD = 5.5 V VS = 0.6 V/4.5 V, VD = 4.5 V/0.6 V; see Figure 19 VS = VD = 0.6 V or 4.5 V; see Figure 20 VIN = VINL or VINH RL = 50 Ω, CL = 35 pF VS = 3 V/0 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS = 3 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 22 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 S1A−S2A/S1B−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 S1A−S1B/S2A−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p RL = 50 Ω, CL = 5 pF; see Figure 26 RL = 50 Ω, CL = 5 pF; see Figure 26 VDD = 5.5 V Digital inputs = 0 V or 5.5 V ADG884 VDD = 3.4 V to 4.2 V; GND = 0 V, unless otherwise noted. 1 Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 0.33 0.38 0.013 0.042 0.13 0.155 −40°C to +85°C Unit 0 V to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 0.45 0.065 0.175 ±0.2 ±0.2 nA typ nA typ 2.0 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 tON 2 Break-Before-Make Time Delay, tBBM 42 50 15 21 17 Charge Injection Off Isolation 100 −60 ns typ ns max ns typ ns max ns typ ns min pC typ dB typ Channel-to-Channel Crosstalk −120 dB typ −60 dB typ 0.01 % −0.03 18 110 300 dB typ MHz typ pF typ pF typ 0.003 μA typ μA max tOFF 54 24 10 Total Harmonic Distortion, THD + N Insertion Loss −3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 1 1 2 V min V max μA typ μA max pF typ Temperature range of the B version is −40°C to +85°C. Guaranteed by design, not subject to production test. Rev. A | Page 4 of 16 Test Conditions/Comments VDD = 3.4 V, VS = 0 V to VDD, IS = 100 mA See Figure 18 VDD = 3.4 V, VS = 2 V, IS = 100 mA VDD = 3.4 V, VS = 0 V to VDD IS = 100 mA VDD = 4.2 V VS = 0.6 V/3.9 V, VD = 3.9 V/0.6 V; see Figure 19 VS = VD = 0.6 V or 3.9 V; see Figure 20 VIN = VINL or VINH RL = 50 Ω, CL = 35 pF VS = 1.5 V/0 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS = 1.5 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 22 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 S1A−S2A/S1B−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 S1A−S1B/S2A−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p RL = 50 Ω, CL = 5 pF; see Figure 26 RL = 50 Ω, CL = 5 pF; see Figure 26 VDD = 4.2 V Digital inputs = 0 V or 4.2 V ADG884 VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. 1 Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON On Resistance Flatness, RFLAT (ON) 25°C 0.4 0.5 0.02 0.07 0.18 −40°C to +85°C Unit 0 V to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 0.6 0.1 0.25 LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ±0.2 ±0.2 nA typ nA typ 1.3 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 tON 2 Break-Before-Make Time Delay, tBBM 42 56 14 19 24 Charge Injection Off Isolation Channel-to-Channel Crosstalk 85 −60 −120 ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ −60 dB typ 0.03 −0.03 18 110 300 % dB typ MHz typ pF typ pF typ 0.003 μA typ μA max tOFF 62 21 10 Total Harmonic Distortion, THD + N Insertion Loss –3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 1 1 2 V min V max μA typ μA max pF typ Temperature range of the B version is −40°C to +85°C. Guaranteed by design, not subject to production test. Rev. A | Page 5 of 16 Test Conditions/Comments VDD = 2.7 V, VS = 0 V to VDD IS = 100 mA; see Figure 18 VDD = 2.7 V, VS = 0.6 V IS = 100 mA VDD = 2.7 V, VS = 0 V to VDD IS = 100 mA VDD = 3.6 V VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V, see Figure 19 VS = VD = 0.6 V or 3.3 V; see Figure 20 VIN = VINL or VINH RL = 50 Ω, CL = 35 pF VS = 1.5 V/0 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS = 1.5 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 22 VS = 1.25 V, RS = 0 Ω, CL = 1 nF; see Figure 23 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 S1A−S2A/S1B−S2B, RL = 50 V, CL = 5 pF, f = 100 kHz; see Figure 27 S1A−S1B/S2A−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p RL = 50 Ω, CL = 5 pF; see Figure 26 RL = 50 Ω, CL = 5 pF; see Figure 26 VDD = 3.6 V Digital inputs = 0 V or 3.6 V ADG884 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D 5 V Operation Continuous Current, S or D 5 V Operation Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature 10-Lead MSOP Package θJA Thermal Impedance θJC Thermal Impedance 10-Lead WLCSP Package (4-Layer Board) θJA Thermal Impedance 10-Lead LFCSP Package (4-Layer Board) θJA Thermal Impedance θJC Thermal Impedance IR Reflow, Peak Temperature <20 s 1 Rating −0.3 V to +6 V −0.3 V to VDD + 0.3 V −0.3 V to 6 V or 10 mA (whichever occurs first) 600 mA (pulsed at 1 ms, 10% duty cycle max) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 400 mA −40°C to +85°C −65°C to +150°C 150°C 206°C/W 44°C/W 120°C/W 76°C/W 13.5°C/W 235°C Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 16 ADG884 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADG884 TOP VIEW (Not to Scale) S1B GND 1 2 S2B 3 IN1 IN2 10 4 D1 D2 10 S2A S1A 2 ADG884 9 D2 S1A VDD S2A TOP VIEW (Not to Scale) 8 IN2 8 7 6 7 S2B 6 GND IN1 4 S1B 5 05028-002 D1 3 9 (SOLDER BUMPS ON OPPOSITE SIDE) Figure 2. LFCSP and MSOP Pin Configuration Figure 3. WLCSP Pin Configuration Table 6. Pin Function Descriptions LFCSP, MSOP 1 2 3 4 5 6 7 8 9 10 Pin No. WLCSP 7 8 9 10 1 2 3 4 5 6 Mnemonic VDD S1A D1 IN1 S1B GND S2B IN2 D2 S2A 05028-003 5 VDD 1 Description Most Positive Power Supply Potential. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Source Terminal. May be an input or output. Ground (0 V) Reference. Source Terminal. May be an input or output. Login Control Input. Drain Terminal. May be an input or output. Source Terminal. May be an input or output. Rev. A | Page 7 of 16 ADG884 TYPICAL PERFORMANCE CHARACTERISTICS 0.30 0.45 TA = 25°C IDS = 100mA VDD = 3.3V IDS = 100mA 0.40 0.25 0.35 4.5V 0.20 5.5V 0.15 ON RESISTANCE ON RESISTANCE +85°C 4.2V 5V 0.10 0.30 +25°C 0.25 –40°C 0.20 0.15 0.10 0 0 1 2 3 SIGNAL RANGE 4 0.05 0 5 0 Figure 4. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V 1.0 1.5 2.0 SIGNAL RANGE 2.5 3.0 5 TA = 25°C IDS = 100mA 0.40 0.35 VDD = 5V 4 3 2.7V LEAKAGE CURRENT (nA) 0.30 3V 0.25 3.3V 0.20 0.15 0.10 2 ID, IS (ON) 1 0 IS (OFF) –1 –2 0 0 0.5 1.0 1.5 2.0 SIGNAL RANGE 2.5 05028-008 05028-005 –3 0.05 –4 –5 3.0 0 Figure 5. On Resistance vs. VD (VS), VDD = 2.7 V to 3.3 V 10 20 30 40 50 TEMPERATURE 60 70 80 Figure 8. Leakage Current vs. Temperature, VDD = 5 V 0.35 5 VDD = 5V IDS = 100mA 0.30 VDD = 4.2V LEAKAGE CURRENT (nA) 4 0.25 +85°C 0.20 +25°C 0.15 –40°C 0.10 3 2 1 ID, IS (ON) 0 05028-006 0.05 0 0 1 2 3 SIGNAL RANGE 4 05028-009 ON RESISTANCE 0.5 Figure 7. On Resistance vs. VD (VS) for Different Temperature, VDD = 3.3 V 0.45 ON RESISTANCE 05028-007 05028-004 0.05 IS (OFF) –1 5 0 Figure 6. On Resistance vs. VD (VS) for Different Temperature, VDD = 5 V Rev. A | Page 8 of 16 10 20 30 40 50 TEMPERATURE 60 70 Figure 9. Leakage Current vs. Temperature, VDD = 4.2 V 80 ADG884 4.0 0 VDD = 3.3V 3.5 –1 TA = 25°C VDD = 5V/4.2V/3V –2 2.5 ATTENUATION (dB) LEAKAGE CURRENT (nA) 3.0 2.0 1.5 ID, IS (ON) 1.0 0.5 –3 –4 –5 –6 0 –1.0 10 20 30 40 50 TEMPERATURE 60 70 –8 0.03 80 05028-022 IS (OFF) 0 –7 05028-026 –0.5 0.10 1.00 10.00 FREQUENCY (MHz) Figure 10. Leakage Current vs. Temperature, VDD = 3.3 V 100.00 Figure 13. Bandwidth 600 0 TA = 25°C –10 500 TA = 25°C VDD = 5V/4.2V/3V VDD = 5V ATTENUATION (dB) –20 QINJ (pC) 400 VDD = 4.2V 300 200 –30 –40 –50 –60 0 0 0.5 1.0 1.5 2.0 –70 05028-010 VDD = 3V 2.5 3.0 VS (V) 3.5 4.0 4.5 –80 10 5.0 05028-023 100 100 1k 10k 100k 1M FREQUENCY (MHz) 10M 100M 10M 100M Figure 14. Off Isolation vs. Frequency Figure 11. Charge Injection vs. Source Voltage 0 50 TA = 25°C –10 TA = 25°C VDD = 5V/4.2V/3V VDD = 5V –20 VDD = 3V tON ATTENUATION (dB) TIMES 30 20 VDD = 5V tOFF –40 –50 –60 VDD = 3V –70 05028-011 10 0 –40 –30 –20 0 20 40 TEMPERATURE (°C) 60 –80 10 80 Figure 12. tON/tOFF Times vs. Temperature 05028-024 40 100 1k 10k 100k 1M FREQUENCY (MHz) Figure 15. Crosstalk vs. Frequency Rev. A | Page 9 of 16 ADG884 0.10 0 –20 TA = 25°C VDD = 5V/4.2V/3V 0.09 0.08 0.07 THD + N (%) –60 –80 –100 0.06 0.05 0.04 VDD = 3V, 1.5V p-p 0.03 –120 –160 10 100 1k 10k 100k 1M FREQUENCY (MHz) 10M 0.01 05028-027 VDD = 5V, 3.5V p-p 0.02 –140 05028-025 ATTENUATION (dB) –40 VDD = 4.2V, 2V p-p 0 0 100M Figure 16. AC PSRR 10 20 30 40 50 60 70 FREQUENCY (kHz) Figure 17. THD + N Rev. A | Page 10 of 16 80 90 100 ADG884 TERMINOLOGY IDD Positive supply current. CD, CS (ON) On switch capacitance. Measured with reference to ground. VD (VS) Analog voltage on Terminals D, S. CIN Digital input capacitance. RON Ohmic resistance between D and S. tON Delay time between the 50% and 90% points of the digital input and switch on condition. RFLAT (ON) The difference between the maximum and minimum values of on resistance as measured on the switch. ΔRON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. tOFF Delay time between the 50% and 90% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to another. ID (OFF) Drain leakage current with the switch off. Charge Injection Measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. ID, IS (ON) Channel leakage current with the switch on. Off Isolation Measure of unwanted signal coupling through an off switch. VINL Maximum input voltage for Logic 0. Crosstalk Measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Measured with reference to ground. CD (OFF) Off switch drain capacitance. Measured with reference to ground. −3 dB Bandwidth Frequency at which the output is attenuated by 3 dB. On Response Frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N Ratio of the harmonics amplitude plus noise of a signal to the fundamental. Rev. A | Page 11 of 16 ADG884 TEST CIRCUITS IDS V1 D A ID (ON) VD VS Figure 18. On Resistance S NC D VD Figure 19. Off Leakage Figure 20. On Leakage VDD 0.1μF VDD S1B S1A VS VOUT D 50% VIN CL 35pF RL 50Ω IN 50% 90% 90% GND tON tOFF 05028-015 VOUT Figure 21. Switching Times, tON, tOFF VDD 0.1μF 50% VDD S1B S1A VS VIN RL IN 80% CL 35pF 80% tBBM tBBM 05028-016 50Ω 50% 0V VOUT VOUT D GND Figure 22. Break-Before-Make Time Delay, tBBM VDD SW ON NC D S1A VOUT 1nF IN VOUT ΔVOUT QINJ = CL × ΔVOUT GND Figure 23. Charge Injection Rev. A | Page 12 of 16 05028-017 VS SW OFF VIN S1B A 05028-014 RON = V1/IDS ID (OFF) S A 05028-012 VS D 05028-013 IS (OFF) S ADG884 VDD VDD 0.1μF 0.1μF NETWORK ANALYZER S1B S1A 50Ω VOUT 50Ω VS RL 50Ω VOUT 50Ω GND OFF ISOLATION = 20 LOG RL 50Ω VS 05028-018 RL 50Ω D S1B D GND VOUT VS CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG Figure 24. Off Isolation VOUT VS Figure 26. Bandwidth VDD 0.1μF VDD S1B S1A NETWORK ANALYZER NETWORK ANALYZER VOUT 50Ω 50Ω VS S2A D2 NC S2B D INSERTION LOSS = 20 LOG VOUT VOUT WITH SWITCH VOUT WITHOUT SWITCH 50Ω VS S1A D1 S1B CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG NC VOUT VS Figure 27. Channel-to-Channel Crosstalk (S1A–S2A) Figure 25. Channel-to-Channel Crosstalk (S1A–S1B) Rev. A | Page 13 of 16 50Ω 05028-021 GND RL 50Ω 05028-019 NC VDD S1A 05028-020 VDD ADG884 OUTLINE DIMENSIONS INDEX AREA 3.00 BSC PIN 1 INDICATOR 3.00 BSC SQ 10 1.50 BCS SQ 0.50 BSC 2.48 2.38 2.23 EXPOSED PAD TOP VIEW (BOTTOM VIEW) 6 10 1 4.90 BSC 3.00 BSC 1 5 PIN 1 6 0.80 0.75 0.70 SEATING PLANE 0.80 MAX 0.55 TYP 0.50 0.40 0.30 0.50 BSC 0.95 0.85 0.75 1.74 1.64 1.49 1.10 MAX 0.15 0.00 0.05 MAX 0.02 NOM SIDE VIEW 0.30 0.23 0.18 5 0.27 0.17 SEATING PLANE 0.23 0.08 8° 0° COPLANARITY 0.10 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 28. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Figure 29. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 0.63 0.57 0.51 SEATING PLANE 1.56 1.50 1.44 C B 1 0.36 0.32 0.28 BUMP 1 IDENTIFIER TOP VIEW (BUMP SIDE DOWN) 2.06 2.00 1.94 A BOTTOM VIEW 2 (BUMP SIDE UP) 0.50 BSC BALL PITCH 3 4 0.26 0.22 0.18 0.11 0.09 0.07 Figure 30. 10-Ball Wafer Level Chip Scale Package [WLCSP] (CB-10) Dimensions shown in millimeters Rev. A | Page 14 of 16 0.80 0.60 0.40 ADG884 ORDERING GUIDE Model ADG884BRMZ 2 ADG884BRMZ-REEL2 ADG884BRMZ-REEL72 ADG884BCPZ-REEL2 ADG884BCPZ-REEL72 ADG884BCBZ-500RL72, 3 ADG884BCBZ-REEL2, 3 ADG884BCBZ-REEL72, 3 1 2 3 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description Mini Small Outline Package (MSOP) Mini Small Outline Package (MSOP) Mini Small Outline Package (MSOP) Lead Frame Chip Scale Package (LFCSP_WD) Lead Frame Chip Scale Package (LFCSP_WD) Micro Chip Scale Package (WLCSP) Micro Chip Scale Package (WLCSP) Micro Chip Scale Package (WLCSP) Branding on this package is limited to three characters due to space constraints. Z = Pb-free package. Contact Sales for availability; product under development. Rev. A | Page 15 of 16 Package Option RM-10 RM-10 RM-10 CP-10-9 CP-10-9 CB-10 CB-10 CB-10 Branding 1 S9C S9C S9C S9C S9C S0W S0W S0W ADG884 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05028–0–6/05(A) Rev. A | Page 16 of 16