ETC 24C00T-E/OT

24AA00/24LC00/24C00
128 Bit I2C™ Bus Serial EEPROM
DEVICE SELECTION TABLE
PACKAGE TYPES
VCC Range
Temp Range
24AA00
1.8 - 6.0
C,I
24LC00
2.5 - 6.0
C,I
24C00
4.5 - 5.5
C,I,E
8-PIN PDIP/SOIC
FEATURES
1
NC
2
NC
3
Vss
4
1
2
3
4
NC
NC
NC
VSS
VCC
7
NC
6
SCL
5
SDA
8
7
6
5
VCC
NC
SCL
SDA
5-PIN SOT-23
SCL
1
VSS
2
SDA
3
24xx00
DESCRIPTION
The Microchip Technology Inc. 24AA00/24LC00/24C00
(24xx00*) is a 128-bit Electrically Erasable PROM
memory organized as 16 x 8 with a 2-wire serial interface. Low voltage design permits operation down to 1.8
volts for the 24xx00 version, and every version maintains a maximum standby current of only 1 µA and typical active current of only 500 µA. This device was
designed for where a small amount of EEPROM is
needed for the storage of calibration values, ID numbers or manufacturing information, etc. The 24xx00 is
available in 8-pin PDIP, 8-pin SOIC (150 mil), 8-pin
TSSOP and the 5-pin SOT-23 packages.
8
8-PIN TSSOP
24xx00
• Low power CMOS technology
- 500 µA typical active current
- 250 nA typical standby current
• Organized as 16 bytes x 8 bits
• 2-wire serial interface bus, I2C™ compatible
• 100 kHz (1.8V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• 4 ms maximum byte write cycle time
• 1,000,000 erase/write cycles guaranteed
• ESD protection > 4 kV
• Data retention > 200 years
• 8L DIP, SOIC, TSSOP and 5L SOT-23 packages
• Temperature ranges available:
- Commercial (C):
0°C to
+70°C
- Industrial (I):
-40°C to
+85°C
- Automotive (E):
-40°C to +125°C
NC
24xx00
Device
5
VCC
4
NC
BLOCK DIAGRAM
HV GENERATOR
I/O
CONTROL
LOGIC
SDA
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
SCL
YDEC
VCC
VSS
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
*24xx00 is used in this document as a generic part number for the 24AA00/24LC00/24C00 devices.
 1998 Microchip Technology Inc.
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DS21178C-page 3-1
24AA00/24LC00/24C00
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
TABLE 1-1
Name
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins................................................4 kV
Function
VSS
Ground
SDA
Serial Data
SCL
Serial Clock
VCC
+1.8V to 6.0V (24AA00)
+2.5V to 6.0V (24LC00)
+4.5V to 5.5V (24C00)
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2
PIN FUNCTION TABLE
NC
No Internal Connection
DC CHARACTERISTICS
All Parameters apply across the recom- Commercial (C): Tamb = 0°C to +70°C, VCC = 1.8V to 6.0V
mended operating ranges unless other- Industrial (I):
Tamb = -40°C to +85°C, VCC = 1.8V to 6.0V
Automotive (E)
Tamb = -40°C to +125°C, VCC = 4.5V to 5.5V
wise noted
Parameter
Symbol
Min.
VIH
0.7 VCC
SCL and SDA pins:
High level input voltage
Low level input voltage
VIL
Hysteresis of Schmitt trigger inputs
VHYS
Low level output voltage
.05 VCC
VOL
Input leakage current
-10
Units
V
Conditions
(Note)
0.3 VCC
V
(Note)
—
V
Vcc ≥ 2.5V (Note)
.40
V
IOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, VCC = 2.5V
10
µA
VIN = VCC or VSS
ILO
-10
10
µA
VOUT = VCC or VSS
CIN,
COUT
—
10
pF
VCC = 5.0V (Note)
Tamb = 25°C, f = 1 MHz
ICC Write
—
2
mA
VCC = 5.5V, SCL = 400 kHz
ICC Read
—
1
mA
VCC = 5.5V, SCL = 400 kHz
ICCS
—
1
µA
VCC = 5.5V, SDA = SCL = VCC
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
ILI
Max.
Standby current
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING DATA
THIGH
TF
TSU:STA
SCL
TLOW
SDA
IN
TR
TSP
TSU:DAT
THD:DAT
TSU:STO
THD:STA
TBUF
TAA
SDA
OUT
DS21178C-page 3-2
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 1998 Microchip Technology Inc.
24AA00/24LC00/24C00
TABLE 1-3
AC CHARACTERISTICS
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Parameter
Commercial (C):
Industrial (I):
Automotive (E):
Tamb = 0°C to +70°C, VCC = 1.8V to 6.0V
Tamb = -40°C to +85°C, VCC = 1.8V to 6.0V
Tamb = -40°C to +125°C, VCC = 4.5V to 5.5V
Symbol
Min
Max
Units
Clock frequency
FCLK
—
—
—
100
100
400
kHz
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
Clock high time
THIGH
4000
4000
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
Clock low time
TLOW
4700
4700
1300
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
SDA and SCL rise time
(Note 1)
TR
—
—
—
1000
1000
300
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
SDA and SCL fall time
TF
—
300
ns
(Note 1)
START condition hold time
THD:STA
4000
4000
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
START condition setup time
TSU:STA
4700
4700
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
Data input hold time
THD:DAT
0
—
ns
(Note 2)
Data input setup time
TSU:DAT
250
250
100
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
STOP condition setup time
TSU:STO
4000
4000
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
TAA
—
—
—
3500
3500
900
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
Bus free time: Time the bus must
be free before a new transmission can start
TBUF
4700
4700
1300
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 6.0V
Output fall time from VIH
minimum to VIL maximum
TOF
20+0.1
CB
250
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
TSP
—
50
ns
(Notes 1, 3)
Write cycle time
TWC
Output valid from clock
(Note 2)
Endurance
—
4
ms
1M
—
cycles
Conditions
25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.
 1998 Microchip Technology Inc.
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DS21178C-page 3-3
24AA00/24LC00/24C00
2.0
PIN DESCRIPTIONS
4.0
2.1
SDA Serial Data
The following bus protocol has been defined:
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
BUS CHARACTERISTICS
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
2.2
Both data and clock lines remain HIGH.
SCL Serial Clock
4.1
Bus not Busy (A)
This input is used to synchronize the data transfer from
and to the device.
4.2
2.3
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Noise Protection
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
3.0
FUNCTIONAL DESCRIPTION
The 24xx00 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be controlled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions, while the 24xx00
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device determines which mode is activated.
DS21178C-page 3-4
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0.1
Start Data Transfer (B)
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.3
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
 1998 Microchip Technology Inc.
24AA00/24LC00/24C00
4.4
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 4-2).
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24xx00 does not generate any
acknowledge bits if an internal programming cycle is in progress.
FIGURE 4-1:
SCL
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(C)
(D)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
(C)
(A)
SDA
FIGURE 4-2:
STOP
CONDITION
DATA
ALLOWED
TO CHANGE
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
SDA
3
4
5
6
7
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
 1998 Microchip Technology Inc.
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8
9
1
2
3
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
DS21178C-page 3-5
24AA00/24LC00/24C00
5.0
DEVICE ADDRESSING
After generating a START condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write bit that indicates what type of operation is to be performed. The slave address for the
24xx00 consists of a 4-bit device code (1010) followed
by three don’t care bits.
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. (Figure 5-1). The 24xx00 monitors the bus for
its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true
and it is not in a programming mode.
FIGURE 5-1:
CONTROL BYTE FORMAT
Read/Write Bit
Don’t Care
Bits
Device Select
Bits
S
1
0
1
0
X
X
X R/W ACK
Slave Address
Start Bit
Acknowledge Bit
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6.0
WRITE OPERATIONS
6.1
Byte Write
Following the start signal from the master, the device
code (4 bits), the don’t care bits (3 bits), and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24xx00. Only the lower
four address bits are used by the device, and the upper
four bits are don’t cares. The 24xx00 will acknowledge
the address byte and the master device will then transmit the data word to be written into the addressed
memory location. The 24xx00 acknowledges again and
the master generates a stop condition. This initiates the
internal write cycle, and during this time the 24xx00 will
not generate acknowledge signals (Figure 7-2). After a
byte write command, the internal address counter will
not be incremented and will point to the same address
location that was just written. If a stop bit is transmitted
to the device at any point in the write command
sequence before the entire sequence is complete, then
the command will abort and no data will be written. If
more than 8 data bits are transmitted before the stop bit
is sent, then the device will clear the previously loaded
byte and begin loading the data buffer again. If more
than one data byte is transmitted to the device and a
stop bit is sent before a full eight data bits have been
transmitted, then the write command will abort and no
data will be written. The 24xx00 employs a VCC threshold detector circuit which disables the internal erase/
write logic if the VCC is below 1.5V (24AA00 and
24LC00) or 3.8V (24C00) at nominal conditions.
 1998 Microchip Technology Inc.
24AA00/24LC00/24C00
7.0
ACKNOWLEDGE POLLING
FIGURE 7-1:
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master sending a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
FIGURE 7-2:
BYTE WRITE
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S
CONTROL
BYTE
1
0
1
0
X
X
BUS ACTIVITY
WORD
ADDRESS
X
X
0
A
C
K
X
X
S
T
O
P
DATA
P
X
A
C
K
A
C
K
X = Don’t Care Bit
 1998 Microchip Technology Inc.
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DS21178C-page 3-7
24AA00/24LC00/24C00
8.0
READ OPERATIONS
device as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24xx00 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a stop condition and the device discontinues
transmission (Figure 8-2). After this command, the
internal address counter will point to the address location following the one that was just read.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1
Current Address Read
The 24xx00 contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the device issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
device discontinues transmission (Figure 8-1).
8.2
8.3
Sequential reads are initiated in the same way as a random read except that after the device transmits the first
data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
Random Read
To provide sequential reads the 24xx00 contains an
internal address pointer which is incremented by one at
the completion of each read operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
FIGURE 8-1:
Sequential Read
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S 1 0 1 0 X XX 1
CONTROL
BYTE
S
T
O
P
DATA
P
A
C
K
BUS ACTIVITY
N
O
A
C
K
X = Don’t Care Bit
FIGURE 8-2:
RANDOM READ
BUS ACTIVITY
MASTER
S
T
A
R
T
CONTROL
BYTE
X X X X
S 1 0 1 0 X X X 0
SDA LINE
CONTROL
BYTE
DATA (n)
P
A
C
K
N
O
A
C
K
X = Don’t Care Bit
FIGURE 8-3:
S
T
O
P
S 1 0 1 0 X X X 1
A
C
K
A
C
K
BUS ACTIVITY
S
T
A
R
T
WORD
ADDRESS (n)
SEQUENTIAL READ
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
S
T
O
P
DATA n + X
P
SDA LINE
BUS ACTIVITY
A
C
K
DS21178C-page 3-8
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A
C
K
A
C
K
A
C
K
N
O
A
C
K
 1998 Microchip Technology Inc.
24AA00/24LC00/24C00
NOTES:
 1998 Microchip Technology Inc.
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DS21178C-page 3-9
24AA00/24LC00/24C00
24XX00 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
24xx00 —
/P
Package:
Temperature
Range:
Device:
P
SN
ST
OT
=
=
=
=
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body)
TSSOP, 8-lead
SOT-23, 5-lead
Blank = 0°C to +70°C
I = –40°C to +85°C
E = –40°C to +125°C
24AA00
24AA00T
24LC00
24LC00T
24C00
24C00T
128 bit 1.8V I2C Serial EEPROM
128 bit 1.8V I2C Serial EEPROM (Tape and Reel)
128 bit 2.5V I2C Serial EEPROM
128 bit 2.5V I2C Serial EEPROM (Tape and Reel)
128 bit 5.0V I2C Serial EEPROM
128 bit 5.0V I2C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Web Site (www.microchip.com)
DS21178C-page 3-10
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 1998 Microchip Technology Inc.
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Atlanta
Microchip Asia Pacific
Unit 2101, Tower 2
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
ASIA/PACIFIC
Hong Kong
ASIA/PACIFIC (continued)
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Tel: 86-10-85282100 Fax: 86-10-85282104
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
India
Denmark
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Korea
Germany
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Shanghai
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Italy
11/15/99
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
 1999 Microchip Technology Inc.
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