AD AD5235BRU250

PRELIMINARY TECHNICAL DATA
a
Nonvolatile Memory, Dual 1024
Position Digital Potentiometers
AD5235
FEATURES
Dual, 1024 Position Resolution
25K, 250K Ohm Terminal Resistance with 50ppm/°C Tempco
Nonvolatile Memory Preset
SPI Compatible Serial Data Input with Readback Function
Increment/Decrement Commands, Push Button Command
+3 to +5V Single Supply Operation
±2.5V Dual Supply Operation
30 bytes of general purpose nonvolatile memory
FUNCTIONAL BLOCK DIAGRAMS
RDAC1
CS
ADDRESS
DECODE
A1
RDAC1
REGISTER
W1
CLK
SDI
B1
SER IAL
IN P U T
R E G IS T E R
EEMEM1
SDO
RDAC2
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
DIP Switch Setting
PR
RDAC2
REGISTER
PWR ON
PRESET
A2
W2
B2
WP
RDY
EEMEM
CONTROL
V SS
EEMEM2
G ND
G ND
SPARE
EEMEM
GENERAL DESCRIPTION
The AD5235 provides a dual channel, digitally controlled variable
resistor (VR) with resolutions of 1024 positions. These devices
perform the same electronic adjustment function as a potentiometer or
variable resistor. The AD5235’s versatile programming via a Micro
Controller allows multiple modes of operation and adjustment.
In the direct program mode a predetermined setting of the RDAC
register can be loaded directly from the micro controller. Another key
mode of operation allows the RDAC register to be refreshed with the
setting previously stored in the EEMEM register. When changes are
made to the RDAC register to establish a new wiper position, the
value of the setting can be saved into the EEMEM by executing an
EEMEM save operation. Once the settings are saved in the EEMEM
register, these values will be transferred automatically to the RDAC
register to set the wiper position at system power ON. Such operation
is enabled by the internal preset strobe and the preset can also be
accessed externally.
An internal scratch pad RDAC register can be programmed by the
micro controller to set the resistance between terminals W-and-B.
Once the target value is achieved, the RDAC content register can be
placed in the non-volatile memory for automatic recall during Power
Up.
The AD5235 is available in the thin TSSOP-16 package. All parts are
guaranteed to operate over the extended industrial temperature range
of -40°C to +85°C.
REV PrD 6 Nov 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or
other rights of third parties which may result from its use. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices.
V DD
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
Fax:781/326-8703
PRELIMINARY TECHNICAL DATA
AD5235
Nonvolatile Memory Digital Potentiometers
ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS (VDD = +3V±10% or +5V±10% and VSS=0V, VA
= +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL2
R-DNL
RWB, VA=NC
-1
±1/4
+1
LSB
Resistor Nonlinearity2
R-INL
RWB, VA=NC
-2
±1/2
+2
LSB
Nominal resistor tolerance
Resistance Temperature Coefficent
Wiper Resistance
Wiper Resistance
∆R
RAB/∆T
RW
RW
TA = 25°C, VAB = VDD,Wiper (VW) = No connect
VAB = VDD, Wiper (VW) = No Connect
IW = 1 V/R, VDD = +5V
IW = 1 V/R, VDD = +3V
-30
30
%
ppm/°C
Ω
Ω
50
50
200
100
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution
Integral Nonlinearity3
Differential Nonlinearity3
Voltage Divider Temperature Coefficent
Full-Scale Error
Zero-Scale Error
N
INL
DNL
∆VW/∆T
VWFSE
VWZSE
10
–2
–1
Code = Half-scale
Code = Full-scale
Code = Zero-scale
–3
0
±1/2
±1/4
15
-1
+1
+2
+1
+0
+3
Bits
LSB
LSB
ppm/°C
LSB
LSB
RESISTOR TERMINALS
Voltage Range4
VA,B,W
Capacitance5 Ax, Bx
CA,B
f = 1 MHz, measured to GND, Code = Half-scale
Capacitance5 Wx
CW
f = 1 MHz, measured to GND, Code = Half-scale
Common-mode Leakage Current7
ICM
VA = VB = VDD/2
Input Logic High
Input Logic Low
Output Logic High
Output Logic High
Output Logic Low
Input Current
VIH
VIL
VOH
VOH
VOL
IIL
with respect to GND
with respect to GND
RPULL-UP = 2.2KΩ to +5V
IOH = 40µA, VLOGIC = +5V
IOL = 1.6mA, VLOGIC = +5V
VIN = 0V or VDD
Input Capacitance5
CIL
VSS
VDD
45
60
0.01
V
pF
pF
1
µA
0.3•VDD
V
V
V
V
V
µA
DIGITAL INPUTS & OUTPUTS
0.7•VDD
4.9
4
0.4
±1
5
pF
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0V
2.7
5.5
V
Dual-Supply Power Range
Positive Supply Current
Programming Mode Current
Read Mode Current
Negative Supply Current
VDD/VSS
IDD
IDD(PG)
IDD(READ)
ISS
VSS = 0V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND, VDD = 2.5V, VSS = -2.5V
±2.2
±2.7
20
10
V
µA
mA
µA
µA
Power Dissipation6
Power Supply Sensitivity
PDISS
PSS
VIH = VDD or VIL = GND
∆VDD = +5V ±10%
0.05
0.01
mW
%/%
Bandwidth –3dB
Total Harmonic Distortion
VW Settling Time
BW_25K
THDW
tS
R = 12KΩ
VA =1Vrms, VB = 0V, f=1KHz
VA= VDD, VB=0V, 50% of final value
400
0.003
KHz
%
Resistor Noise Voltage
eN_WB
25K/250K
RWB = 10KΩ, f = 1KHz
0.6/3/6
9
µs
nV√Hz
Crosstalk
CT
2
15
650
0.002
DYNAMIC CHARACTERISTICS5, 7
VA = VDD, VB = 0V, Measue VW with adjacent
VR making full scale change
-65
dB
REV PrD 6 NOV, 2000
2
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5235
Nonvolatile Memory Digital Potentiometers
ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS (VDD = +3V±10% to +5V±10% and VSS=0V, VA
= +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 8)
Clock Cycle Time
Input Clock Pulse Width
CS Setup Time
Data Setup Time
Data Hold Time
CLK Shutdown Time
CS Rise to Clock Rise Setup
CS High Pulse Width
CLK to SDO Propagation Delay9
Store to Nonvolatile EEMEM Save Time10
CS to SDO - SPI line acquire
CS to SDO - SPI line release
RDY Rise to CLK Rise
Startup Time
CLK Setup Time
Preset Pulse Width
t1
t 2, t 3
t4
t5
t6
t7
t8
t9
t 10
t 11
t 12
t 13
t 14
t 15
t 16
tPR
20
10
10
5
5
0
10
10
1
Clock level high or low
From Positive CLK transition
From Positive CLK transition
RL = 1KΩ, CL < 20pF
Applies to Command 2H, 3H
25
25
For 1 CLK period (t4 - t3 = 1 CLK period)
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ms
ns
ns
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Typicals represent average readings at +25°C and VDD = +5V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step
change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. IW = VDD/R for both VDD=+3V or VDD=+5V.
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.
Resistor terminals A,B,W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
PDISS is calculated from (IDD x VDD=+5V).
All dynamic characteristics use VDD = +5V.
See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are
measured using both VDD = +3V or +5V.
Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text.
Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms.
Timing Diagram
CLK
t 16
t1
t3
t8
t2
t7
t4
CS
t9
t5
SDI
t6
SDO
LSB
MSB
t 12
t 10
1
t 13
LSB
MSB
S D O2
LSB
MSB
t 14
t 15
RDY
SDO 1 CLK IDLES LOW
t 11
SDO 2 CLK IDLES HIGH
Figure 1. Timing Diagram
REV PrD 6 NOV, 2000
3
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5235
Nonvolatile Memory Digital Potentiometers
AD5235 PIN CONFIGURATION
Absolute Maximum Rating (TA = +25°C, unless otherwise
noted)
VDD to GND..............................................................-0.3, +7V
VSS to GND ................................................................. 0V, -7V
VDD to VSS ......................................................................... +7V
VA, VB, VW to GND ................................................. VSS, VDD
AX – BX, AX – WX, BX – WX ...................................... ±20mA
Ox to GND...................................................................0V, VDD
Digital Inputs & Output Voltage to GND .................. 0V, +7V
Operating Temperature Range......................... -40°C to +85°C
Maximum Junction Temperature (TJ MAX)...................+150°C
Storage Temperature ..................................... -65°C to +150°C
Lead Temperature (Soldering, 10 sec)..........................+300°C
Thermal Resistance θJA,
TSSOP-16...................................................... 180°C/W
Model
#CHs/
k Ohm
AD5235BRU25 X2/25
AD5235BRU250 X2/250
Temp
Range
Package
Package
Description Option
-40/+85°C TSSOP-16
-40/+85°C TSSOP-16
The AD5235 contains 16,000 transistors.
Die size: 100 x 105 mil = 10,500 sq. mil
RU-16
RU-16
1
16 RDY
SDI
2
15 CS
SDO
3
14 PR
GND
4
13 WP
VSS
5
12 VDD
A1
6
11 A2
W1
7
10 W2
B1
8
9
B2
AD5235 PIN FUNCTION DESCRIPTION
# Name
Description
1
CLK
Serial Input Register clock pin. Shifts in one bit at
a time on positive clock edges.
2
SDI
Serial Data Input Pin. Shifts in one bit at a time
on positive clock CLK edges.
3
SDO
Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
and 10 activate the SDO output. See Instruction
operation Truth Table. Table 2.
4
GND
Ground pin, logic ground reference
5
VSS
Negative Supply. Connect to zero volts for single
supply applications.
Package Power Dissipation = (TJMAX - TA) / θJA
Ordering Guide
CLK
6
A1
A terminal of RDAC1.
7
W1
Wiper terminal of RDAC1,
ADDR(RDAC1) = 0H.
8
B1
B terminal of RDAC1.
9
B2
B terminal of RDAC2.
10
W2
Wiper terminal of RDAC2,
ADDR(RDAC3) = 1H.
11
A2
A terminal of RDAC2.
12
VDD
Positive Power Supply Pin. Should be ≥ the
input-logic HIGH voltage.
13
WP
Write Protect Pin. Prevents any changes to the
present EEMEM contents when active low.
14
PR
Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of the
EEMEM register. Factory default loads midscale
51210.
15
CS
Serial Register chip select active low. Serial
register operation takes place when CS returns to
logic high.
16
RDY
Ready. Active-high open drain output. Identifies
completion of commands 2, 3, 8, 9, 10.
REV PrD 6 NOV, 2000
4
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5235
Nonvolatile Memory Digital Potentiometers
OPERATIONAL OVERVIEW
•
The AD5235 digital potentiometer is designed to operate as a true
variable resistor replacement device for analog signals that remain
within the terminal voltage range of VSS<VTERM<VDD. The basic
voltage range is limited to a VDD - VSS<5.5V. Control of the digital
potentiometer allows both scratch pad register (RDAC register)
changes to be made, as well as 100,000 times of nonvolatile
electrically erasable memory (EEMEM) register operations. The
EEMEM update process takes approximately 20.2ms, during this
time the shift register is locked preventing any changes from taking
place. The RDY pin flags the completion of this EEMEM save.
The EEMEM retention is designed to last 10 years without refresh.
The scratch pad register can be changed incrementally by using the
software controlled Increment/Decrement instruction or the Shift
Left/Right instruction command. Once an Increment, Decrement or
Shift command has been loaded into the shift register, subsequent
CS strobes will repeat this command. This is useful for push button
control applications. Alternately the scratch pad register can be
programmed with any position value using the standard SPI serial
interface mode by loading the representative data word. The
scratch pad register can be loaded with the current contents of the
nonvolatile EEMEM register under the program control. At system
power ON, the default value of the scratch pad memory is the value
previously saved in the EEMEM register. The factory EEMEM
preset value is midscale 51210.
•
A serial data output pin is available for daisy chaining and for
readout of the internal register contents. The serial input data
register uses a 24-bit instruction/address/data WORD. The writeprotect (WP) pin provides a hardware EEMEM protection feature
disabling any changes of the present EEMEM contents.
SERIAL DATA INTERFACE
The AD5235 contains a four-wire SPI compatible digital interface
(SDI, SDO, CS, and CLK). Key features of this interface include:
•
•
Permanent storage of the present scratch pad RDAC register
values into the corresponding EEMEM register
30 bytes of user addressable electrical-erasable memory
The serial interface of AD5235 digital potentiometer uses a 24-bit
serial word loaded with MSB first. The format of the SPI
compatible word is shown in Table 1. The Command Bits (Cx)
control the operation of the digital potentiometer according to the
command instruction shown in Table 2. The Address Bits (Ax)
determine which register is activated. The Data Bits (Dx) are the
values that are loaded into the decoded register. The last
instruction executed prior to a period of no programming activity
should be the NOP instruction. This will place the internal logic
circuitry in a minimum power dissipation state.
PR
V A L ID
CO MMAND
CO UNTER
C LK
CO MMAND
PROCESSOR
& ADDRESS
DECODE
+5V
R P U L LU P
S E R IA L
R E G IS T E R
SDO
CS
GND
SDI
Figure 2. Equivalent Digital Input-Output Logic
The equivalent serial data input and output logic is shown in figure
2. The open drain output SDO is disabled whenever chip select CS
is logic high. The SPI interface can be used in two slave modes
CPHA=1, CPOL=1 and CPHA=0, CPOL=0. CPHA and CPOL
refer to the control bits, which dictate SPI timing in the following
microprocessors/MicroConverters: ADuC812/824, M68HC11, and
MC68HC16R1/916R1.
Independently Programmable Read & Write to all registers
Direct parallel refresh of all RDAC wiper registers from
corresponding EEMEM registers
Table 1. AD5235 24-bit Serial Data Word
M
S
B
AD5235
C3 C2 C1 C0 A3 A2 A1 A0 X
X
X
X
X
X
D9 D8 D7 D6 D5 D4
Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in table 2.
D3
D2
D1
L
S
B
D0
REV PrD 6 NOV, 2000
5
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5235
Nonvolatile Memory Digital Potentiometers
Table 2. AD5235 Instruction/Operation Truth Table
Inst
No.
Data Byte 1
B15 •••• B8
X ••• D9 D8
X ••• X X
Data Byte 0
B7 ••• B0
D7 ••• D0
X ••• X
Operation
0
Instruction Byte 1
B15 •••••••••••••••• B8
C3 C2 C1 C0 A3 A2 A1 A0
0 0 0 0 X X X X
1
0
0
0
1
<< ADDR >>
X ••• X
X
X
••• X
Write contents of EEMEM(ADDR) to RDAC(ADDR)
Register
2
0
0
1
0
<< ADDR >>
X ••• X
X
X
••• X
SAVE WIPER SETTING: Write contents of
RDAC(ADDR) to EEMEM(ADDR)
3
0
0
1
1
<< ADDR >>
X ••• D9 D8
D7 ••• D0
Write contents of Serial Register Data Byte 0 & 1 to
EEMEM(ADDR)
4
0
1
0
0
<< ADDR >>
X ••• X
X
X
••• X
DEC 6dB: Right Shift contents of RDAC(ADDR) ,
LSB rolls over to MSB position
5
0
1
0
1
X
X
X ••• X
X
X
••• X
DEC All 6dB: Right Shift contents of all RDAC
Registers, LSB rolls over to MSB position
6
0
1
1
0
<< ADDR >>
X ••• X
X
X
••• X
Decrement contents of RDAC(ADDR) by One, does
not rollover at zero-scale
7
0
1
1
1
X
X
X
X
X ••• X
X
X
••• X
Decrement contents of all RDAC Registers by One,
does not rollover at zero-scale
8
1
0
0
0
0
0
0
0
X ••• X
X
X
••• X
RESET: Load all RDACs with their corresponding
EEMEM previously-saved values
9
1
0
0
1
<< ADDR >>
X ••• X
X
X
••• X
Write contents of EEMEM(ADDR) to Serial Register
Data Byte 0 & 1
10
1
0
1
0
<< ADDR >>
X ••• X
X
X
••• X
Write contents of RDAC(ADDR) to Serial Register
Data Byte 0 & 1
11
1
0
1
1
<< ADDR >>
X ••• D9 D8
D7 ••• D0
Write contents of Serial Register Data Byte 0 &1 to
RDAC(ADDR)
12
1
1
0
0
<< ADDR >>
X ••• X
X
X
••• X
INC 6dB: Left Shift contents of RDAC(ADDR), stops
at all 'Ones'.
13
1
1
0
1
X
X
X ••• X
X
X
••• X
INC All 6dB: Right Shift contents of all RDAC
Registers, stops at all 'Ones'.
14
1
1
1
0
<< ADDR >>
X ••• X
X
X
••• X
Increment contents of RDAC(ADDR) by One, does
not rollover at full-scale stops at all 'Ones'.
15
1
1
1
1
X
X ••• X
X
X
••• X
Increment contents of all RDAC Registers by One,
does not rollover at full-scale stops at all 'Ones'.
X
X
X
X
X
X
X
NOP: Do nothing
NOTES:
1. The SDO output shifts-out the last 24-bits of data clocked into the serial register for daisy chain operation. Exception,
following Instruction #9 or #10 the selected internal register data will be present in data byte 0 & 1. Instructions following
#9 & #10 must be a full 24-bit data word to completely clock out the contents of the serial register.
2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile
EEMEM register.
3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high.
.
REV PrD 6 NOV, 2000
6
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5235
Nonvolatile Memory Digital Potentiometers
Detail Potentiometer Operation
The actual structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. The RDAC contains a
string of connected resistor segments, with an array of analog
switches that act as the wiper connection to several points along the
resistor array. The number of points is the resolution of the device.
The AD5235 has 1024 connection points allowing it to provide
better than 0.5% set-ability resolution. Figure 3 provides an
equivalent diagram of the connections between the three terminals
that make up one channel of the RDAC. The SWA and SWB will
always be ON while one of the switches SW(0) to SW(2N-1) will
be ON one at a time depends upon the resistance step decoded from
the Data Bits. Note that there are two 50Ω wiper resistances, RW.
The resistance contributed by RW must be accounted for when
calculating the output resistance. RW is the sum of the resistances of
SWA + SWX and SWB + SWX for A-to-Wiper and B-to-Wiper
respectively.
SW A
AX
ladder until the last tap point is reached at RWB=25025Ω. See figure
3 for a simplified diagram of the equivalent RDAC circuit.
The general equation, which determines the digitally programmed
output resistance between Wx and Bx, is:
RWB(Dx) = (Dx/2N) * RAB + RW
eqn. 1
Where N is the resolution of the VR, Dx is the data contained in
the RDACx latch, and RAB is the nominal end-to-end resistance.
Since N=10 and RW=50Ω for AD5235, eqn. 1 becomes:
RWB(Dx) = (Dx/1024) * RAB + 50Ω
eqn. 2
For example, when VB = 0V and A–terminal is open circuit the
following output resistance values will be set for the following
RDAC latch codes (applies to RAB=25KΩ potentiometers):
Dx
(DEC)
RWB
(Ω)
Output State
1023
512
1
0
25025Ω
12500Ω
74Ω
50Ω
Full-Scale
Mid-Scale
1 LSB
Zero-Scale (Wiper contact resistance)
SW(2 N -1)
RDAC
WX
RS
WIPER
SW(2 N -2)
REGISTER
&
DECODER
Note that in the zero-scale condition a finite wiper resistance of
50Ω is present. Care should be taken to limit the current flow
between W and B in this state to no more than 20mA to avoid
degradation or possible destruction of the internal switch contact.
RS
SW(1 )
RS
SW(0 )
N
RS = R AB /2
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
SW B
BX
Figure 3. Equivalent RDAC structure
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and B
are available with values of 25KΩ, and 250KΩ. The final digits of
the part number determine the nominal resistance value, e.g., 25KΩ
= 25; 250KΩ = 250. The nominal resistance (RAB) of the AD5235
VR has 1024 contact points accessed by the wiper terminal, plus
the B terminal contact. The 10-bit data word in the RDAC latch is
decoded to select one of the 1024 possible settings. The wiper's
first connection starts at the B terminal for data 00H. This B–
terminal connection has a wiper contact resistance, RW of 50Ω,
regardless of what the nominal resistance RAB is. The second
connection (25KΩ part) is the first tap point where RWB =74Ω [RWB
=RAB/1024 + RW = 24Ω+50Ω)] for data 01H. The third connection
is the next tap point representing RWB =49+50=99Ω for data 02H.
Each LSB data value increase moves the wiper up the resistor
Figure 4. Symmetrical RDAC Operation
Like the mechanical potentiometer the RDAC replaces, the
AD5235 part is totally symmetrical. The resistance between the
wiper W and terminal A also produces a digitally controlled
resistance RWA. Figure 4 shows the symmetrical programmability
of the various terminal connections. When these terminals are used,
the B–terminal should be tied to the wiper. Setting the resistance
value for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch is increased in value. The
general equation for this operation is:
REV PrD 6 NOV, 2000
7
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5235
Nonvolatile Memory Digital Potentiometers
RWA(Dx) = [ (2N-Dx)/2N ] * RAB + RW
eqn. 3
ESD PROTECTION CIRCUITS
VDD
Similarly, eqn. 3 becomes:
RWA(Dx) = [ (1024-Dx)/1024 ] * RAB + 50Ω
For example, when VA = 0V and B–terminal is tied to the wiper W
the following output resistance values will be set for the following
RDAC latch codes (applies to RAB=10KΩ potentiometers):
Dx
(DEC)
RWA
(Ω)
IN P U T S
eqn. 4
L O G IC
P IN S
Output State
GND
Figure 5A. Equivalent Digital Input ESD Protection
1023
512
1
0
74
12500
25000
25050
Full-Scale
Mid-Scale
1 LSB
Zero-Scale
V DD
O UTPU TS
O1 & O2
P IN S
A ±1% typical distribution of RAB from channel-to-channel occurs
within the same package. On the other hand, device to device
matching is process lot dependent such that a maximum of ±30%
variation is possible. The change in RAB with temperature has a 50
ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal. For
example connecting A–terminal to +5V and B–terminal to ground
produces an output voltage at the wiper which can be any value
starting at zero volts and up to 1 LSB less than +5V. Each LSB of
voltage is equal to the voltage applied across terminal AB divided
by the 2N resolution of the potentiometer divider. The general
equation defining the output voltage with respect to ground for any
given input voltage applied to terminals AB is:
GND
Figure 5B. Equivalent Digital Output ESD Protection
VDD
O U TPUTS
SDO
P IN
VW(Dx) = Dx/2N * VAB + VB eqn. 5
GND
Since N=10,
VW(Dx) = (Dx/1024) * VAB + VB
Figure 5C. Equivalent SDO Output ESD Protection Circuit
eqn. 6
Operation of the digital potentiometer in the divider mode results in
more accurate operation over temperature. Here the output voltage
is dependent on the ratio of the internal resistors and not the
absolute value. Therefore, the drift reduces to 15ppm/°C.
Figure 5 shows the equivalent ESD protection circuit for digital
pins. Figure 6 shows the equivalent analog-terminal protection
circuit for the variable resistors.
P O T E N T IO M E T E R
T E R M IN A L S
A, B, W
P IN S
V SS
Figure 6. Equivalent VR-Terminal ESD Protection
REV PrD 6 NOV, 2000
8
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5235
Nonvolatile Memory Digital Potentiometers
TEST CIRCUITS
Figures 7 to 15 define the test conditions used in the product
specification's table.
Figure 12. Non-Inverting Gain test circuit
Figure 7. Potentiometer Divider Nonlinearity error test circuit
(INL, DNL)
Figure 13. Gain Vs Frequency test circuit
Figure 8. Resistor Position Nonlinearity Error (Rheostat Operation;
R-INL, R-DNL)
Figure 14. Incremental ON Resistance Test Circuit
Figure 9. Wiper Resistance test Circuit
Figure 15. Common Mode Leakage current test circuit
Figure 10. Power supply sensitivity test circuit (PSS, PSSR)
TYPICAL PERFORMANCE GRAPHS
TBD
Figure 11. Inverting Gain test Circuit
REV PrD 6 NOV, 2000
9
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers
AD5235
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
REV PrD 6 NOV, 2000
10
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com