To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Description The 32180 Group is a 32-bit, single-chip RISC microcomputer with built-in flash memory, which was developed for use in general industrial and household equipment. To accomplish high-precision arithmetic operations, it incorporates a fully IEEE754 compliant, single-precision FPU. This microcomputer contains a variety of peripheral functions ranging from two independent blocks of 16-channel AD converters to 64-channel multifunction timers, 10-channel DMACs, 6-channel serial I/Os, and 1-channel real-time debugger. Also included are 2-channel Full-CAN modules and JTAG (boundary scan facility). With the software necessary to run these numerous peripheral functions stored in its large-capacity flash memory, this microcomputer meets the needs of application systems for high functionality, highperformance arithmetic capability, and sophisticated control. With lower power consumption and low noise characteristics also considered, these microcomputers are ideal for embedded equipment applications. Features M32R-FPU core • Uses the M32R family RISC CPU core (M32R family common instruction set + single-precision FPU/extended instructions) • Five-stage pipelined processing • Sixteen 32-bit general-purpose registers • 16-bit/32-bit instructions implemented • DSP function instructions (sum-of-products calculation using 56-bit accumulator) • Built-in single-precision FPU (fully compliant with IEEE754 standard: four rounding modes, etc.) • Bit manipulation extended instructions • Built-in flash memory .....................1M bytes (1024K bytes) • Built-in flash programming boot program • Built-in RAM ....................................................... 48K bytes • PLL clock generating circuit.............. Built-in x 8 PLL circuit • Oscillation stop detection function • Maximum operating frequency of the CPU clock Type Name Frequency Temperature range M32180F8VFP M32180F8TFP 64MHz 80MHz -40°C to +125°C -40°C to +85°C • Single power supply: 5 V (+ 0.5 V) or 3.3 V (+ 0.3 V) 64-channel multijunction timers (MJT) Multifunction timers are incorporated that support various purposes of use. 16-bit output related timers (TOP) ................... 11 channels 16-bit input/output related timers (TIO)............ 10 channels 16-bit input related timers (TMS) ....................... 8 channels 16-bit input related up/down-timers (TID) .......... 3 channels 24-bit output related timers (TOU) ................... 24 channels 32-bit input related timers (TML) ....................... 8 channels • Flexible configuration is possible through interconnection of timers. • The internal DMAC and A-D converter can be started by a timer. • Built-in PWM output cut function for motor control (TOU) Real-time Debugger • Includes dedicated clock-synchronized serial I/O that can read and write the contents of the internal RAM independently of the CPU. • Can look up and update the data table in real time while the program is running. • Can generate a dedicated interrupt based on RTD communication. Abundant internal peripheral functions In addition to the timers and real-time debugger, the microcomputer contains the following peripheral functions. • DMAC ............................................................. 10 channels • A-D converters (Sample & hold mode, Disconnection detector assist function, Injection current bypass circuit) ................................16 channels 10-bit converter x 2 • Serial I/O ........................................................... 6 channels • Interrupt controller: 32 interrupt sources, 8 priority levels • Wait controller • Full CAN (CAN Specification 2.0B active)......... 2 channels • Virtual-Flash emulation function .......... 4K bytes x 8 banks • JTAG (boundary scan function, Mitsubishi original SDI debug function) • Port input threshold level select function Designed to operate at high temperatures To meet the need for use at high temperatures, M32180F8VFP is designed to be able to operate in the temperature range of -40 to +125°C when CPU clock operating frequency = 64 MHz. M32180F8TFP is designed to be able to operate in the temperature range of –40 to +85°C when CPU clock operating frequency = 80 MHz. Applications Automobile equipment control (e.g., Engine, ABS, and AT), industrial equipment system control, and high-function OA equipment (e.g., PPC) Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P67 P210/TO37 P211/TO38 P212/TO39 P213/TO40 P214/TO41 P215/TO42 P216/TO43 P217/TO44 P160/TO21 P161/TO22 P162/TO23 P163/TO24 P164/TO25 P165/TO26 P166/TO27 P167/TO28 VSS VCCE VCC-BUS P226/CS2# P227/CS3# P44/CS0# P45/CS1# P224/A11/CS2# P225/A12/CS3# P46/A13 P47/A14 P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 VSS P20/A23 P21/A24 P22/A25 P23/A26 P24/A27 P25/A28 P26/A29 P27/A30 VCC-BUS VSS VCCE P93/TO16 P94/TO17 P95/TO18 P96/TO19 Pin Assignment(top view) 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 M32180F8VFP M32180F8TFP 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P97/TO20 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 P147/TIN15 P146/TIN14 P145/TIN13 P144/TIN12 P143/TIN11 P142/TIN10 P141/TIN9 P140/TIN8 P197/TIN33/PWMOFF2 P196/TIN32 P195/TIN31 P194/TIN30 P193/TIN29 P192/TIN28 P191/TIN27 P190/TIN26 P127/TCLK3 P126/TCLK2 P125/TCLK1 P124/TCLK0 EXCVCC VSS VCCE VSS VSS VSS SBI# P63 P62 P61 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 VREF0 AVCC0 VSS VCCE AVCC1 VSS VCCE P150/TIN0 P151/TIN1 P152/TIN2 P153/TIN3 P154/TIN4 P155/TIN5 P156/TIN6 P157/TIN7 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 P220/CTX0 P221/CRX0 P222/CTX1 P223/CRX1 VCCE OSC-VSS VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P180/TO29 P181/TO30 P182/TO31 P183/TO32 P184/TO33 P185/TO34 P186/TO35 P187/TO36 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI JTDO JTRST JTCK JTMS P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P173/TIN25 P172/TIN24 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE VCC-BUS P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 P12/DB10 P11/DB9 P10/DB8 P07/DB7 P06/DB6 P05/DB5 P04/DB4 P03/DB3 P02/DB2 P01/DB1 P00/DB0 VSS P73/HACK# P72/HREQ# P71/WAIT# P70/BCLK/WR# P43/RD# P42/BHW#/BHE# P41/BLW#/BLE# VCC-BUS VSS AD1IN15 AD1IN14 AD1IN13 AD1IN12 AD1IN11 AD1IN10 AD1IN9 AD1IN8 AVSS1 AD1IN7 AD1IN6 AD1IN5 AD1IN4 AD1IN3 AD1IN2 AD1IN1 AD1IN0 VREF1 Package 240P6Y-A(0.5mm pitches) Note: It is shown that the pin (signal) with which "#" sticks to the last of a pin name (signal name) is "L" active pin (signal). Figure 1. Pin Layout Diagram 2 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal bus interface M32R-FPU core (max. 80MHz) DMAC (10 channels) Internal RAM (48K bytes) A-D converter x 2 (A-D0 : 10-bit,16 channels) (A-D1 : 10-bit,16 channels) Internal 16-bit bus Internal flash memory (1M bytes=1024K bytes) Input/output timer (64 channels) Internal 32-bit bus Single-precision FPU (fully IEEE754 compliant) Internal 32-bit bus Multiplier accumulator (32x16+56) Serial I/O (6 channels) Interupt controller (8 priority levels) Wait controller Real-time debugger (RTD) Full CAN (2 channels) PLL clock generation circuit Internal power supply generation circuit (VDC) External bus interface Data Address Input/output port 158 ports Figure 2. Block diagram 3 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 1. Outline Performance Functional Block Features M32R-FPU core External data bus Instruction set Internal flash memory Internal RAM DMAC Multijunction timer A-D converter Serial I/O Real-time Debugger (RTD) Interrupt controller Wait controller CAN JTAG Clock Power Supply Voltage Operating temperature range Package M32R family CPU core, internally configured in 32-bit Built-in multiplier-accumulator (32 x 16 + 56) Basic bus cycle M32180F8VFP: 15.625 ns (CPU clock frequency at 64 MHz, Internal peripheral clock frequency at 16MHz) M32180F8TFP: 12.5 ns (CPU clock frequency at 80 MHz, Internal peripheral clock frequency at 20MHz) Logical address space: 4G bytes, linear General-purpose register: 32-bit register x 16, Control register: 32-bit register x 6 Accumulator: 56-bit 16-bit data bus 16-bit/32-bit instruction formats 100 discrete instructions in six addressing modes 1024K bytes Rewrite durability: 100 times 48K bytes 10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral I/O and internal RAM, and between internal RAMs) Channels can be cascaded and can operate in combination with internal peripheral I/O 64 channels of multijunction timers. TOP : 16-bit output related timer, 11 channels (single-shot, delayed single-shot, and continuous) TIO : 16-bit input/output related timer, 10 channels (measure clear/measure free-run/noise processing input, PWM/ single-shot/delayed single-shot/continuous output) TMS : 16-bit input related timer, 8 channels (measure input) TID : 16-bit input related up/down-timer, 3 channels (fixed period, event count, up/down event count, x4 count) TOU : 24-bit output related timer, 24 channels (PWM, single-shot PWM, delayed single-shot, single-shot, continuous) Note: Functions as a 16-bit timer when in PWM or one-shot PWM mode TML : 32-bit input related timer, 8 channels (measure input) Flexible timer configuration is possible through interconnection of channels using the clock bus or event bus. 2 independent 10-bit multifunction A-D converters • Input 16 channels x 2 • Scan-based conversion can be switched between N (N = 1 to 16) channels • Capable of interrupt conversion during scan • 8-bit/10-bit readout function available with sample & hold mode • Disconnection detector assist function • Injection current bypass circuit 6 channels (The serial I/Os can be set for synchronous serial I/O or UART. SIO2, SIO3 are UART mode only) 1-channels dedicated clock-synchronized serial H’0080 4000 to H’0080 FFFF: internal RAM area Can access the internal RAM for read/rewrite from outside independently of the CPU, and also generate an exclusive-use interrupt. Controls interrupts from internal peripheral I/Os (Priority can be set to one of 8 levels including interrupt disabled) Controls wait when accessing external extended area (Chip selects for four external extended areas each can have access extended for 0–7 wait cycles plus WAIT# signal entered from external source) (Note1) Two channels, each having 16-channel message slots Boundary-Scan function, Built-in SDI debugger function in MITSUBISHI M32180F8VFP: CPU clock: maximum 64 MHz (for CPU, internal ROM, and internal RAM access) Internal peripheral clock (BCLK): maximum 16 MHz (for peripheral module access) External input clock (XIN): maximum 8.0 MHz, built-in x8 PLL circuit M32180F8TFP: CPU clock: maximum 80 MHz (for CPU, internal ROM, and internal RAM access) Internal peripheral clock (BCLK): maximum 20 MHz (for peripheral module access) External input clock (XIN): maximum 10.0 MHz, built-in x8 PLL circuit 5 V (+ 0.5 V) or 3.3 V (+ 0.3 V) [T.B.D]: single power supply voltage (The internal logic operates with 2.5 V, however) M32180F8VFP: -40 to +125°C (CPU clock 64MHz, internal peripheral clock 16MHz) (Note2) M32180F8TFP: -40 to +85°C (CPU clock 80MHz, internal peripheral clock 20MHz) 0.5mm pitches / 240-pin QFP package (240P6Y-A) Note 1: Wait Cycle by the external WAIT# input is not received when 0wait is selected. Moreover, as for all idol setup after the wait / strike robe / recovery / lead of CS block, only operation by "nothing" setup is guaranteed when 0wait is selected. Note 2: This does not mean that the microcomputer is guaranteed for continuous operation at 125°C. If 125°C applications are desired, please consult Mitsubishi. 4 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 5 XIN XOUT Clock P101/TO9/TXD3 P102/TO10/CTX1 2 Port11 P124/TCLK0-P127/TCLK3 Port12 4 Mode 8 Port1 P10/DB8-P17/DB15 8 6 P132/TIN18-P137/TIN23 Port2 P20/A23-P27/A30 8 8 P140/TIN8-P147/TIN15 Port14 Port3 P30/A15-P37/A22 8 8 P150/TIN0-P157/TIN7 Port15 P160/TO21-P167/TO28 Port16 P131/TIN17/PWMOFF1 8 P41/BLW#/BLE# P42/BHW#/BHE# 2 P174/TXD2 P44/CS0# P175/RXD2 P45/CS1# P46/A13, P47/A14 P61-P63 Port6 2 3 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P67 P70/BCLK/WR# P71/WAIT# Bus Control P72/HREQ# Port7 P73/HACK# P74/RTDTXD P75/RTDRXD RTD 7 P201/RXD4 P202/TXD5 Serial I/O P210/TO37-P217/TO44 Port21 Multijunction timer CAN P222/CTX1 P223/CRX1 P224/A11/CS2# P225/A12/CS3# P226/CS2# Port22 Address bus Bus Control P227/CS3# JTMS P87/SCLKI1/SCLKO1 JTCK SBI# VREF0, VREF1 Multijunction timer Port20 P221/CRX0 P86/RXD1 AVSS0, AVSS1 Port19 P220/CTX0 P85/TXD1 AVCC0, AVCC1 Port18 P203/RXD5 8 P84/SCLKI0/SCLKO0 AD1IN0-AD1IN15 P190/TIN26-P196/TIN32 P200/TXD4 P83/RXD0 A-D converter P180/TO29-P187/TO36 P197/TIN33/PWMOFF2 P82/TXD0 AD0IN0-AD0IN15 Serial I/O P177/RXD3 8 P77/RTDCLK Interrupt Controller Port17 P176/TXD3 P76/RTDACK Port8 Port13 P172/TIN24, P173/TIN25 P43/RD# M32180F8VFP, M32180F8TFP Port4 Multijunction timer P130/TIN16/PWMOFF0 P00/DB0-P07/DB7 Port0 Address Bus Serial I/O CAN P110/TO0-P117/TO7 8 MOD0 MOD1 FP Serial I/O Port10 P103/TO11-P107/TO15 RESET# Bus Control Serial I/O 5 Reset Data Bus Port9 P100/TO8 VCNT OSC-VCC OSC-VSS P93/TO16-P97/TO20 16 JTRST 16 JTDO 2 2 2 VDDE JTAG JTDI 13 7 2 VSS VCCE EXCVCC EXCVDD VCC-BUS 4 Note: It is shown that the pin (signal) with which "#" sticks to the last of a pin name (signal name) is "L" active pin (signal). Figure 3. Pin Function Diagram 5 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 2. Description of Pin Function (1/3) Type Pin Name Description Input/Output Function Power Supply VCCE EXCVCC - Power supply (5.0V + 0.5V or 3.3 V + 0.3V). External capacitance connecting pin. - VSS XIN XOUT Power supply External capacitance connect Bus power supply RAM power supply External capacitance connect Ground Clock input Clock output Input Output Power supply for the bus control pins (5.0V + 0.5V or 3.3 V + 0.3V). Internal RAM backup power supply (5.0V + 0.5V or 3.3 V + 0.3V). Backup power supply for the internal RAM, external capacitance connecting pin. Connect all VSS pins to ground (GND). Clock input/output pins. These pins contain a PLL-based frequency multiply-by-8, so input the clock whose frequency is 1/8 the operating frequency. (XIN input = 10 MHz when CPU clock operates at 80 MHz) BCLK System clock Output OSC-VCC OSC-VSS VCNT Clock power supply Clock ground PLL control Input RESET# MOD0, MOD1 Reset Mode Input Input VCC-BUS VDDE EXCVDD Clock Reset Mode Flash only Address Bus Data bus FP A11-A30 Flash Protect Address bus Input Output DB0-DB15 Data bus Input/output Bus Control CS0#-CS3# RD# WR# BHW# BLW# Chip select Read Write Byte High Write Byte Low Write Output Output Output Output Output BHE# Byte High Enable Output BLE# Byte Low Enable Output WAIT# Wait Input HREQ# Hold request Input HACK# Hold acknowledge Output Note 1: In boot mode, the FP pin must be at the high level. 6 Outputs a clock twice the externally sourced clock frequency, XIN (when the internal CPU memory clock is 80 MHz, BCLK output = 20 MHz). Use this output when external sync design is desired. Power supply to the PLL circuit. Connect OSC-VCC to the power supply Connect OSC-VSS to ground. This pin controls the PLL circuit. Connect a resistor and capacitor to this pin. This pin resets the internal circuits. These pins set an operation mode. MOD0 MOD1 0 0 1 0 1 0 Mode Single-chip mode Expanded external mode Processor mode (Boot mode) (Note1) 1 1 (Do not select) This pin protects the flash memory against E/W in hardware. To allow four blocks of up to 2 MB memory space each to be added externally, 20-bit address (A11-A30) is provided. A31 is not output. This is a 16-bit data bus connecting to an external device. During write cycle, the microcomputer outputs BHW# or BLW# to indicate the valid byte write position of the 16-bit data bus. During read cycle, the microcomputer always reads the full 16-bit data bus. Transferred to the internal circuit of the M32R, however, is the data at only the valid byte position. Chip select signals for external devices. This signal is output when reading external devices. This signal is output when writing external devices. Indicates the byte positions to which valid are transferred when writing to external devices. BHW#/BHE# and BLW#/BLE# correspond to the upper address side (DB0-DB7 effective) and the lower address side (DB8-DB15 effective), respectively. For external device access, it indicates that the upper byte data (DB0DB7) is valid. For external device access, it indicates that the lower byte data (DB8DB15) is valid. If WAIT# input is low when the M32R accesses external devices, the wait cycle extended. This pin is used by an external device to request control of the external bus. The M32R goes to a hold state when HREQ# input is pulled low. This signal indicates to the external device that the M32R has entered a hold state and relinquished control of the external bus. Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 2. Description of Pin Function (2/3) Type Pin Name Description Input/Output Function Multijunction timer TIN0 Timer input Input Input pin for multijunction timer Timer output Output Output pin for multijunction timer TCLK0 -TCLK3 Timer clock Input Clock input pin for multijunction timers. AVCC0, AVCC1 Analog power supply - AVCC0 and AVCC1 are the power supply for the A-D0 converter and AD1 converter, respectively. Connect AVCC0 and AVCC1 to the power supply rail. AVSS0, AVSS1 Analog ground - AVSS0 is the analog ground for the A-D0 converters. AVSS1 is the analog ground for the A-D1 converters. Connect AVSS0, 1 to ground. AD0IN0 -AD0IN15 AD1IN0 -AD1IN15 Analog input Input 16-channel analog input pins for the A-D0 converter in the first block. 16-channel analog input pins for the A-D1 converter in the second block. VREF0, VREF1 Reference voltage input Input VREF0 and VREF1 are the reference voltage input pin for the A-D0 converter and A-D1 converter, respectively. Interrupt controller SBI# System break interrupt Input System break interrupt (SBI) input pin of the interrupt controller Serial I/O SCLKI0/ SCLKO0 UART transmit/receive clock output or CSIO transmit/receive clock input/output Input/output When Channel 0 is in UART mode: Clock output derived from BRG output by dividing it by 2 When Channel 0 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected SCLKI1/ SCLKO1 UART transmit/receive clock output or CSIO transmit/receive clock input/output Input/output When Channel 1 is in UART mode: Clock output derived from BRG output by dividing it by 2 When Channel 1 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected SCLKI 4/ SCLKO4 UART transmit/receive clock output or CSIO transmit/receive clock input/output Input/output When Channel 4 is in UART mode: Clock output derived from BRG output by dividing it by 2 When Channel 4 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected SCLKI5/ SCLKO5 UART transmit/receive clock output or CSIO transmit/receive clock input/output Input/output When Channel 5 is in UART mode: Clock output derived from BRG output by dividing it by 2 When Channel 5 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected TXD0 Transmit data Output Transmit data output pin of serial I/O channel 0 -TIN33 TO0 -TO44 A-D converter RXD0 Receive data Input Receive data input pin of serial I/O channel 0 TXD1 Transmit data Output Transmit data output pin of serial I/O channel 1 RXD1 Receive data Input Receive data input pin of serial I/O channel 1 TXD2 Transmit data Output Transmit data output pin of serial I/O channel 2 RXD2 Receive data Input Receive data input pin of serial I/O channel 2 TXD3 Transmit data Output Transmit data output pin of serial I/O channel 3 RXD3 Receive data Input Receive data input pin of serial I/O channel 3 TXD4 Transmit data Output Transmit data output pin of serial I/O channel 4 RXD4 Receive data Input Receive data input pin of serial I/O channel 4 TXD5 Transmit data Output Transmit data output pin of serial I/O channel 5 RXD5 Receive data Input Receive data input pin of serial I/O channel 5 7 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 2. Description of Pin Function (3/3) Type Pin Name Description Input/Output Function Real-time Debugger RTDTXD Transmit data Output Serial data output pin of the Real-time Debugger RTDRXD Receive data Input Serial data input pin of the Real-time Debugger RTDCLK Clock input Input Serial data transmit/receive clock input pin of the Real-time Debugger RTDACK Acknowledge Output This pin outputs a low pulse synchronously with the Real-time Debugger’s first clock of serial data output word. The low pulse width indicates the type of the command/data the Real-time Debugger has received. CTX0.CTX1 Transmit data Output Data output pin from CAN module. CRX0, CRX1 Receive data Input Data input pin to CAN module. JTMS Test mode Input Test select input for controlling the test circuit’s state transition JTCK Clock Input Clock input to the debugger module and test circuit. JTRST Test reset Input Test reset input for initializing the test circuit asynchronously. JTDO Serial output Output Serial output of test instruction code or test data. JTDI Serial input Input Serial input of test instruction code or test data. P00-P07 Input/output port0 Input/output Programmable input/output port. P10-P17 Input/output port 1 Input/output Programmable input/output port. P20-P27 Input/output port 2 Input/output Programmable input/output port. P30-P37 Input/output port 3 Input/output Programmable input/output port. P41-P47 Input/output port 4 Input/output Programmable input/output port. P61-P67 Input/output port 6 Input/output Programmable input/output port. (However, P64 is an input-only port) P70-P77 Input/output port 7 Input/output Programmable input/output port. P82-P87 Input/output port 8 Input/output Programmable input/output port. P93-P97 Input/output port 9 Input/output Programmable input/output port. P100- P107 Input/output port 10 Input/output Programmable input/output port. P110- P117 Input/output port 11 Input/output Programmable input/output port. P124 -P127 Input/output port 12 Input/output Programmable input/output port. P130 -P137 Input/output port 13 Input/output Programmable input/output port. P140 -P147 Input/output port 14 Input/output Programmable input/output port. P150 -P157 Input/output port 15 Input/output Programmable input/output port. P160 -P167 Input/output port 16 Input/output Programmable input/output port. P172 -P177 Input/output port 17 Input/output Programmable input/output port. P180 -P187 Input/output port 18 Input/output Programmable input/output port. P190 -P197 Input/output port 19 Input/output Programmable input/output port. P200 -P203 Input/output port 20 Input/output Programmable input/output port. P210 -P217 Input/output port 21 Input/output Programmable input/output port. P220 -P227 Input/output port 22 Input/output Programmable input/output port. (However, P93, P97 is an input-only port) CAN JTAG Input/output Port (Note1) Note 1: Input/output port 5 is reserved for future use. 8 2002-07-12 Rev.1.0 Mitsubishi Microcomputers 32180 Group Under Development Outline of the CPU core The 32180 Group is built around the M32R RISC CPU core, and has the instruction set common to all of the M32R family microcomputers. To achieve high-precision arithmetic operation, this microcomputer additionally incorporates a fully IEEE754 compliant, single-precision FPU. Instructions are processed in five pipelined stages consisting of instruction fetch, decode, execution, memory access, and write back. Thanks to its “out-of-order-completion” mechanism, the M32R CPU allows clock cycle to realize efficient instruction execution control. The M32R CPU internally contains sixteen 32-bit generalpurpose registers. The instruction set consists of 100 discrete instructions, which come in either 16-bit or 32-bit instruction format. Use of the 16-bit instruction format helps to reduce the program code size. Also, the availability of 32-bit instructions facilitates programming and increases the performance at the same clock speed, as compared to architectures with segmented address spaces. Multiply-Accumulate instructions comparable to DSP The M32R-FPU contains a multiplier/accumulator that can execute 32-bit x 16-bit in one cycle. Therefore, it executes a 32-bit x 32-bit integer multiplication instruction in three cycles. Also, the M32R-FPU supports the following four sum-ofproducts instructions (or multiplication instructions) for DSP function use. (1) 16 high-order register bits x 16 high-order register bits (2) 16 low-order register bits x 16 low-order register bits (3) All 32 register bits x 16 high-order register bits (4) All 32 register bits x 16 low-order register bits Furthermore, the M32R-FPU has instructions for rounding the value stored in the accumulator to 16 or 32-bit, and instructions for shifting the accumulator value to adjust digits before storing in a register. Because these instructions also can be executed in one cycle, DSP comparable data processing capability can be obtained by using them in combination with high-speed data transfer instructions such as Load & Address Update or Store & Address Update. FPU instructions (12 instructions) The M32R-FPU supports single-precision, floating-point arithmetic operations fully compliant with IEEE754 standard. More specifically, it supports all of the following five exceptions and four rounding modes. Because the generalpurpose registers are used for floating-point arithmetic, data transfer overhead is reduced. • Five exceptions (invalid operation, division by zero, overflow, underflow, and precision error) • Four rounding modes (round toward nearest, round toward zero, round toward +∞, round toward -∞) SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Also included are the sum-of-product (FMADD) and difference-of-product (FMSUB) instructions suitable for butterfly operation in FFT. Extended instructions (5 instructions) The M32R-FPU has several instructions implemented in it as extended instructions such as those to set, clear, and test bits, those to set and clear data in the processor status register, and those to automatically increment the address in which to store a halfword. Address space The 32180 Group’s logical address is always handled in width of 32-bit, providing a linear address space of up to 4G bytes. The 32180 Group’s address space is divided into the following spaces. User space A 2G-byte area from H’0000 0000 to H’7FFF FFFF is the user space. Located in this space are the user ROM area, external extended area, internal RAM area, and SFR (Special Function Register) area (internal peripheral I/O registers). Of these, the user ROM area and external extended area are located differently depending on mode settings. System space A 2G-byte area from H’8000 0000 to H’FFFF FFFF is the system area. This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user. Built-in flash memory and RAM The M32180F8VFP, M32180F8TFP Group contains 1M bytes (= 1,024K bytes) flash memory and 48K bytes RAM. The internal flash memory can be programmed while being mounted on the printed circuit board (on-board programming). Use of flash memory allows the same chip as those used in mass production to be used beginning with the development stage. This means that system development can be proceeded without having to change the printed circuit boards during the entire course, from prototype to mass production. 9 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Logical address Single-chip mode H’0000 0000 Logical address Processor mode External extended mode H’0000 0000 Internal ROM (1M bytes) 16M bytes Internal ROM H’000F FFFF H’0010 0000 CS0 area CS0 (16M bytes) area H’001F FFFF H’0020 0000 2G bytes User space Ghost area in units of 16 bytes CS1 area CS1 area CS2 area CS2 area CS3 area CS3 area SFR area SFR area RAM area RAM area Reserved area Reserved area H’003F FFFF H’0040 0000 (16M bytes) (16M bytes) H’7FFF FFFF H’8000 0000 H’005F FFFF H’0060 0000 SFR area (16K bytes) 2G bytes System space H’007F FFFF H’0080 0000 H’0080 3FFF H’0080 4000 RAM area (48K bytes) H’0080 FFFF H’0081 0000 Reserved area (64k bytes) H’0081 FFFF H’0082 0000 Ghost area in units of 128k bytes H’FFFF FFFF H’00FF FFFF *The maximum 8M bytes of extended area Figure 4. Address space 10 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development +0 address SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER +1 address +0 address H’0080 0000 H’0080 078C H’0080 078E H’0080 0790 Interrupt controller (ICU) H’0080 007E H’0080 0080 +1 address MJT (TID0) MJT (TOU0) Multijun ction timer (MJT) H’0080 07E2 A-D0 converter H’0080 00EE H’0080 0A00 Serial I/O4, 5 H’0080 0100 Serial I/O0-3 H’0080 0A26 H’0080 0180 H’0080 0186 Wait controller H’0080 0A80 H’0080 0AEE H’0080 01E0 H’0080 01F8 Flash control H’0080 0146 H’0080 0B8C H’0080 0B8E H’0080 0B90 H’0080 0200 MJT (common part) AD1 converter MJT (TID1) MJT (TOU1) H’0080 023E H’0080 0240 H’0080 0BE2 MJT (TOP) H’0080 02FE H’0080 0300 MJT (TIO) H’0080 03BE H’0080 03C0 H’0080 03D8 H’0080 03E0 H’0080 03FE H’0080 0400 Multijunction timer (MJT) H’0080 0C8C H’0080 0C8E H’0080 0C90 MJT (TID2) MJT (TOU2) H’0080 0CE2 Multijun ction timer (MJT) MJT (TMS) MJT (TML0) DMAC H’0080 0478 H’0080 0FE0 H’0080 0FFE H’0080 1000 MJT (TML1) CAN0 H’0080 11FE H’0080 0700 Input/output port H’0080 077F H’0080 1400 CAN1 H’0080 15FE Figure 5. SFR Area 11 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in 64-channel multijunction timers (MJT) The microcomputer contains a total of 64 channels of multijunction timers consisting of 11 channels of 16-bit output related timers, 10 channels of 16-bit input/output related timers, eight channels of 16-bit input related timers, eight channels of 32-bit input related timers, three channels of 16-bit input related up/down-timers, and 24 channels of 24-bit output related timers. Each timer has multiple operation modes to choose from, depending on the purposes of use. Table 3. Outline of the MJT Name Type Also, the multijunction timers internally have a clock bus, input event bus, and an output event bus, so that multiple timers can be used in combination allowing for a flexible timer configuration. The output related timers have a correcting function which allows the timer’s count value to be incremented or decremented as necessary while count is in progress, making real time output control possible. Number of channels Contents TOP (Timer Out Put) Output related 16-bit timer (down-counter) 11 TIO (Timer Input Output) Input/output related 16-bit timer (downcounter) 10 TMS (Timer Measure Small) Input related 16-bit timer (up-counter) 8 One of three output modes is selected in software. <With correcting function> • Single-shot output mode • Delayed single-shot output mode <Without correcting function> • Continuous output mode One of three input modes and four output modes is selected in software. <Input mode> • Measure clear input mode • Measure free-run input mode • Noise processing input mode <Output mode without correcting function> • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode 16-bit input measure timer. TML (Timer Measure Large) TID (Timer Input Derivation) 32-bit timer (up-counter) 8 32-bit input measure timer. Input related 16-bit timer (up/down-counter) 3 TOU (Timer Output Unification) Output related 24-bit timer (down-counter) 24 One of three input modes is selected in software. • Fixed period mode • Event count mode • Up/down event count mode • Multiply-by-4 event count mode One of five output modes is selected in software. <Without correcting function> • PWM output mode (Note1) • Single-shot PWM mode (Note1) • Delayed one-shot output mode • Single-shot output mode • Continuous output mode Note 1: During PWM and one-shot PWM modes • Functions as a 16-bit timer 12 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group E/L SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 16-bit output related timer: 11 channels 16-bit input/output related timer: 10 channels 16-bit input related timer: 8 channels 16-bit input related up/down timer: 3 channels 24-bit output related timer: 24 channels 32-bit input related timer: 8 channels EN Timer PRS F/F T Opin Interrupt output CLK TN pin To DMA and A-D converter Interrupt output CLK 1/2 internal peripheral clock Output event bus TCLK pin Input event bus Clock bus Under Development Timer F/F EN E/L T Opin E/L : Edge/level selector PRS : Prescaler : Junction box (selector) F/F : Output flip-flop Note: This is a conceptual diagram and does not show the actual timer configuration. Figure 6. Conceptual Diagram of the Multijunction Timers (MJT) 13 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus Input event bus Output event bus 3210 3210 clk S TCLK0 (P124) clk TCLK0S IRQ9 TIN0 (P150) clk TIN0S clk S DMA3,DMA commonness clk PRS0 BCLK/2 en TOP 0 udf en TOP 1 udf 0123 F/F0 TO0 (P110) F/F1 TO1 (P111) F/F2 TO2 (P112) F/F3 TO3 (P113) F/F4 TO4 (P114) F/F5 TO5 (P115) S F/F6 TO6 (P116) S F/F7 TO7 (P117) S F/F8 TO8 (P100) S F/F9 TO9 (P101) S F/F10 TO10 (P102) S F/F11 TO11 (P103) S F/F12 TO12 (P104) S F/F13 TO13 (P105) S F/F14 TO14 (P106) S F/F15 TO15 (P107) S F/F16 TO16 (P93) S F/F17 TO17 (P94) S F/F18 TO18 (P95) S F/F19 TO19 (P96) F/F20 TO20 (P97) IRQ2 IRQ2 en TOP 2 udf en TOP 3 udf en TOP 4 udf IRQ2 IRQ2 PRS1 clk PRS2 S clk S clk IRQ9 TIN1 (P151) IRQ2 TIN1S DMA6 IRQ2 en TOP 5 udf en TOP 6 udf en TOP 7 udf en TOP 8 udf IRQ1 IRQ1 S TIN2 (P152) clk S IRQ9 TIN2S clk S IRQ6 en TOP 9 udf IRQ6 DMA7 clk IRQ12 TIN3 (P153) TIN3S S clk TIN5 (P155) TIN4S TOP 10 udf IRQ0 en/cap TIO 0 udf clk IRQ0 en/cap TIO 1 udf S IRQ12 TIN5S IRQ0 clk en/cap TIO 2 udf clk en/cap TIO 3 udf S clk S IRQ12 TIN6 (P156) en S DMA1 IRQ12 TIN4 (P154) IRQ5 TIN6S IRQ0 IRQ4 en/cap TIO 4 udf S S TCLK1 (P125) TIN7 (P157) TCLK2 (P126) TIN8 (P140) TCLK1S IRQ4 IRQ8 TCLK2S clk S TIN7S en/cap TIO 5 udf S IRQ4 DMA8 IRQ8 S TIN8S clk en/cap TIO 6 udf clk en/cap TIO 7 udf S DMA9 IRQ4 IRQ8 TIN9 (P141) S TIN9S S IRQ8 TIN10 (P142) S TIN10S commonness IRQ3 clk en/cap TIO 8 udf clk en/cap TIO 9 udf : Output flip-flop S S IRQ8 TIN11 (P143) DMA0 DMA S TIN11S IRQ3 S 3210 3210 PRS0-5 : Prescaler 0123 F/F : Selector Note : IRQ0-18 denote interrupt signals, with the same number representing interrupts in the same group. DMA0-9 and DMA common denote DMA requests to the DMAC. AD0TRG and AD1TRG denote trigger signals for the A-D0 and A-D1 converters, respectively. Figure 7. Block Diagram of MJT (1/4) 14 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus Input event bus Output event bus 3210 3210 TCLK3 (P127) TCLK3S 0123 cap3 IRQ10 TIN12 (P144) TIN12S TIN13 (P145) TIN13S TMS 0 cap2 cap1 clk S cap0 ovf IRQ7 S IRQ10 S DMA1 IRQ10 TIN14 (P146) TIN14S TIN15 (P147) TIN15S S IRQ10 S cap3 IRQ10 TIN16/PWMOFF0 (P130) TIN16S TIN17/PWMOFF1 (P131) TIN17S TIN18 (P132) TIN18S TMS 1 cap2 cap1 clk S cap0 ovf IRQ7 S IRQ10 S IRQ10 S DMA2 IRQ10 TIN19 (P133) S TIN19S DMA4 clk S BCLK/2 cap3 IRQ11 TIN20 (P134) TML 0(32bit) cap2 cap1 cap0 S TIN20S DMA5 IRQ11 TIN21 (P135) TIN21S TIN22 (P136) TIN22S TIN23 (P137) TIN23S S IRQ11 S IRQ11 S (To A-D0 converter) AD0TRG (To A-D1 converter) AD1TRG clk S BCLK/2 cap3 IRQ18 TIN30 (P194) TIN30S TIN31 (P195) TIN31S TIN32 (P196) TIN32S TIN33/PWMOFF2 (P197) TIN33S TML 1(32bit) cap2 cap1 cap0 S IRQ18 S IRQ18 S AD0TRG (To A-D0 converter) IRQ18 S AD0TRG(To A-D0 converter)/AD1TRG(To A-D1 converter) AD0TRG(To A-D0 converter)/AD1TRG(To A-D1 converter) 3210 3210 0123 Figure 8. Block Diagram of MJT (2/4) 15 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Output event bus 0 TIN16/PWMOFF0 (P130) PWMOFF0S clk clk clk clk BCLK/2 S en TOU0_1 (24-bit) udf en TOU0_2 (24-bit) udf en TOU0_3 (24-bit) udf F/F21 TO21 (P160) F/F22 TO22 (P161) F/F23 TO23 (P162) F/F24 TO24 (P163) F/F25 TO25 (P164) F/F26 TO26 (P165) F/F27 TO27 (P166) F/F28 TO28 (P167) DMA6 IRQ13 DMA7 IRQ13 IRQ13 udf clk en TOU0_5 (24-bit) udf clk en TOU0_6 (24-bit) udf en TOU0_7 (24-bit) udf clk PO0DOS DMA5 IRQ13 en TOU0_4 (24-bit) clk PRS3 TIN24 (P172) TIN25 (P173) udf clk IRQ11 TIN24S IRQ13 en TOU0_0 (24-bit) IRQ13 IRQ13 DMA8 IRQ13 DMA9 ovf udf CLK1 CLK2 TID 0 IRQ11 IRQ14 DMA0 S TIN25S TIN17/PWMOFF1 (P131) PWMOFF1S en TOU1_0 (24-bit) udf clk en TOU1_1 (24-bit) udf clk en TOU1_2 (24-bit) udf clk en TOU1_3 (24-bit) udf clk en TOU1_4 (24-bit) udf clk clk IRQ11 TIN26S BCLK/2 S clk clk PRS4 TIN26 (P190) TIN27 (P191) IRQ16 clk PO1DIS F/F29 TO29 (P180) F/F30 TO30 (P181) F/F31 TO31 (P182) F/F32 TO32 (P183) F/F33 TO33 (P184) F/F34 TO34 (P185) F/F35 TO35 (P186) F/F36 TO36 (P187) IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 en TOU1_5 (24-bit) udf IRQ16 en TOU1_6 (24-bit) udf IRQ16 en TOU1_7 (24-bit) udf DMA4 ovf udf CLK1 CLK2 TID 1 IRQ11 IRQ15,AD1TRG (To A-D1 converter) DMA1 S TIN27S TIN33/PWMOFF2 (P197) PWMOFF2S clk clk clk clk clk clk clk IRQ11 TIN28S BCLK/2 S clk PRS5 TIN28 (P192) TIN29 (P193) IRQ11 TIN29S Figure 9. Block Diagram of MJT (3/4) 16 clk IRQ16 en TOU2_0 (24-bit) udf PO2DIS F/F37 TO37 (P210) F/F38 TO38 (P211) F/F39 TO39 (P212) F/F40 TO40 (P213) F/F41 TO41 (P214) F/F42 TO42 (P215) F/F43 TO43 (P216) F/F44 TO44 (P217) IRQ16 en TOU2_1 (24-bit) udf IRQ16 en TOU2_2 (24-bit) udf IRQ16 en TOU2_3 (24-bit) udf IRQ16 en TOU2_4 (24-bit) udf IRQ16 en TOU2_5 (24-bit) udf IRQ16 en TOU2_6 (24-bit) udf IRQ16 en TOU2_7 (24-bit) udf DMA5 ovf udf CLK1 CLK2 TID 2 S IRQ17 DMA2 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Input event bus Output event bus 3 2 1 0 0 1 2 3 AD0 completed TIO8_udf TIN0S S AD0 completed TIO8_udf S DMA0 udf end DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf end Started in Software TID0_udf/ovf CAN0_S0/S15 TIN3S TID1_udf/ovf S TIN13S Started in Software S TIN18S Started in Software S SIO0_TXD SIO1_RXD Started in Software S SIO0_RXD Started in Software S CAN0_S1/S14 TID2_udf/ovf S TIN0S AD1 completed S TIN19S SIO0_TXD TOU1_7irq S TIN20S TOU0_0irq TOU2_7irq Started in Software S TOU0_1irq SIO1_RXD S SIO3_TXD TOU0_2irq S TOU0_6irq TIN7S S AD1 completed TOU0_7irq S 3 2 1 0 DMA0-4 Interrupt SIO2_RXD S SIO1_TXD TIN1S Started in Software S SIO2_TXD TIN2S Started in Software S SIO3_RXD Started in Software SIO3_TXD TIN8S Started in Software DMA5 udf end DMA6 udf end DMA7 udf end DMA8 udf end DMA9 udf end S S DMA5-9 Interrupt 0 1 2 3 Figure 10. Block Diagram of MJT (4/4) 17 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development Built-in 10-Channel DMAC The microcomputer contains 10 channels of DMAC, allowing for data transfer between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs. DMA transfer requests can be issued from the user-created software, as well as can be triggered by a signal generated by the internal peripheral I/O (A-D converter, timer, or serial I/O). SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER The microcomputer also supports cascaded connection between DMA channels (starting DMA transfer on a channel at end of transfer on another channel). This makes advanced transfer processing possible without causing any additional CPU load. Table 4. Outline of the DMAC Item Number of channels Transfer request Maximum number of times transferred Transferable address space Transfer data size Transfer method Transfer mode Direction of transfer Channel priority Maximum transfer rate Interrupt request Content 10 channels • Software trigger • Request from internal peripheral I/O: A-D converter, timer, or serial I/O (reception completed, transmit buffer empty) • Cascaded connection between DMA channels possible (Note1) 65536 times • 64K bytes (address space from H’0080 0000 to H’0080 FFFF) • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral IO, and between internal RAMs are supported 16-bit or 8-bit Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-address transfer Single transfer mode One of three modes can be selected for the source and destination of transfer: • Address fixed • Address increment • 32-channel ring buffer Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (Fixed priority) 13.3M bytes per second (when internal peripheral clock = 20 MHz) Group interrupt request can be generated when each transfer count register underflows Note 1: The following DMA channels can be cascaded. DMA transfer on channel 1 started at end of one DMA transfer on channel 0 DMA transfer on channel 5 started at completion of all DMA transfers on channel 0 (transfer count register underflow) DMA transfer on channel 2 started at end of one DMA transfer on channel 1 DMA transfer on channel 0 started at end of one DMA transfer on channel 2 DMA transfer on channel 3 started at end of one DMA transfer on channel 2 DMA transfer on channel 4 started at end of one DMA transfer on channel 3 DMA transfer on channel 6 started at end of one DMA transfer on channel 5 DMA transfer on channel 7 started at end of one DMA transfer on channel 6 DMA transfer on channel 5 started at end of one DMA transfer on channel 7 DMA transfer on channel 8 started at end of one DMA transfer on channel 7 DMA transfer on channel 9 started at end of one DMA transfer on channel 8 18 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Input event bus Output event bus 3 2 1 0 0 1 2 3 AD0 completed TIO8_udf TIN0S S AD0 completed TIO8_udf S DMA0 udf end DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf end Started in Software TID0_udf/ovf CAN0_S0/S15 TIN3S TID1_udf/ovf S TIN13S Started in Software S TIN18S Started in Software S SIO0_TXD SIO1_RXD Started in Software S SIO0_RXD Started in Software S CAN0_S1/S14 TID2_udf/ovf S TIN0S AD1 completed S TIN19S SIO0_TXD TOU1_7irq S TIN20S TOU0_0irq TOU2_7irq Started in Software S TOU0_1irq SIO1_RXD S SIO3_TXD TOU0_2irq S TOU0_6irq TIN7S S AD1 completed TOU0_7irq S 3 2 1 0 DMA0-4 Interrupt SIO2_RXD S SIO1_TXD TIN1S Started in Software S SIO2_TXD TIN2S Started in Software S SIO3_RXD Started in Software SIO3_TXD TIN8S Started in Software DMA5 udf end DMA6 udf end DMA7 udf end DMA8 udf end DMA9 udf end S S DMA5-9 Interrupt 0 1 2 3 Figure 11. Block Diagram of DMAC 19 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development Built-in Two Independent 16-channel A-D Converters The microcomputer contains two 16-channel A-D converters with 10-bit resolution (A-D0 converter and A-D1 converter). In addition to single conversion on each channel, continuous A-D conversion on a combined group of N (N = 1–16) channels is possible. The A-D converted value can be read out in either 10-bit or 8-bit. In addition to ordinary A-D conversion, the converters support comparator mode in which the set value and A-D converted value are compared to determine which is larger or smaller than the other. SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Moreover, there is also sample & hold mode, input voltage is sampled, when A-D conversion is started, and the A-D conversion of the sampling voltage is carried out. Since there is no invalid domain near [which becomes a problem by the external operational amplifier etc.] VCCE/VSS, conversion by the full range is possible in this Sample & hold circuit. When A-D conversion is finished, the converters can generated a DMA transfer request, as well as an interrupt. The A-D converters are interfaced using a dedicated power supply to allow for connections to the peripheral circuits operating with 5 V. Table 5. Outline of the A-D Converters Item Content Analog input 16-channel x 2 A-D conversion method Successive approximation method Resolution 10-bit (Conversion results can be read out in either 10 or 8-bit) Absolute accuracy (conditions: During low speed mode: Normal mode: + 2 LSB, double speed mode: + 2 LSB (Note1) Ta = 25°C, AVCC0, 1 = During high speed mode: Normal mode: + 3 LSB, double speed mode: + 3 LSB (Note1) VREF0, 1 = 5.12 V) Conversion mode A-D conversion mode, comparator mode Operation mode Single mode, scan mode Scan mode Single -shot scan mode, continuous scan mode Special mode Single mode forcible execution under scan mode operation, scan mode start after the single mode execution, conversion re-start Sample & hold mode Input voltage is sampled when A-D conversion is started, and it is A-D conversion about sampling voltage. Conversion start trigger Software start Started by setting A-D conversion start bit to 1 Hardware start A-D0 conversion start sources: MJT input event bus 2, MJT input event bus 3, MJT output event bus 3, and TIN23 A-D1 converter start sources: MJT input event bus 2, MJT input event bus 3, and TID1_ovf / udf / TIN23S Conversion During single mode Low-speed Normal 299BCLK 14.95µs (Note2) BCLK : Internal peripheral clock • At the time of sample & Mode Double speed 173BCLK 8.65µs hold invalid • At the time of normal High-speed Normal 131BCLK 6.55µs sample & hold effective Mode Double speed 89BCLK 4.45µs During single mode (Available for High-speed Sample & Hold) During comparator mode Interrupt request generation DMA transfer request generation Low-speed Mode Normal Double speed 191BCLK 101BCLK 9.55µs 5.05µs High-speed Mode Normal Double speed 95BCLK 53BCLK 4.75µs 2.65µs Low-speed Mode Normal Double speed 47BCLK 29BCLK 2.35µs 1.45µs High-speed Mode Normal Double speed 23BCLK 17BCLK 1.15µs 0.85µs When A-D conversion is finished, when comparate operation is finished When single-shot scan is finished, or when one cycle of continuous scan is finished When A-D conversion is finished, when comparate operation is finished When single-shot scan is finished, or when one cycle of continuous scan is finished Note 1: The performance is the same during sample & hold mode. Note 2: Internal peripheral clock (BCLK) = o'clock (1BCLK=50ns) of 20MHz conversion time 20 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal date bus 8-bit readout 10-bit Readout Shifter AD0DT0 10-bit A-D0 Data Register 0 AD0DT1 10-bit A-D0 Data Register 1 AD0SIM0,1 AD0DT2 10-bit A-D0 Data Register 2 AD0SCM0,1 A-D0 Scan Mode Register AD0DT3 10-bit A-D0 Data Register 3 AD0DT4 10-bit A-D0 Data Register 4 AD0DT5 10-bit A-D0 Data Register 5 AD0DT6 10-bit A-D0 Data Register 6 Input event bus3 Input event bus2 Output event bus3 AD0DT7 10-bit A-D0 Data Register 7 TIN23 AD0DT8 10-bit A-D0 Data Register 8 AD0DT9 10-bit A-D0 Data Register 9 AD0DT10 10-bit A-D0 Data Register 10 AD0DT11 10-bit A-D0 Data Register 11 AD0DT12 10-bit A-D0 Data Register 12 AD0DT13 10-bit A-D0 Data Register 13 AD0DT14 10-bit A-D0 Data Register 14 AD0DT15 10-bit A-D0 Data Register 15 AD0CMP A-D0 Single Mode Register AD0CTRG1 S S AD0STRG1 A-D Comparate Data Register A-D Control Circuit AVCC0 AVSS0 10-bit A-D Successive Approximation Register (AD0SAR) Mode selection Channel selectikon Interrupt request Conversion time selection VREF0 10-bit D-A Converter Flag control Comparator AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 Interrupt control DMA transfer request DMA0 DMA commonness Sample & Hold control circuit Selector Successive Approximationtype A-D Converter Unit Figure 12. Block Diagram of the A-D0 Converter 21 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal data bus 8-bit readout 10-bit readout shifter AD1DT0 10-bit A-D1 Data Register 0 AD1DT1 10-bit A-D1 Data Register 1 AD1SIM0,1 A-D1 Single Mode Register AD1DT2 10-bit A-D1 Data Register 2 AD1SCM0,1 A-D1 Scan Mode Register AD1DT3 10-bit A-D1 Data Register 3 AD1DT4 10-bit A-D1 Data Register 4 AD1DT5 10-bit A-D1 Data Register 5 AD1DT6 10-bit A-D1 Data Register 6 AD1DT7 10-bit A-D1 Data Register 7 AD1DT8 10-bit A-D1 Data Register 8 AD1DT9 10-bit A-D1 Data Register 9 AD1DT10 10-bit A-D1 Data Register 10 AD1DT11 10-bit A-D1 Data Register 11 AD1DT12 10-bit A-D1 Data Register 12 AD1DT13 10-bit A-D1 Data Register 13 AD1DT14 10-bit A-D1 Data Register 14 AD1DT15 10-bit A-D1 Data Register 15 AD1CMP AD1CTRG1 Input event bus3 Input event bus2 TID1_udf/ovf TIN23S S S AD1STRG1 A-D Comparate Data Register A-D Control Circuit AVCC1 AVSS1 10-bit A-D Successive Approximation Register (AD1SAR) Mode selection Channel selectikon Conversion time selection VREF1 10-bit D-A Converter Flag control comparator AD1IN0 AD1IN1 AD1IN2 AD1IN3 AD1IN4 AD1IN5 AD1IN6 AD1IN7 AD1IN8 AD1IN9 AD1IN10 AD1IN11 AD1IN12 AD1IN13 AD1IN14 AD1IN15 Sample & Hold control circuit Selector Successive Approximationtype A-D Converter Unit Figure 13. Block Diagram of the A-D1 Converter 22 Interrupt control Interrupt request DMA transfer request DMA3 DMA9 2002-07-12 Rev.1.0 Mitsubishi Microcomputers 32180 Group Under Development 6-channel High-speed Serial I/Os The microcomputer contains six channels of serial I/Os consisting of four channels that can be set for CSIO mode (clock-synchronized serial I/O) or UART mode (asynchronous serial I/O) and two other channels that can only be set for UART mode. SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER The SIO has the function to generate a DMA transfer request when data reception is completed or the transmit register becomes empty, and is capable of high-speed serial communication without causing any additional CPU load. Table 6. Outline of the Serial I/O Item Number of channels Content CSIO/UART : 4 channels (SIO0, SIO1, SIO4, SIO5) UART only : 2 channels (SIO2, SIO3) Clock During CSIO mode : Internal clock / external clock, selectable (Note1) During UART mode: Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex BRG count source f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (When internal clock is selected) (Note2) Data format CSIO mode: Data length = Fixed to 8-bit Order of transfer = Fixed to LSB first UART mode: Start bit = 1-bit Character length = 7, 8, or 9-bit Parity bit = With or without (If included, selectable between odd and even parity) Stop bit = 1 or 2-bit Order of transfer = Fixed to LSB first Baud rate CSIO mode : 152-bit per second to 2M-bit per second (when operating with f(BCLK) = 20 MHz) UART mode: 19-bit per second to 156K-bit per second (when operating with f(BCLK) = 20 MHz) Error detection CSIO mode : Overrun error only UART mode: Overrun, parity, and framing errors (The error-sum bit indicates which error has occurred) Fixed cycle clock output When SIO0, SIO1, SIO4, or SIO5 is in UART mode, this function outputs a 1/2 BRG clock from function the SCLK pin. Note 1: During CSIO mode, the maximum input frequency of an external clock is f(BCLK) divided by 16. Note 2: When f(BCLK) is selected for the BRG count source, the BRG set value is subject to limitations. 23 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER SIO0 SIO0 Transmit Buffer Register Transmit interrupt TXD0 SIO0 Transmit Shift Register RXD0 SIO0 Receive Shift Register To interrupt controller Receive interrupt Transmit /receive control circuit Transmit DMA transfer request Receive DMA transfer request To DMA3, DMA4 To DMA4 SIO0 Receive Buffer Register BCLK Clock divider CSIO mode When external clock selected When internal clock selected 1/16 1 (Set value + 1) Baud rate generator (BRG) 1/2 CSIO mode When internal clock selected When UART mode selected SIO1 TXD1 SIO1 Transmit Shift Register RXD1 SIO1 Receive Shift Register Transmit /receive control circuit Internal data bus BCLK, BCLK/8, BCLK/32, BCLK/256 UART mode Transmit interrupt Receive interrupt Transmit DMA transfer request Receive DMA transfer request SCLKI0 / SCLKO0 To interrupt controller To DMA6 To DMA3, DMA6 SCLKI1 / SCLKO1 SIO2 TXD2 SIO2 Transmit Shift Register RXD2 SIO2 Receive Shift Register Transmit /receive control circuit Transmit interrupt Receive interrupt Transmit DMA transfer request Receive DMA transfer request To DMA7 To DMA5 SIO3 Transmit interrupt TXD3 RXD3 SIO3 Transmit Shift Register SIO3 Receive Shift Register Transmit /receive control circuit To interrupt controller Receive interrupt Transmit DMA transfer request Receive DMA transfer request To DMA9, DMA7 To DMA8 SIO4 TXD4 RXD4 SIO4 Transmit Shift Register SIO4 Receive Shift Register Transmit /receive control circuit Transmit interrupt Receive interrupt SCLKI4 / SCLKO4 SIO5 TXD5 RXD5 SIO5 Transmit Shift Register SIO5 Receive Shift Register Transmit /receive control circuit Transmit interrupt To interrupt controller Receive interrupt SCLKI5 / SCLKO5 Note 1: When BCLK is selected for the BRG count source,the BRG set value is subject to limitations. Note 2: SIO2 and SIO3 do not have the SCLKI/SCLKO function. Figure 14. Block Diagram of Serial I/O 24 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development Input/output Ports The microcomputer has a total of 158 input/output ports (of which P5 is reserved for future use). The input/output ports can be used as input ports or output ports by setting up their direction registers. Each input/output port is a dual- SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER function pin shared with other internal peripheral I/O or external extended bus signal lines. These pin functions are selected by using the chip operation mode select or the input/output port operation mode registers Table7. Outline of Input/output Ports Item Specification Number of Port Total 158 ports (8 lines) P00-P07 : P0 (8 lines) P10-P17 : P1 (8 lines) P20-P27 : P2 (8 lines) P30-P37 : P3 (7 lines) P41-P47 : P4 (6 lines) P61-P63, P65-P67 : P6 (8 lines) P70-P77 : P7 (6 lines) P82-P87 : P8 (5 lines) P93-P97 : P9 (8 lines) P100-P107 : P10 (8 lines) P110-P117 : P11 (4 lines) P124-P127 : P12 (8 lines) P130-P137 : P13 (8 lines) P140-P147 : P14 (8 lines) P150-P157 : P15 (8 lines) P160-P167 : P16 (6 lines) P172-P177 : P17 (8 lines) P180-P187 : P18 (8 lines) P190-P197 : P19 (4 lines) P200-P203 : P20 (8 lines) P210-P217 : P21 (8 lines) P220-P227 : P22 Port function The input/output ports can be set for input or output mode bit wise by using the input/output port direction control register. (However, P221 and P223 are CAN0 input-only ports.) Pin function Dual-functions shared with peripheral I/O or external extended signals (or multi-functions shared with peripheral I/Os which have multiple functions) Pin function P0-4, P224-P227 : Changed by setting CPU operation mode (MOD0 and MOD1 pins) (Note1) changeover P6-22 : Changed by setting the input/output port operation mode register (However, peripheral I/O pin functions are selected using the peripheral I/O register.) Note 1: When the CPU is operating in external extension mode, P0-P3, P44-P47 and P224-P227 by default are set for input/output port pins, but have their functions switched for external extension signal pins by setting the Port Operation Mode Register. When operating in single-chip or processor mode, the pin functions are switched over by setting the CPU operation mode pins as shown in Table 8. Three operation modes 32180 Group has three-operation modes-single-chip mode, extended external mode, and processor mode. Each operation mode switches over by setting the MOD0 and MOD1 pins. Table 8. CPU Operation Modes and P0–P4, P224–P227 Pin Functions MOD0 MOD1 Operation mode P0-P3, P44-P47, P224-P227 pin function VSS VSS Single-chip mode Input/output port pin VSS VCCE External extended mode Input/output port pin or External extended signal pin VCCE VSS Processor mode (FP pin = VSS) External extended signal pin VCCE VCCE Do not select Note: VCC and VSS are connected to power supply and GND, respectively. 25 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development Settings of Chip operation mode (Note1) 0 1 2 3 4 5 6 7 P0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 P1 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 P2 A23 A24 A25 A26 A27 A28 A29 A30 P3 A15 A16 A17 A18 A19 A20 A21 A22 BLW# / BLE# BHW# / BHE# RD# CS0# CS1# A13 A14 (P61) (P62) (P63) HREQ# HACK# TXD0 RXD0 SCLKI0 / SCLKO0 TXD1 RXD1 SCLKI1 / SCLKO1 TO16 TO17 TO18 TO19 TO20 TO11 TO12 TO13 TO14 TO15 TO3 TO4 TO5 TO6 TO7 TCLK0 TCLK1 TCLK2 TCLK3 P4 Reserved SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER P5 P6 P7 BCLK / WR# WAIT# P8 MOD0 MOD1 (Note3) (Note3) P9 P10 TO8 P11 TO0 TO9 / TO10 / TXD3(Note2) CTX1(Note2) TO1 TO2 P12 P13 Settings of input/ output port Operation Mode Register TIN16/ TIN17/ PWMOFF0 PWMOFF1 SBI# (Note3) SCLKI4 / SCLKI5 / SCLKO4 SCLKO5 (P67) RTDTXD RTDRXD RTDACK RTDCLK TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 P14 TIN8 TIN9 TIN10 TIN11 TIN12 TIN13 TIN14 TIN15 P15 TIN0 TIN1 TIN2 TIN3 TIN4 TIN5 TIN6 TIN7 P16 TO21 TO22 TO23 TO24 TO25 TO26 TO27 TO28 TIN24 TIN25 TXD2 RXD2 TXD3 RXD3 P17 P18 TO29 TO30 TO31 TO32 TO33 TO34 TO35 TO36 P19 TIN26 TIN27 TIN28 TIN29 TIN30 TIN31 TIN32 TIN33/ PWMOFF2 P20 TXD4 RXD4 TXD5 RXD5 P21 TO37 TO38 TO39 TO40 TO41 TO42 TO43 TO44 P22 CTX0 CRX0 CTX1 CRX1 CS2# CS3# A11 / A12 / CS2#(Note2) CS3#(Note2) (Note1) Note 1: It changes to an external extension signal pin function at the time of processor mode. At the time of external extension mode, only P41-P43 change to an external bus interface pin. Since other pins turn into an input/output ports pin at the time of reset, it is necessary to set the pin to be used as an external bus interface pin by the port operation mode register. Note 2: It is a triple function pin. It is necessary to set up the circumference function to output by the circumference output selection register. Note 3: It cannot be used as a function of an input/output ports. The input level of SBI#, MOD0, and an MOD1 pin can be read. Figure15. Input/Output Ports and pin function Assignments 26 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER CAN Modules The 32180 Group contains two blocks of Full-CAN modules compliant with CAN Specification V2.0B active. The CAN modules each have 16 slots of Message Slot. Data Bus CAN0 Status Register CAN0 REC Register CAN0 TEC Register CAN0 Message Slot 0-15 Control Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Global Mask Register CAN0 Local Mask RegisterA CAN0 Local Mask RegisterB CAN0 Control Register CRX0 CAN0 Protocol controller Ver 2.0B active (1)Message ID (2)Date Code (3)Message Data (4)Time Stamp CAN0 Slot Status Register CAN0 slot Interrupt Control Register Acceptance filtering CTX0 Message Memory CAN0 error Interrupt Control Register 16-bit Timer CAN0 Time Stamp Register CAN0 Transmit/Receive &Error Interrupt Interrupt Control circuit Figure 16. Block Diagram of the CAN0 Module Data Bus CAN1 Status Register CAN1 REC Register CAN1 TEC Register CAN1 Message Slot 0-15 Control Register CAN1 Extended ID Register CAN1 Configuration Register CAN1 Control Register Acceptance filltering CTX1 CRX1 CAN1 Protocol controller Ver 2.0B active 16-bit Timer CAN1 Time Stamp Register CAN1 Global Mask Register CAN1 Local Mask RegisterA CAN1 Local Mask RegisterB Message Memory (1)Message ID (2)Date Code (3)Message Data (4)Time Stamp CAN1 Slot Status Register CAN1 slot Interrupt Control Register CAN1 error Interrupt Control Register CAN1 Transmit/Receive &Error Interrupt Interrupt Control circuit Figure 17. Block Diagram of the CAN1 Module 27 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Port Input threshold level select function The port Input threshold level select function selects the port threshold between TTL, CMOS, and Schmitt as desired. This setting is possible for each group individually. 8-level Interrupt Controller The Interrupt Controller controls interrupt requests from each internal peripheral I/O (32 sources) by using eight priority levels assigned to each interrupt source, including interrupts prohibition. In addition to these interrupts, it handles System Break Interrupt (SBI), Reserved Instruction Exception (RIE), and Address Exception (AE) as nonmaskable interrupts. Realtime Debugger (RTD) The Realtime Debugger (RTD) provides a function for accessing directly from the outside to the internal RAM. It uses a dedicated clock-synchronized serial I/O to communicate with the outside. Use of the RTD communicating via dedicated serial lines allows the internal RAM to be read out and rewritten without having to halt the CPU. Also, it can activate an exclusive RTD interrupt through RTD communication. Wait Controller The Wait Controller supports access to external devices. For access to an external extended area of up to 8M bytes (during external extended or processor mode), the Wait Controller controls bus cycle extension by inserting zero to seven wait cycles and using external WAIT# signal input. However, as setup for lead of CS signal / lead of strobe signal / recovery / idol after lead cycle, only operation by "nothing" setup is guaranteed when 0wait is selected. Moreover, WAIT by the external WAIT input is not received when 0wait is selected. Built-in Virtual-Flash emulation function The 1M bytes of internal flash memory can have its 4K bytes areas (total 256 banks) replaced with 4K bytes areas of the internal RAM (4K bytes x 8). Use of this function helps to make the necessary changes and evaluate the changed program during development phase without having to reset the microcomputer. Also, when combined with the real-time debugger, this function enables the data in RAM to be rewritten and read out without causing CPU load, making it possible to reduce the program evaluation period. Built-in clock frequency multiplier The PLL (clock frequency multiplier) multiplies the input clock frequency by 8 to generate the CPU memory clock. For the maximum CPU memory clock frequency of 80 MHz, the input clock frequency is 10.0 MHz. 0.7VCCE S VT+ S VT- Schmitt 0.5VCCE Pin PORT Input S Input function enable 0.35VCCE Threshold S CMOS PTnSEL VTnSELL Standard input threshold level of peripheral function Figure 18. Port Input threshold level select function 28 S WFnSEL Peripheral function input Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 32180 RTDCLK RTDRXD Internal RAM M32R CPU Real-Time Debugger (RTD) Virtual-DPRAM structure Command address Data Data Data RTDTXD RTDACK R/W without CPU intervention Data Bus(CPU) Data Bus(RTD) Figure 19. Conceptual Diagram of the Real-time Debugger (RTD) <Internal RAM> H'0080 4000 <Internal flash> H'0000 0000 S bank 0 (4K bytes) H'0000 1000 S bank 1 (4K bytes) H'0000 2000 S bank 2 (4K bytes) H'0080 7FFF H'000F D000 S bank 253 (4K bytes) H'000F E000 S bank 254 (4K bytes) H'000F F000 S bank 255 (4K bytes) 4K bytes H'0080 8000 4K bytes H'0080 9000 4K bytes H'0080 A000 4K bytes H'0080 B000 4K bytes H'0080 C000 4K bytes H'0080 D000 4K bytes H'0080 E000 4K bytes H'0080 F000 Figure20. Conceptual Diagram of the Virtual -Flash Emulation (Units 4K bytes) 29 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development CPU Instruction Set The M32R employs a RISC architecture, supporting a total of 83 discrete instructions. Load Load Load Load Load Load Store Store Store Store byte unsigned halfword unsigned locked byte halfword • Multiplication/division byte halfword unlocked (2) Transfer instructions Perform register to register transfer or register to immediate transfer. LD24 LDI MV MVFC MVTC SETH Load 24-bit immediate Load immediate Move register Move from control register Move to control register Set high-order 16-bit (3) Branch instructions Used to change the program flow. BC BEQ BEQZ BGEZ BGTZ BL BLEZ BLTZ BNC BNE BNEZ BRA JL JMP NOP Branch on C-bit Branch on equal Branch on equal zero Branch on greater than or equal zero Branch on greater than zero Branch and link Branch on less than or equal zero Branch on less than zero Branch on not C-bit Branch on not equal Branch on not equal zero Branch Jump and link Jump No operation (4) Arithmetic/logic instructions Perform comparison, arithmetic/logic operation, multiplication/division, or shift between registers. • Comparison CMP CMPI CMPU CMPUI Compare Compare Compare Compare immediate unsigned unsigned immediate • Logical operation AND AND3 NOT OR OR3 XOR XOR3 30 • Arithmetic operation ADD ADD3 ADDI ADDV ADDV3 ADDX NEG SUB SUBV SUBX (1) Load/store instructions Perform data transfer between memory and registers. LD LDB LDUB LDH LDUH LOCK ST STB STH UNLOCK SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER AND AND 3-operand Logical NOT OR OR 3-operand Exclusive OR Exclusive OR 3-operand DIV DIVU MUL REM REMU Add Add 3-operand Add immediate Add(with overflow checking) Add 3-operand Add with carry Negate Subtract Subtract (with overflow checking) Subtract with borrow Divide Divide unsigned Multiply Remainder Remainder unsigned • Shift SLL SLL3 SLLI SRA SRA3 SRAI SRL SRL3 SRLI Shift Shift Shift Shift Shift Shift Shift Shift Shift left logical left logical 3-operand left logical immediate right arithmetic right arithmetic 3-operand right arithmetic immediate right logical right logical 3-operand right logical immediate (5) Instructions for the DSP function Perform 32-bit x 16-bit or 16-bit x 16-bit multiplication or sum-of-products calculation. These instructions also perform rounding of the accumulator data or transfer between accumulator and general-purpose register. MACHI MACLO MACWHI MACWLO MULHI MULLO MULWHI MULWLO word MVFACHI MVFACLO word MVFACMI MVTACHI MVTACLO RAC RACH Multiply-accumulate halfwords Multiply-accumulate halfwords Multiply-accumulate high-order halfword Multiply-accumulate low-order halfword Multiply high-order Multiply low-order Multiply word and halfword Multiply word and Move word Move high-order low-order word and word and halfwords halfwords high-order low-order from accumulator high-order from accumulator low-order Move from accumulator middle-order word Move to accumulator high-order word Move to accumulator low-order word Round accumulator Round accumulator halfword (6) EIT related instructions Start trap or return from EIT processing. RTE TRAP half- Return Trap from EIT Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER (7) Instructions for the FPU function The microcomputer supports fully IEEE754 compliant, single-precision floating-point arithmetic. FADD FSUB FMUL FDIV FMADD FMSUB ITOF UTOF FTOI FTOS FCMP FCMPE (8) Extended instructions STH BSET BCLR BTST SETPSW CLRPSW Floating-point add Floating-point subtract Floating-point multiply Floating-point divide Floating-point multiply and add Floating-point multiply and subtract Integer to float Unsigned to float Float to integer Float to short Floating-point compare Floating-point compare with exception if unordered <Multiply instruction> Store halfword(@R+ addressing added) Bit set Bit clear Bit test Set PSW Clear PSW 0 <Multiply-accumulate instruction> 63 ACC Rsrc1 15 16 0 Rsrc2 15 16 31 0 L H H 31 Rsrc1 15 16 0 L H Rsrc2 15 16 31 0 L 31 H x L x x MULHI instruction 0 x MULLO instruction 63 + ACC + Rsrc1 0 31 0 32bit 0 Rsrc2 15 16 H MACHI instruction MACLO instruction 63 31 ACC L 0 63 ACC x x MULHI instruction 0 Rsrc1 MULLO instruction 63 0 Rsrc2 15 16 31 0 32bit ACC H 31 L x x + + <Round off instruction> 0 MACWLO instruction 63 MACWHI instruction 0 63 ACC ACC RAC instruction 0 sign 63 <Accumulator-register transfer instruction> 0 data 0 MVFACMI instruction 63 0 15 16 31 32 47 48 63 31 0 Rsrc ACC ACC MVFACHI instruction RACH instruction 0 sign data 63 0 MVFACLO instruction 0 31 Rdest MVTACHI instruction 0 MVTACLO instruction 31 32 63 ACC Figure 21. Instructions for the DSP Function 31 Mitsubishi Microcomputers 2002-07-12 Rev.1.0 32180 Group Under Development SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Package Dimensions Diagram MMP Plastic 240pin 32 x 32mm body QFP Weight(g) JEDEC Code – Lead Material Cu Alloy MD HD D ME EIAJ Package Code QFP240-P-3232-0.50 e 240P6Y-A b2 121 180 120 181 I2 Symbol HE E Recommended Mount Pad 61 240 1 60 F A L1 A1 c A2 e y b x M Detail F L A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME Dimension in Millimeters Min Nom Max – – 4.1 0.35 0.45 0.25 3.6 – – 0.15 0.2 0.3 0.13 0.15 0.2 31.9 32.0 32.1 31.9 32.0 32.1 – 0.5 – 34.4 34.6 34.8 34.4 34.6 34.8 0.3 0.5 0.7 1.3 – – – – 0.08 0.1 – – 0 10 – 0.225 – – 1.2 – – 32.6 – – – – 32.6 Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. • Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. • All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). • When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. • Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. • The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. • If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. • Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. ©2002 MITSUBISHI ELECTRIC CORP. New publication, effective Jul. 2002. Specifications subject to change without notice. REVISION HISTORY Rev. 32180 Group Data Sheet Date Description Summary Page 1.0 7/12/02 - First Edition. (1/1)