Revised November 2000 74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs General Description Features The LVTH646 consists of registered bus transceiver circuits, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-toHIGH transition of the appropriate clock pin (CPAB or CPBA). (See Functional Description) ■ Input and output interface capability to systems at 5V VCC The LVTH646 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The bus transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH646 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ Functionally compatible with the 74 series 646 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number 74LVTH646WM M24B 74LVTH646MTC MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code. Logic Symbols IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS012017 www.fairchildsemi.com 74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs November 1999 74LVTH646 Connection Diagram Pin Descriptions Pin Names A0–A7 Description Data Register A Inputs Data Register A Outputs B0–B7 Data Register B Inputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Transmit/Receive Inputs OE Output Enable Input DIR Direction Control Input Data Register B Outputs Truth Table (Note 1) Inputs Data I/O DIR CPAB CPBA H X H or L X X X X X X X X L H X L X An to Bn—Real Time (Transparent Mode) L H X L X Clock An Data into A Register L H X H X L H X H X Clock An Data into A Register and Output to Bn L L X H H or L H X L Bn to An—Real Time (Transparent Mode) X X H or L X L L X L L X L L X H = HIGH Voltage Level X H or L SAB SBA X L X H X H L = LOW Voltage Level A0–A7 B0–B7 Input Input Function OE Isolation Clock An Data into A Register Clock Bn Data into B Register Input Output Output X = Immaterial Input A Register to Bn (Stored Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental busmanagement functions that can be performed. The direction control (DIR) determines which bus will receive data when OE is LOW. In the isolation mode (OE HIGH), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two busses, A or B, may be driven at a time. Real-Time Transfer Bus B to Bus A OE DIR L L Real-Time Transfer Bus B to Bus A CPAB CPBA SAB SBA X X X L OE DIR L H Transfer Storage Data to A or B CPAB CPBA SAB SBA X X L X Storage OE DIR OE DIR L L CPAB CPBA SAB SBA X H or L X H L H L H H or L X H X L L H X H X 3 CPAB CPBA SAB SBA X X X X L X X L X X X X www.fairchildsemi.com 74LVTH646 Functional Description 74LVTH646 Absolute Maximum Ratings(Note 2) Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 3) V V V IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State V mA mA mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V VCC Supply Voltage VI Input Voltage IOH HIGH Level Output Current −32 IOL LOW Level Output Current 64 TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Units mA −40 85 °C 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. www.fairchildsemi.com 4 Symbol TA =−40°C to +85°C VCC Parameter (V) Min Units Max −1.2 VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA 2.7 2.4 V IOH = −8 mA 3.0 2.0 II(HOLD) II(OD) Output LOW Voltage Bushold Input Minimum Drive Power Off Leakage Current IPU/PD Power up/down 3-STATE VO ≤ 0.1V or VO ≥ VCC − 0.1V V IOH = −32 mA V IOL = 100 µA 2.7 0.5 V IOL = 24 mA 3.0 0.4 V IOL = 16 mA 3.0 0.5 V IOL = 32 mA 3.0 0.55 V IOL = 64 mA 3.0 75 µA VI = 0.8V −75 µA VI = 2.0V 500 µA (Note 4) −500 µA (Note 5) 3.6 10 µA VI = 5.5V Control Pins 3.6 ±1 µA VI = 0V or VCC Data Pins 3.6 −5 µA VI = 0V 1 µA VI = VCC ±100 µA Input Current IOFF V 0.8 0.2 Current to Change State II 2.0 2.7 3.0 Bushold Input Over-Drive V Conditions Input Clamp Diode Voltage VOL 2.7 II = −18 mA VIK 0 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V 0–1.5V ±100 µA IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.0V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.6V IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < V O ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ V O ≤ 5.5V ∆ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC − 0.6V Output Current VI = GND or VCC Outputs Disabled (Note 6) Other Inputs at VCC or GND Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 7) TA = 25°C VCC (V) Min Typ Conditions Max Units CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 8) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 8) Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. 5 www.fairchildsemi.com 74LVTH646 DC Electrical Characteristics 74LVTH646 AC Electrical Characteristics TA = −40°C to +85°C Symbol CL = 50 pF, RL = 500Ω Parameter VCC = 3.3V ± 0.3V Min fMAX Maximum Clock Frequency 150 tPLH Propagation Delay Data to Output 1.8 Max VCC = 2.7V Min Max 150 5.7 1.8 MHz 6.3 tPHL Clock to A or B 1.8 5.0 1.8 5.6 tPLH Propagation Delay Data to Output 1.3 4.6 1.3 5.0 tPHL Data to A or B 1.3 4.6 1.3 5.3 tPLH Propagation Delay Data to Output 1.5 5.5 1.5 6.5 tPHL SBA or SAB to A or B 1.5 5.5 1.5 6.3 tPZH Output Enable Time 1.1 5.7 1.1 6.8 tPZL OE to A or B 1.1 6.3 1.1 7.3 tPHZ Output Disable Time 1.9 5.7 2.3 6.1 tPLZ OE to A or B 1.6 5.5 2.3 5.9 tPZH Output Enable Time 1.3 6.1 1.3 6.7 tPZL DIR to A or B 1.3 6.7 1.3 7.7 tPHZ Output Disable Time 1.5 6.2 1.5 7.1 1.5 5.6 1.5 6.3 tPLZ DIR to A or B tW Pulse Duration tS Setup Time tH Hold Time tOSHL Output to Output Skew (Note 9) Clock HIGH or LOW 3.3 3.3 A or B Before Clock, Data HIGH 1.2 1.5 A or B Before Clock, Data LOW 1.6 2.2 A or B after Clock 0.8 tOSLH Units ns ns ns ns ns ns ns ns ns 0.8 ns 1.0 1.0 1.0 1.0 ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance Symbol (Note 10) Typical Units CIN Input Capacitance Parameter VCC = 0V, VI = 0V or VCC Conditions 4 pF CI/O Input/Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.fairchildsemi.com 6 74LVTH646 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 7 www.fairchildsemi.com 74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8