ETC AD7318

PRELIMINARY TECHNICAL DATA
±0.5°C Accurate Digital Temperature Sensor and
a
Quad Voltage Output 12/10/8-Bit DAC
Preliminary Technical Data
ADT7316/7317/7318
FEATURES
ADT7316 - Four 12-Bit DACs
ADT7317 - Four 10-Bit DACs
ADT7318 - Four 8-Bit DACs
Buffered Voltage Output
Guaranteed Monotonic By Design Over All Codes
10-Bit Temperature to Digital Converter
Temperature range:
-40oC to +125oC
Temperature Sensor Accuracy of ±0.5oC
Supply Range : + 2.7 V to + 5.5 V
GENERAL DESCRIPTION
The ADT7316/7317/7318 combines a 10-Bit Temperature-to-Digital Converter and a quad 12/10/8-Bit DAC
respectively, in a 16-Lead QSOP package. This includes a
bandgap temperature sensor and a 10-bit ADC to monitor
and digitize the temperature reading to a resolution of
0.25oC. The ADT7316/17/18 operates from a single
+2.7V to +5.5V supply. The output voltage of the DAC
ranges from 0 V to 2VREF , with an output voltage settling
time of typ 7 msec. The ADT7316/17/18 provides two
serial interface options, a four-wire serial interface which
is compatible with SPITM, QSPITM, MICROWIRETM and
DSP interface standards; and a two-wire SMBus/I2 C interface. It features a standby mode that is controlled via
the serial interface.
DAC Output Range: 0 - 2VREF
µA
Power-Down Current 1µ
Internal 2.25 VRef Option
Double-Buffered Input Logic
Buffered / Unbuffered Reference Input Option
Power-on Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
On-Chip Rail-to-Rail Output Buffer Amplifier
The reference for the four DACs is derived either internally or from two reference pins (one per DAC pair) .The
outputs of all DACs may be updated simultaneously using
the software LDAC function or external LDAC pin. The
ADT7316/7317/7318 incorporates a power-on-reset circuit, which ensures that the DAC output powers-up to
zero volts and it remains there until a valid write takes
place.
I2C, SPITM, QSPITM, MICROWIRETM and DSP-Compatible 4wire Serial Interface
16-Lead QSOP Package
APPLICATIONS
Portable Battery Powered Instruments
Personal Computers
Telecommunications Systems
Electronic Test Equipment
Domestic Appliances
Process Control
ON-CHIP
TEMPERATURE
SENSOR
D-
8
ANALOG
MUX
A-TO-D
CONVERTER
VDD
SENSOR
VDD
VALUE
REGISTER
LIMIT
COMPARATOR
THIGH LIMIT
REGISTERS
DIGITAL MUX
7
ADDRESS POINTER
REGISTER
INTERNAL TEMPERATURE
VALUE REGISTER
DIGITAL MUX
D+
The ADT7316/7317/7318’s wide supply voltage range,
low supply current and SPI/I2 C-compatible interface,
make it ideal for a variety of applications, including personal computers, office equipment and domestic appliances.
TLOW LIMIT
REGISTERS
VDD Limit
REGISTERS
CONTROL CONFIG. 1
REGISTER
EXTERNAL TEMPERATURE
VALUE REGISTER
DAC A
REGISTERS
STRING
DAC A
2
VOUT-A
DAC B
REGISTERS
STRING
DAC B
1
VOUT-B
DAC C
REGISTERS
STRING
DAC C
16 VOUT-C
DAC D
REGISTERS
STRING
DAC D
15 VOUT-D
CONTROL CONFIG. 2
REGISTER
CONTROL CONFIG. 3
REGISTER
DAC CONFIGURATION
REGISTER
ADT7316/17/18
GAIN
SELECT
LOGIC
LDAC CONFIGURATION
REGISTER
STATUS
REGISTERS
POWER
DOWN
LOGIC
INTERRUPT MASK
REGISTERS
10
INT/INT
SMBus/SPI INTERFACE
INTERNAL
REFERENCE
6
5
VDD
GND
4
13
CS
SCL/SCLK
12
11
SDA/DIN DOUT/ADD
FUNCTIONAL BLOCK DIAGRAM
REV. Pr. O 01/’03
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
9
LDAC
3
14
VREF-AB
VREF-CD
I 2 C is a registered trademark of Philips Corporation
SPI and QSPI are trademarks of Motorola, INC.
MICROWIRE is a trademark of National Semiconductor Corporation.
The ADT7316/7317/7318 is protected by the following U.S. patent
numbers and by other intellectual property rights :
6,169,442
6,097,239
US Patent Pending
5,867,012
5,764174
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
ADT7316/ADT7317/ADT7318-SPECIFICATIONS1
(VDD=2.7 V to 5.5 V, GND=0 V, REFIN=2.25 V, unless otherwise noted)
Parameter 2
Min
Units
Preliminary Technical Data
Typ
Max
Conditions/Comments
8
±0.15
tbd
±0.02
±1
tbd
±0.25
Bits
LSB
LSB
LSB
Excluding Offset and Gain errors
Guaranteed Monotonic by design over all codes
10
±0.5
tbd
±0.05
±4
tbd
±0.5
Bits
LSB
LSB
LSB
Excluding Offset and Gain errors
Guaranteed Monotonic by design over all codes
20
±16
tbd
±0.9
±3
±0.5
±1.25
±0.5
60
Bits
LSB
LSB
LSB
% of FSR
LSB
% of FSR
LSB
mV
Upper Deadband
tbd
tbd
mV
Offset Error Drift5
Gain Error Drift5
-12
-5
-60
200
3,4
DAC DC PERFORMANCE
ADT7318
Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
ADT7317
Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
ADT7316
Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Lower Deadband
DC Power Supply Rejection Ratio 5
DC Crosstalk 5
12
±2
tbd
±0.02
±0.4
±0.3
Excluding Offset and Gain errors
Guaranteed Monotonic by design over all codes
Lower Deadband exists only if Offset Error is
Negative. See Figure 5.
Upper Deadband exists if VREF = VDD and Offset
plus Gain Error is positive. See Figure 6.
ppm of FSR/°C
ppm of FSR/°C
dB
∆V DD = ±10%.
µV
Reference Figure 4.
Internal Reference used. Averaging on.
THERMAL CHARACTERISTICS
INTERNAL TEMPERATURE
SENSOR
Accuracy @ VDD = 3.3V ±10%
±0.5
±2
Accuracy @ VDD = 5V ±5%
±2
±3
Resolution
Long Term Drift
Conversion Time
0.5
25.92
1.62
EXTERNAL TEMPERATURE
SENSOR
Accuracy @ VDD = 3.3V ±10%
Accuracy @ VDD = 5V ±5%
±2
±3
Resolution
Conversion Time
Output Source Current
±0.5
±2
±3
±1
±3
±4
10
°C
°C
°C
°C
°C
°C
Bits
°C/1000hrs
ms
ms
±1
±2
±3
±1.5
±3
±4
10
°C
°C
°C
°C
°C
°C
Bits
ms
ms
16.8
1.05
180
11
µA
µA
TA = 40°C
TA = 0°C to +85°C
TA = -40°C to +125°C
TA = 40°C
TA = 0°C to +85°C
TA = -40°C to +125°C
Equivalent to 0.25°C
Averaging (16 samples) on.
Averaging off.
External Transistor = 2N3906.
TA = 40°C.
TA = 0°C to +85°C.
TA = -40°C to +125°C
TA = 40°C.
TA = 0°C to +85°C
TA = -40°C to +125°C
Equivalent to 0.25°C
Averaging (16 samples) on.
Averaging off.
High Level
Low Level
VOLTAGE OUTPUT
8-Bit DAC Output
–2–
REV. PrO
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
Parameter2
Min
Resolution
Scale Factor
ADT7316/7317/7318
Typ
Max
1
10-Bit DAC Output
Resolution
Scale Factor
Units
8.79
17.58
°C
mV/°C
mV/°C
0-VREF Output. TA = -40°C to +125°C
0-2VREF Output. TA = -40°C to +125°C
2.2
4.39
°C
mV/°C
mV/°C
0-VREF Output. TA = -40°C to +125°C
0-2VREF Output. TA = -40°C to +125°C
43.43
2.715
ms
ms
0.25
ROUND ROBIN UPDATE RATE6
Time to complete one measurement cycle.
Averaging On
Averaging Off
DAC EXTERNAL
REFERENCE INPUT 7
VREF Input Range
VREF Input Range
VREF Input Impedance
1
0.25
37
74
Reference Feedthrough
Channel-to-Channel Isolation
ON-CHIP REFERENCE
Reference Voltage7
Temperature Coefficient 7
VDD
VDD
45
90
>10
-90
-75
V
V
kΩ
kΩ
MΩ
dB
dB
2.25
80
V
ppm/ °C
OUTPUT CHARACTERISTICS 7
Output Voltage 8
0.001
DC Output Impedance
Short Circuit Current
Power Up Time
LDAC Pulse Width
Ω
mA
mA
µs
µs
±1
0.8
µA
V
V
pF
ns
1.89
3
10
50
Buffered Reference Mode
Unbuffered Reference Mode
Unbuffered Reference Mode. 0-2 V REF Output Range.
Unbuffered Reference Mode. 0- V REF Output Range.
Buffered reference mode and Power-Down Mode
Frequency=10KHz
Frequency=10KHz
This is a measure of the minimum and maximum drive
capability of the output amplifier
V DD = +5V
V DD = +3V
Coming out of Power Down Mode. VDD = +5 V
Coming out of Power Down Mode. V DD = +3.3 V
V IN = 0V to V DD
All Digital Inputs
Input Filtering Suppresses Noise Spikes of Less than 50
ns
ns
2.4
0.4
1
V
V
mA
ISOURCE = I SINK = 200 µA
IOL = 3 mA
V OH = 5 V
50
0.8
pF
V
IOUT = 4 mA
2.5
µs
Fast-Mode I2C. See Figure 1
0
ns
See Figure 1
50
ns
See Figure 1
ns
ns
See Figure 1
See Figure 1
ns
ns
ns
See Figure 2
See Figure 2
See Figure 2
ns
See Figure 2
ns
See Figure 2
Output Capacitance, COUT
ALERT Output Saturation Voltage
I C TIMING CHARACTERISTICS
V
20
DIGITAL OUTPUT
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Current, IOH
2
V DD -0.001
0.5
25
16
2.5
5
DIGITAL INPUTS 7
Input Current
VIL, Input Low Voltage
VIH , Input High Voltage
Pin Capacitance
SCL, SDA Glitch Rejection
Conditions/Comments
9,10
Serial Clock Period, t 1
Data In Setup Time to SCL High, t2
Data Out Stable after SCL Low, t3
SDA Low Setup Time to SCL Low
(Start Condition), t4
SDA High Hold Time after SCL High
(Stop Condition), t5
SDA and SCL Fall Time, t6
50
90
SPI TIMING CHARACTERISTICS11, 12
CS to SCLK Setup Time, t 1
SCLK High Pulsewidth, t2
SCLK Low Pulse, t3
Data Access Time after
SCLK Falling edge, t413
Data Setup Time Prior
to SCLK Rising Edge, t5
REV. Pr.O
0
50
50
35
20
–3–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
Data Hold Time after
SCLK Rising Edge, t 6
CS to SCLK Hold Time, t7
0
0
CS to DOUT High Impedance, t 8
POWER REQUIREMENTS
VDD
VDD Settling Time
2.7
IDD (Normal Mode)14
IDD (Power Down Mode)
tbd
tbd
tbd
tbd
Power Dissipation
40
ns
ns
ns
5.5
50
V
ms
2
2.2
3
10
6.6
10
mA
mA
µA
µA
mW
µW
See Figure 2
See Figure 2
See Figure 2
VDD settles to within 10% of it’s final voltage
level.
VDD = +3.3V, VIH = VDD and VIL = GND
VDD = +5V, VIH = VDD and VIL = GND
VDD = +3.3V, VIH = VDD and VIL = GND
VDD = +5V, VIH = VDD and VIL = GND
VDD = +3.3 V. Using Normal Mode.
VDD = +3.3 V. Using Shutdown Mode.
Notes:
1
Temperature ranges are as follows: A Version: -40°C to +125°C.
2
See Terminology.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)
5
See Terminology.
6
Round Robin is the continuous sequential measurement of the following three channels : VDD , Internal Temperature and External Temperature.
7
Guaranteed by Design and Characterization, not production tested
8
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its
maximum voltage, V REF =V DD , "Offset plus Gain" Error must be positive.
9
The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I 2C specification. Switching off the input
filters improves the transfer rate but has a negative affect on the EMC behaviour of the part.
10
Guaranteed by design. Not tested in production.
11
Guaranteed by design and characterization, not production tested.
12
All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
13
Measured with the load circuit of Figure 3.
14
IDD spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
Specifications subject to change without notice.
DAC AC CHARACTERISTICS1
Parameter2
(VDD = +2.7V to +5.5 V; RL=4k7Ω to GND; CL=200pF to GND;
4K7Ω to VDD; All specifications TMIN to TMAX unless otherwise noted.)
Min Typ @ 25°C
Output Voltage Settling Time
ADT7318
ADT7317
ADT7316
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
6
7
8
0.7
12
0.5
1
0.5
3
200
-70
Max
Units
8
9
10
µs
µs
µs
V/µs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
Conditions/Comments
V REF =V DD =+5V
1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex)
1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex)
1/4 Scale to 3/4 Scale change (400 Hex to C00 Hex)
1 LSB change around major carry.
V REF =2V±0.1Vpp
V REF =2.5V±0.1Vpp. Frequency=10kHz.
NOTES
1
Guaranteed by Design and Characterization, not production tested
2
See Terminology
Specifications subject to change without notice.
t1
SC L
t4
t5
t2
SD A
DA T A IN
t3
SD A
DA T A O U T
t6
Figure 1. Diagram for I2C Bus Timing
–4–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
CS
t1
t7
t2
SCLK
t3
DIN
D7
D6
D5
t6
t5
D4
D3
D2
D1
t8
D0
X
X
X
X
X
X
X
D6
D5
D4
D3
D2
D1
D0
X
t4
DOUT
X
X
X
X
X
X
X
X
D7
Figure 2. Diagram for SPI Bus Timing
200 ␮A
TO
OUTPUT
PIN
I OL
1.6V
CL
50pF
2 00 ␮A
IO L
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
VDD
4Κ7Ω
To DAC
Ou tp ut
4Κ7Ω
200pF
Figure 4. Load Circuit for DAC Outputs
REV. Pr.O
–5–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
Table 1. I2C Address Selection
ABSOLUTE MAXIMUM RATINGS1
VDD to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
16-Lead QSOP Package
Power Dissipation2
Thermal Impedance3
θJA Junction-to-Ambient
θJC Junction-to-Case
IR Reflow Soldering
Peak Temperature
Time at Peak Temperature
Ramp-up Rate
Ramp-down Rate
–0.3 V to +7 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3V
–40°C to +125°C
–65°C to +150°C
+150°C
Low
1001 000
Float
1001 010
High
1001 011
(Tj max - TA) / θJA
PIN CONFIGURATION
QSOP
105.44 °C/W
38.8 °C/W
+220°C (-0/+5°C)
10 to 20 secs
2-3°C/sec
-6°C/sec
Vout -B
1
16 Vout -C
Vout -A
2
15 Vout -D
Vref -AB
3
14 Vref -CD
CS
4
GND
5
Notes:
1
I2C Address
ADD Pin
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Values relate to package being used on a 4-layer board.
3
Junction-to-Case resistance is applicable to components featuring a
preferential flow direction, eg. components mounted on a heat sink.
Junction-to-Ambient resistance is more useful for air-cooled PCBmounted components.
ADT7316/
7317/7318
TOP VIEW
13 SCL/SCLK
12 SDA/DIN
VDD
6
D+
7
10 INT/INT
D-
8
9
(Not to Scale)
11 DOUT/ADD
LDAC
ORDERING GUIDE
Model
Temperature Range
DAC Resolution
Package Description
Package Options
ADT7318ARQ
–40°C to +125°C
8-Bits
16-Lead QSOP
RQ-16
ADT7317ARQ
-40°C to +125°C
10-Bits
16-Lead QSOP
RQ-16
ADT7316ARQ
-40°C to +125°C
12-Bits
16-Lead QSOP
RQ-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADT7316/7317/7318 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–6–
WARNING!
ESD SENSITIVE DEVICE
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
ADT7316/7317/7318 PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
V O U TB
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
2
V OUT A
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
3
V REF AB
Reference Input Pin for DACs A and B. It may be configured as a buffered or unbuffered input
to both DACs A and B. It has an input range from 0.25 V to VDD in unbuffered mode and
from 1 V to VDD in buffered mode. DACs A and B default on power-up to this pin.
4
CS
SPI - Active low control Input. This is the frame synchronization signal for the input data.
When CS goes low, it enables the input register and data is transferred in on the rising edges
and out on the falling edges of the subsequent serial clocks. It is recommended that this pin be
tied high to VDD when operating the serial interface in I2C mode.
5
GND
6
V DD
Positive Supply Voltage, +2.7 V to +5.5 V. The supply should be decoupled to ground.
7
D+
Positive connection to external temperature sensor
8
D-
Negative connection to external temperature sensor
9
LDAC
Active low control input that transfers the contents of the input registers to their respective
DAC registers. A falling edge on this pin forces any or all DAC registers to be updated if the
input registers have new data. A minimum pulse width of 20ns must be applied to the LDAC
pin to ensure proper loading of a DAC register. This allows simultaneous update of all DAC
outputs. Bit C3 of Control Configuration 3 register enables LDAC pin. Default is with
LDAC pin controlling the loading of DAC registers.
10
INT/INT
Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active
high interrupt when temperature or VDD limits are exceeded. Default is active low.
11
DOUT/ADD
SPI - Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data
is clocked out on the falling edge of SCLK. Open Drain output - needs a pull-up resistor.
Ground Reference Point for all circuitry on the part. Analog and Digital Ground.
ADD - I2C serial bus address selection pin. Logic input. A low on this pin gives the address
1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address
1001 011. The I2C address set up by the ADD pin is not latched by the device until after this
address has been sent twice. On the 8th SCL cycle of the second valid communication, the
serial bus address is latched in. Any subsequent changes on this pin will have no affect on the
I2C serial bus address.
12
SDA/DIN
SDA - I2C Serial Data Input. I2C serial data that is loaded into the device’s registers is provided on this input.
DIN - SPI Serial Data Input. Serial data to be loaded into the device’s registers is provided on
this input. Data is clocked into a register on the rising edge of SCLK.
13
SCL/SCLK
14
V REF CD
Reference Input Pin for DACs C and D. It may be configured as a buffered or unbuffered
input to both DACs C and D. It has an input range from 0.25 V to VDD in unbuffered mode
and from 1 V to VDD in buffered mode. DACs C and D default on power-up to this pin.
15
V O U TD
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
16
V O U TC
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
REV. Pr.O
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock
data out of any register of the ADT7316/7317/7318 and also to clock data into any register
that can be written to.
–7–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
TERMINOLOGY
RELATIVE ACCURACY
Relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. Typical INL versus Code plots can be seen in
TPCs 1, 2 and 3.
is significantly accelerated due to the increase in rates of
reaction within the semiconductor material. As a result of
this operation, the lifetime of an integrated circuit is significantly accelerated due to the increase in rates of reaction within the semiconductor material.
DC POWER-SUPPLY REJECTION RATIO (PSRR)
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified differential
nonlinearity of ±1 LSB maximum ensures monotonicity.
This DAC and Temperature Sensor ADC is guaranteed
monotonic by design. Typical DAC DNL versus Code
plots can be seen in TPCs 4, 5 and 6.
OFFSET ERROR
This is a measure of the offset error of the DAC and the
output amplifier. (See Figures 5 and 6.) It can be negative
or positive. It is expressed as a percentage of the full scale
range.
OFFSET ERROR MATCH
This is the difference in Offset Error between any two
channels.
This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the
change in VOUT to a change in VDD for full-scale output of
the DAC. It is measured in dBs. VREF is held at 2 V and
VDD is varied ±10%.
DC CROSSTALK
This is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC
while monitoring another DAC. It is expressed in µV.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the
DAC output to the reference input when the DAC output
is not being updated (i.e., LDAC is high). It is expressed
in dBs.
CHANNEL-TO-CHANNEL ISOLATION
GAIN ERROR
This is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic
from the ideal expressed as a percentage of the full-scale
range.
GAIN ERROR MATCH
This is the difference in Gain Error between any two
channels.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with
changes in temperature. It is expressed in (ppm of fullscale range)/°C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of fullscale range)/°C.
This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of
another DAC. It is measured in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the
impulse injected into the analog output when the code in
the DAC register changes state. It is normally specified as
the area of the glitch in nV secs and is measured when the
digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to
011 . . . 11).
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected
into the analog output of a DAC from the digital input
pins of the device but is measured when the DAC is not
being written to. It is specified in nV secs and is measured
with a full-scale change on the digital input pins, i.e.,
from all 0s to all 1s or vice versa.
LONG TERM TEMPERATURE DRIFT
This is a measure of the change in temperature error with
the passage of time. It is expressed in °C/1000hrs. The
concept of long-term stability has been used for many
years to describe by what amount an IC’s parameter would
shift during its lifetime. This is a concept that has been
typically applied to both voltage references and monolithic
temperature sensors. Unfortunately, integrated circuits
cannot be evaluated at room temperature (25°C) for 10
years or so to determine this shift. As a result, manufacturers very typically perform accelerated life-time testing of
integrated circuits by operating ICs at elevated temperatures (between 125°C and 150°C) over a shorter period of
time (typically, between 500 and 1000 hours). As a result
of this operation, the lifetime of an integrated circuit
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one
DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of
another DAC. It is measured in stand-alone mode and is
expressed in nV secs.
ANALOG CROSSTALK
This is the glitch impulse transferred to the output of one
DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a fullscale code change (all 0s to all 1s and vice versa) while
keeping LDAC high. Then pulse LDAC low and moni–8–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
tor the output of the DAC whose digital code was not
changed. The area of the glitch is expressed in nV secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one
DAC due to a digital code change and subsequent output change of another DAC. This includes both digital
and analog crosstalk. It is measured by loading one of the
DACs with a full-scale code change (all 0s to all 1s and
vice versa) with LDAC low and monitoring the output
of another DAC. The energy of the glitch is expressed in
nV secs.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used
as the reference for the DAC, and the THD is a measure of
the harmonics present on the DAC output. It is measured
in dBs.
ROUND ROBIN
This term is used to describe the ADT7316/17/18 cycling
through the available measurement channels in sequence,
taking a measurement on each channel.
DAC OUTPUT SETTLING TIME
MULTIPLYING BANDWIDTH
The amplifiers within the DAC have a finite bandwidth.
The multiplying bandwidth is a measure of this. A sine
wave on the reference (with full-scale code loaded to the
DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls
to 3 dB below the input.
This is the time required, following a prescribed data
change, for the output of a DAC to reach and remain
within ±0.5 LSB of the final value. A typical prescribed
change is from 1/4 scale to 3/4 scale.
GAIN ERROR
+
OFFSET ERROR
OUTPUT
VOL TAGE
NEGATIVE
OFFSET
ERROR
DAC CODE
ACTUA L
GAIN ERROR
+
OFFSET ERROR
IDEAL
UPPER
DEADBAND
CODES
OUTPUT
VOL TAGE
L OWER
DEADBAND
CODES
AMPL IFIER
FOOTROOM
ACTUAL
IDEAL
POSITIVE
OFFSET
ERROR
NEGATIVE
OFFSET
ERROR
Figure 5. Transfer Function with Negative Offset
REV. Pr.O
FULL SCALE
DAC CODE
Figure 6. Transfer Function with Positive Offset (VREF = VDD)
–9–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
0
0
0
0
0
0
TITLE
0
0
0
0
0
TPC 1. ADT7318 Typical INL Plot
0
TITLE
0
0
0
0
0
0
0
0
0
TITLE
0
0
0
0
0
TITLE
0
0
TITLE
0
0
0
0
TITLE
0
0
TPC 7. ADT7318 INL and DNL
Error vs VREF
0
0
TITLE
0
0
0
0
0
0
0
TITLE
0
0
0
TPC 6. ADT7316 Typical DNL Plot
0
0
0
0
0
0
0
0
0
0
0
TPC 5. ADT7317 Typical DNL Plot
0
0
0
0
0
0
0
TPC 3. ADT7316 Typical INL Plot
TITLE
TITLE
TITLE
0
0
TPC 4. ADT7318 Typical DNL Plot
TITLE
0
0
TPC 2. ADT7317 Typical INL Plot
0
0
0
TITLE
0
0
TITLE
TITLE
TITLE
0
0
0
0
0
TITLE
0
0
0
TPC 8. ADT7318 INL Error and DNL
Error vs Temperature
–10–
0
0
0
0
0
0
TITLE
0
0
0
TPC 9. ADT7318 Offset Error and Gain
Error vs Temperature
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
0
0
0
0
0
TITLE
0
0
0
0
TPC 10. Offset Error and Gain
Error vs VDD
0
0
0
TITLE
0
0
0
0
0
0
0
TITLE
0
0
0
0
0
0
TITLE
0
0
0
0
0
0
TITLE
0
0
0
0
0
0
0
0
0
0
TITLE
0
0
0
0
0
0
0
TITLE
TPC 15. Half-Scale Settling (1/4 to 3/4
Scale Code Change)
TITLE
TITLE
TITLE
0
0
0
0
0
0
0
TPC 12. Supply Current vs. DAC Code
0
TPC 13. Supply Current vs. Supply Volt- TPC 14. Power-Down Current vs. Supply
age
Voltage
0
0
0
0
0
0
0
0
0
0
TITLE
TITLE
0
TPC 11. VOUT Source and Sink Current
Capability
0
0
0
TITLE
0
0
TITLE
0
TITLE
TITLE
0
0
0
0
0
TITLE
0
0
0
0
0
0
0
0
0
TITLE
0
0
0
TPC 16. Exiting Power-Down to Midscale TPC 17. ADT7316 Major-Code Transition TPC 18. Multiplying Bandwidth (SmallGlitch Energy
Signal Frequency Response)
REV. Pr.O
–11–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
0
TITLE
TITLE
0
0
0
0
0
0
0
TITLE
0
0
0
0
0
0
TPC 19. Full-Scale Error vs. VREF
0
TITLE
0
0
0
0
TITLE
TITLE
0
TPC 20. DAC-to-DAC Crosstalk
0
0
0
0
0
0
0
0
TITLE
0
0
0
0
0
TPC 21. PSRR vs Supply Ripple Frequency
0
0
0
0
TITLE
0
0
0
TPC 22. Temperature Error @ 3.3 V and 5 V
–12–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
ADT7316/17/18 OPERATION
POWER-UP CALIBRATION
Directly after the power-up calibration routine the
ADT7316/17/18 goes into idle mode. In this mode the
device is not performing any measurements and is fully
powered up. All four DAC outputs are at 0V.
It is recommended that no communication to the part is
initiated until approximately 5ms after VDD has settled to
within 10% of it’s final value. It is generally accepted that
most systems take a maximum of 50ms to power-up.
Power-up time is directly related to the amount of
decoupling on the voltage supply line.
To begin monitoring, write to Control Configuration 1
(address = 18h) register and set bit C0 = 1. The
ADT7316/17/18 goes into it’s power-up default measurement mode, which is Round Robin. The device proceeds
to take measurements on the VDD channel, the internal
temperature sensor channel and the external temperature
sensor channel. Once it finishes taking measurements on
the external temperature sensor channel the device immediately loops back to start taking measurements on the
VDD channel and repeats the same cycle as before. This
loop continues until the monitoring is stopped by resetting
bit C0 of Control Configuration 1 register to 0. It is also
possible to continue monitoring as well as switching to
Single channel mode by writing to Control Configuration
2 register (address = 19h) and setting bit C4 = 1. Further
explanation of the Single channel and Round Robin measurement modes are given in later sections. All measurement channels have averaging enabled on them on
power-up. Averaging forces the device to take an average
of 16 readings before giving a final measured result. To
disable averaging and consequently decrease the conversion time by a factor of 16, set C5 = 1 in Control Configuration 2 register.
Controlling the DAC outputs can be done by writing to
the DACs MSB and LSB registers (addresses 10h - 17h).
The power-up default setting is to have a low going pulse
on the LDAC pin controlling the updating of the DAC
outputs from the DAC registers. You can configure the
updating of the DAC outputs to be controlled by methods
other than the LDAC pin by setting C3 = 1 of the Control
Configuration 3 register (address = 1Ah). The DAC Configuration register (address = 1Bh) and the LDAC Configuration register (address = 1Ch) can now be used to
control the DAC updating. These two registers also control the output range of the DACs, enabling or disabling
the external reference buffer and selecting between the
internal or external reference. DAC A and DAC B outputs
can be configured to give a voltage output proportional to
the temperature of the internal and external temperature
sensors respectively.
The dual serial interface defaults to the I2C protocol on
power-up. To select and lock in the SPI protocol please
follow the selection process as described in the Serial
Interface Selection section. The I2C protocol cannot be
locked in, while the SPI protocol in selection is automatically locked in. The interface can only be switched back to
be I2C when the device is powered off and on. When using
I2C the CS pin should be tied to either VDD or GND.
There are a number of different operating modes on the
ADT7316/17/18 devices and all of them can be controlled
by the configuration registers. These features consist of
the INT/INT pin, enabling and disabling interrupts, polarity of the INT/INT pin, enabling and disabling the
averaging on the measurement channels, SMBus timeout
and software reset.
REV. Pr.O
During this 5ms after VDD has settled, the part is performing a calibration routine and any communication to the
device will interrupt this routine and could cause erroneous temperature measurements. If it not possible to have
VDD at it’s nominal value by the time 50ms has elapsed or
that communication to the device has started prior to VDD
settling then it is recommended that a measurement be
taken on the VDD channel before a temperature measurement is taken. The VDD measurement is used to calibrate
out any temperature measurement error due to different
supply voltage values.
FUNCTIONAL DESCRIPTION - VOLTAGE OUTPUT
DAC
The ADT7316/7317/7318 has four resistor-string DACs
fabricated on a CMOS process with resolutions of 12, 10
and 8 bits respectively. They contain four output buffer
amplifiers and is written to via an I2C serial interface or
an SPI serial interface. See Serial Interface Selection section for more information.
The ADT7316/7317/7318 operates from a single supply
of 2.7 V to 5.5 V and the output buffer amplifiers provide
rail-to-rail output swing with a slew rate of 0.7 V/µs.
DACs A and B share a common external reference input,
namely VREFAB. DACs C and D share a common external
reference input, namely VREFCD. Each reference input
may be buffered to draw virtually no current from the
reference source, or unbuffered to give a reference input
range from GND to VDD. The devices have a power-down
mode, in which all DACs may be turned off completely
with a high-impedance output.
Each DAC output will not be updated until it receives the
LDAC command. Therefore while the DAC registers
would have been written to with a new value, this value
will not be represented by a voltage output until the DACs
have received the LDAC command. Reading back from
any DAC register prior to issuing an LDAC command
will result in the digital value that corresponds to the
DAC output voltage. Thus the digital value written to the
DAC register cannot be read back until after the LDAC
command has been initiated. This LDAC command can
be given by either pulling the LDAC pin low (falling
edge loads DACs), setting up Bits D4 and D5 of DAC
Configuration register (Address = 1Bh) or using the
LDAC register (Address = 1Ch).
When using the LDAC pin to control DAC register loading, the low going pulse width should be 20ns minimum.
The LDAC pin has to go high and low again before the
DAC registers can be reloaded.
–13–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
Digital-to-Analog Section
DAC External Reference Inputs
The architecture of a DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The
voltage at the VREF pin or the on-chip reference of 2.25 V
provides the reference voltage for the corresponding DAC.
Figure 7 shows a block diagram of the DAC architecture.
Since the input coding to the DAC is straight binary, the
ideal output voltage is given by:
VREF * D
VOUT = ---------2N
where D=decimal equivalent of the binary code which is
loaded to the DAC register;
0-255 for ADT7318 (8-Bits)
0-1023 for ADT7317 (10-Bits)
0-4095 for ADT7316 (12-Bits)
N = DAC resolution.
There is a reference pin for each pair of DACs. The reference inputs are buffered but can also be individually configured as unbuffered.
VREFAB
GAIN MODE
(GAIN=1 OR 2)
Int VREF
INPUT
REGISTER
DAC
REGISTER
OUTPUT BUFFER
AMPLIFIER
Figure 7. Single DAC channel architecture
Resistor String
The resistor string section is shown in Figure 8. It is simply a string of resistors, each of value 603Ω approximately. The digital code loaded to the DAC register
determines at what node on the string the voltage is tapped
off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it
is guaranteed monotonic.
R
R
R
TO OUTPUT
AMPLIFIER
STRING
DAC A
STRING
DAC B
Figure 9. DAC Reference Buffer Circuit
If there is a buffered reference in the circuit, there is no
need to use the on-chip buffers. In unbuffered mode the
input impedance is still large at typically 90 kΩ per reference input for 0-VREF output mode and 45 kΩ for 0-2VREF
output mode.
VOUTA
RESISTOR
STRING
2 . 25 V
I nte rn a l V R EF
The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However
if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as VDD since
there is no restriction due to headroom and footroom of
the reference amplifier.
REFERENCE
BUFFER
BUFFER
SELECT
SIGNAL
VRE F-AB
The buffered/unbuffered option is controlled by the DAC
Configuration Register (address 1Bh, see data register
descriptions). The LDAC Configuration register controls
the option to select between internal and external voltage
references. The default setting is for external reference
selected.
Output Amplifier
The output buffer amplifier is capable of generating output voltages to within 1mV of either rail. Its actual range
depends on the value of VREF, GAIN and offset error.
If a gain of 1 is selected (Bits 0-3 of DAC Configuration
register = 0) the output range is 0.001 V to VREF.
If a gain of 2 is selected (Bits 0-3 of DAC Configuration
register = 1) the output range is 0.001 V to 2VREF. However because of clamping the maximum output is limited
to VDD - 0.001V.
The output amplifier is capable of driving a load of 4k7kΩ
to VDD or 4k7kΩ to GND in parallel with 200pF to
GND. See Figure 4. The source and sink capabilities of
the output amplifier can be seen in the plot in TPC 11.
The slew rate is 0.7V/µs with a half-scale settling time to
+/-0.5 LSB (at 8 bits) of 6µs.
THERMAL VOLTAGE OUTPUT
R
R
Figure 8. Resistor String
The ADT7316/17/18 has the capability of outputting a
voltage that is proportional to temperature. DAC A output
can be configured to represent the temperature of the internal sensor while DAC B output can be configured to
represent the external temperature sensor. Bits C5 and C6
of Control Configuration 3 register select the temperature
–14–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
proportional output voltage. Each time a temperature
measurement is taken the DAC output is updated. The
output resolution for the ADT7318 is 8 bits with 1°C
change corresponding to one LSB change. The output
resolution for the ADT7316 and ADT7317 is capable of
10 bits with 0.25°C change corresponding to one LSB
change. The default output resolution for the ADT7316
and ADT7317 is 8 bits. To increase this to 10 bits, set
C1 = 1 of Control Configuration 3 register. The default
output range is 0V-VREF and this can be increased to 0V2VREF. Increasing the output voltage span to 2VREF can be
done by setting D0 = 1 for DAC A (Internal Temperature
Sensor) and D1 = 1 for DAC B (External Temperature
Sensor) in DAC Configuration register (address 1Bh).
1.12V
+87
-1
+127
1.47V
+127
+39
UDB*
1.5V
UDB*
+42
UDB*
2V
UDB*
+99
UDB*
2.25V
UDB*
+127
UDB*
* Upper deadband has been reached. DAC output is not capable of
increasing. Reference Figure 6.
Table 3.
O/P Voltage
The output voltage is capable of tracking a max temperature range of -128°C to +127°C but the default setting is 40°C to +127°C. If the output voltage range is 0V-VREF
(VREF = 2.25 V) then this corresponds to 0V representing
-40°C and 1.48V representing +127°C. This of course
will give an upper deadband between 1.48V and VREF.
Thermal Voltage Output, (0V-2VREF)
Default °C
Max °C
Sample °C
0V
-40
-128
0
0.25V
-26
-114
14
0.5V
+12
-100
+28
0.75V
+3
-85
43
1V
+17
-71
+57
1.12V
+23
-65
+63
1.47V
+43
-45
+83
1.5V
+45
-43
+85
2V
+73
-15
+113
2.25V
+88
0
+127
2.5V
+102
+14
UDB*
2.75V
+116
+28
UDB*
3V
UDB*
+42
UDB*
3.25V
UDB*
+56
UDB*
3.5V
UDB*
+70
UDB*
3.75V
UDB*
+85
UDB*
Offset Register Code(d) = (-40) + 128
4V
UDB*
+99
UDB*
= 88d = 58h
4.25V
UDB*
+113
UDB*
Since a negative temperature has been inputted into the
equation, DB7 (MSB) of the Offset Register code is set to
a 1. Therefore 58h becomes D8h.
4.5V
UDB*
+127
UDB*
The Internal and External Analog Temperature Offset
registers can be used to vary this upper deadband and consequently the temperature that 0V corresponds to. Tables
2 and 3 give examples of how this is done using a DAC
output voltage span of VREF and 2VREF respectively. Simply write in the temperature value, in 2’s complement
format, that you want 0V to start at. For example, if you
are using the DAC A output and you want 0V to start at 40°C then program D8h into the Internal Analog Temperature Offset register (address 21h). This is an 8-bit
register and thus only has a temperature offset resolution
of 1°C for all device models. Use the following formulas
to determine the value to program into the offset registers.
Negative temperatures : Offset Register Code(d)* = (0V Temp) + 128
*D7 of Offset Register Code is set to 1 for negative temperatures.
Example :
* Upper deadband has been reached. DAC output is not capable of
increasing. Reference Figure 6.
58h + DB7(1) ⇒ D8h
The following equation is used to work out the various
temperatures for the corresponding 8-bit DAC output :-
Positive temperatures : -
8-Bit Temp = (DAC O/P ÷ 1 LSB) + ( 0V Temp)
Offset Register Code(d) = 0V Temp
For example, if the output is 1.5V, VREF = 2.25 V, 8-bit
DAC has an LSB size = 2.25V/256 = 8.79x10-3, and 0V
Temp is at -128°C then the resultant temperature works
out to be :-
Example :
Offset Register Code (d) = 10d = 0Ah
Table 2.
O/P Voltage
Thermal Voltage Output (0V-VREF)
Default °C
Max °C
Sample °C
0V
-40
-128
0
0.5V
+17
-71
+56
1V
+73
-15
+113
REV. Pr.O
(1.5 ÷ 8.79x10-3) + (-128) = +43°C
The following equation is used to work out the various
temperatures for the corresponding 10-bit DAC output :10-Bit Temp = ((DAC O/P ÷ 1 LSB)x0.25) + ( 0V Temp)
–15–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
VDD
I
N xI
I BIAS
OPTIONAL CAPACITOR, UP TO
3nF MAX. CAN BE ADDED TO
IMPROVE HIGH FREQUENCY
NOISE REJECTION IN NOISY
ENVIRONMENTS
V OUT+
D+
TO ADC
C1
REMOTE
SENSING
TR ANSISTOR
(2N3906)
DBIAS
DIODE
LOWPASS FILTER
fc = 65kHz
VO UT-
Figure 10. Signal Conditioning for External Diode temperature Sensors
For example, if the output is 0.4991V, VREF = 2.25 V, 10bit DAC has an LSB size = 2.25V/1024 = 2.197x10-3,
and 0V Temp is at -40°C then the resultant temperature
works out to be :((0.4991 ÷2.197x10-3)x0.25) + (-40) = +16.75°C
Figure 11 shows a graph of DAC output vs temperature
for a VREF = 2.25 V.
2.25
2.10
1.95
0 V = -128'C
D A C O U T P U T (V )
1.80
0 V = -40'C
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0 V = 0'C
0.30
0.15
-128 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
0.00
10
20
30
40
50
60
70
80
90 100 110 120 127
FUNCTIONAL DESCRIPTION - MEASUREMENT
TEMPERATURE SENSOR
The ADT7316/7317/7318 contains an A-D converter with
special input signal conditioning to enable operation with
external and on-chip diode temperature sensors. When the
ADT7316/7317/7318 is operating in single channel mode,
the A to D converter continually processes the measurement taken on one channel only. This channel is
preselected by bits C0 and C1 in Control Configuration 2
Register (address 19h). When in Round Robin mode the
analog input multiplexer sequentially selects the VDD input channel, the on-chip temperature sensor to measure its
internal temperature and then the external temperature
sensor. These signals are digitized by the ADC and the
results stored in the various Value Registers.
The measured results are compared with the Internal and
External, THIGH and TLOW limits. These temperature
limits are stored in on-chip registers. If the temperature
limits are not masked out then any out of limit comparisons generate flags that are stored in Interrupt Status 1
Register. One or more out-of limit results will cause the
INT/INT output to pull either high or low depending on
the output polarity setting.
Theoretically, the temperature sensor and ADC can measure temperatures from -128oC to +127oC with a resolution of 0.25oC. However, temperatures outside TA are
outside the guaranteed operating temperature range of the
device. Temperature measurement from -128oC to
+127oC is possible using an external sensor.
Temperature ('C)
Figure 11. DAC Output vs Temperature, VREF = 2.25 V
Temperature measurement is initiated by three methods.
The first method is applicable when the part is in single
channel measurement mode. The temperature is measured
16 times and internally averaged to reduce noise. The
total time to measure a temperature channel is typically
25.92ms (1.62ms x 16) for the internal temperature sensor
and 16.8ms (1.05ms x 16) for the external temperature
–16–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
V DD
I
NxI
IBIAS
V OUT+
TO A DC
VOUTINTERNAL
SENSE
TRA NSISTOR
BIAS
DIODE
Figure 12. Top Level Structure of Internal Temperature Sensor
sensor. The new temperature value is loaded into the
Temperature Value Register and ready for reading by the
I2C or SPI interface. The user has the option of disabling
the averaging by setting a bit (Bit 5) in the Control Configuration Register 2 (address 19h). The ADT7316/7317/
7318 defaults on power-up with the averaging enabled.
up the third and final monitoring channel. You can select
the VDD channel for single channel measurement by setting Bit C4 = 1 and setting Bits C0 to C2 to all 0’s in
Control Configuration 2 register.
When measuring the VDD value, the reference for the
ADC is sourced from the Internal Reference. Table 4
shows the data format. As the max VDD voltage measurable is 7 V, internal scaling is performed on the VDD voltage to match the 2.25V internal reference value. Below is
an example of how the transfer function works.
The second method is applicable when the part is in
Round Robin measurement mode. The part measures both
the internal and external temperature sensors as it cycles
through all possible measurement channels. The two temperature channels are measured each time the part runs a
round robin sequence. In round robin mode the part is
continuously measuring all channels.
VDD = 5 V
ADC Reference = 2.25 V
Temperature measurement is also initiated after every read
or write to the part when the part is in either single channel measurement mode or Round Robin measurement
mode. Once serial communication has started, any conversion in progress is stopped and the ADC reset. Conversion
will start again immediately after the serial communication has finished. The temperature measurement proceeds
normally as described above.
1 LSB = ADC Reference / 2^10 = 2.25 / 1024 =
2.197mV
Scale Factor = Fullscale VCC / ADC Reference = 7 / 2.25
= 3.11
Conversion Result = VDD / ((7/Scale Factor) x LSB size)
V DD MONITORING
The ADT7316/17/18 also has the capability of monitoring
it’s own power supply. The part measures the voltage on
it’s VDD pin to a resolution of 10 bits. The resultant value
is stored in two 8-bit registers, the two LSBs stored in
register address 03h and the eight MSBs are stored in
register address 06h. This allows the user to have the option of just doing a one byte read if 10-bit resolution is not
important. The measured result is compared with VHIGH
and VLOW limits. If the VDD interrupt is not masked out
then any out of limit comparison generates a flag in Interrupt Status 2 Register and one or more out-of-limit results
will cause the INT/INT output to pull either high or low
depending on the output polarity setting.
Measuring the voltage on the VDD pin is regarded as
monitoring a channel. Therefore, along with the Internal
and External temperature sensors the VDD voltage makes
REV. Pr.O
–17–
= 5 / (3.11 x 2.197mV)
= 2DBh
TABLE 4. VDD Data Format, VREF = 2.25V
VDD Value
Digital Output
Binary
Hex
2.5 V
01 0110 1110
16E
3V
01 1011 0111
1B7
3.5 V
10 0000 0000
200
4V
10 0100 1001
249
4.5 V
10 1001 0010
292
5V
10 1101 1011
2DB
5.5 V
11 0010 0100
324
6V
11 0110 1101
36D
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
S/W Reset
Internal
Temp
INTERRUPT
STATUS
REGISTER 1
(TEMP and Ext.
Diode Check)
STATUS BITS
External
Temp
VDD
INTERRUPT
MASK
REGISTERS
INTERRUPT
STATUS
REGISTER 2
(VDD)
INT/INT
(Latched Output)
Diode
Fault
STATUS BIT
WATCHDOG
LIMIT
COMPARISONS
INT/INT
ENABLE BIT
CONTROL
CONFIGURATION
REGISTER 1
Read Reset
Figure 13. ADT7316/17/18 Interrupt Structure
6.5 V
11 1011 0110
3B6
7V
11 1111 1111
3FF
The time taken to monitor all channels will normally not
be of interest, as the most recently measured value can be
read at any time.
For applications where the Round Robin time is important, it can be easily calculated.
ON-CHIP REFERENCE
The ADT7316/17/18 has an on-chip 1.2 V band-gap reference which is gained up by a switched capacitor amplifier to give an output of 2.25 V. The amplifier is powered
up for the duration of the device monitoring phase and is
powered down once monitoring is disabled. This saves on
current consumption. On power-up the default mode is to
have the internal reference selected as the reference for the
ADC. The ADC is used for measuring VDD, internal and
external temperature sensors. The internal reference is
always used when measuring VDD, the internal and external temperature sensors. The external reference is the
default power-up reference for the DACs.
As mentioned previously a conversion on the internal temperature channel takes 25.92 ms, on the external temperature channel it takes 16.8ms and on the VDD channel it
takes 712 us. These values are typical times and the channels have averaging on. This means that each channel is
measured 16 times and internally averaged to reduce
noise.
The total cycle time for voltage and temperature channels
is therefore nominally :
25.92ms + 16.8ms + 712µs = 43.432 ms
The total cycle time with averaging off is:
ROUND ROBIN MEASUREMENT
43.432 ms / 16 = 2.7145 ms
On power-up the ADT7316/17/18 goes into Round Robin
mode but monitoring is disabled. Setting Bit C0 of Configuration Register 1 to a 1 enables conversions. It sequences through the three channels of VDD , Internal
temperature sensor and External temperature sensor and
takes a measurement from each. Once the conversion is
completed on the external temperature sensor, the device
loops around for another measurement cycle on all three
channels. This method of taking a measurement on all
three channels in one cycle is called Round Robin. Setting
Bit 4 of Control Configuration 2 (address 19h) disables
the Round Robin mode and in turn sets up the single
channel mode. The single channel mode is where only one
channel, eg. Internal temperature sensor, is measured in
each conversion cycle.
SINGLE CHANNEL MEASUREMENT
Setting C4 of Control Configuration 2 register enables the
single channel mode and allows the ADT7316/17/18 to
focus on one channel only. A channel is selected by writing to bits C0:C2 in register Control Configuration 2
register. For example to select the VDD channel for monitoring, write to the Control Configuration 2 register and
set C4 to 1 (if not done so already), then write all 0’s to
bits C0 to C2 . All subsequent conversions will be done
on the VDD channel only. To change the channel selection
to the Internal temperature channel, write to the Control
Configuration 2 register and set C0 = 1. When measuring
in single channel mode, conversions on the channel selected occur directly after each other. Any communication
–18–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
INTERNAL TEMPERATURE MEASUREMENT
erenced to ground, but is biased above ground by an internal diode at the D- input. As the sensor is operating in a
noisy environment, C1 is provided as a noise filter. See
the section on layout considerations for more information
on C1.
The ADT7316/7317/7318 contains an on-chip bandgap
temperature sensor, whose output is digitized by the onchip ADC. The temperature data is stored in the Internal
Temperature Value Register. As both positive and negative temperatures can be measured, the temperature data is
stored in two's complement format, as shown in Table 5.
The thermal characteristics of the measurement sensor
could change and therefore an offset is added to the measured value to enable the transfer function to match the
thermal characteristics. This offset is added before the
temperature data is stored. The offset value used is stored
in the Internal Temperature Offset Register.
LAYOUT CONSIDERATIONS
to the ADT7316/17/18 stops the conversions but they are
restarted once the read or write operation is completed.
MEASUREMENT METHOD
EXTERNAL TEMPERATURE MEASUREMENT
The ADT7316/7317/7318 can measure the temperature of
one external diode sensor or diode-connected transistor.
The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative
temperature coefficient of about -2mV/oC. Unfortunately,
the absolute value of Vbe varies from device to device, and
individual calibration is required to null this out, so the
technique is unsuitable for mass-production.
The time taken to measure the external temperature can
be reduced by setting C0 of Control Configuration 3 register (1Ah). This increases the ADC clock speed from
1.4KHz to 22KHz but the analog filters on the D+ and
D- input pins are switched off to accommodate the higher
clock speeds. Running at the slower ADC speed and with
averaging on, the time taken to measure the external temperature is 16.8ms while on the fast ADC this time is
reduced to 712µs.
To measure ∆Vbe, the sensor is switched between operating
currents of I and N x I. The resulting waveform is passed
through a lowpass filter to remove noise, thence to a chopper-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce
a DC voltage proportional to ∆Vbe. This voltage is measured by the ADC to give a temperature output in 8-bit
two’s complement format. To further reduce the effects of
noise, digital filtering is performed by averaging the results of 16 measurement cycles.
Digital boards can be electrically noisy environments, and
care must be taken to protect the analog inputs from
noise, particularly when measuring the very small voltages
from a remote diode sensor. The following precautions
should be taken:
1. Place the ADT7316/17/18 as close as possible
remote sensing diode. Provided that the worst
sources such as clock generators, data/address
CRTs are avoided, this distance can be 4 to 8
to the
noise
buses and
inches.
2. Route the D+ and D- tracks close together, in parallel,
with grounded guard tracks on each side. Provide a
ground plane under the tracks if possible.
3. Use wide tracks to minimize inductance and reduce
noise pickup. 10 mil track minimum width and spacing
is recommended.
GND
10 mil.
10 mil.
The technique used in the ADT7316/7317/7318 is to
measure the change in Vbe when the device is operated at
two different currents.
D+
10 mil.
10 mil.
D-
This is given by:
10 mil.
10 mil.
∆Vbe = KT/q x ln(N)
GND
10 mil.
where:
Figure 14. Arrangement of Signal Tracks
K is Boltzmann’s constant
q is charge on the carrier
T is absolute temperature in Kelvins
N is ratio of the two currents
Figure 10 shows the input signal conditioning used to
measure the output of an external temperature sensor.
This figure shows the external sensor as a discrete substrate transistor. If a PNP transistor is used the base is
connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected
to the D- input and the base to the D+ input.
We recommend that a 2N3906 be used as the external
transistor.
4. Try to minimize the number of copper/solder joints,
which can cause thermocouple effects. Where copper/
solder joints are used, make sure that they are in both
the D+ and D- path and at the same temperature.
Thermocouple effects should not be a major problem as
1oC corresponds to about 240µV, and thermocouple
voltages are about 3µV/oC of temperature difference.
Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages
should be much less than 200mV.
5. Place 0.1µF bypass and 2200pF input filter capacitors
close to the ADT7316/17/18.
To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not refREV. Pr.O
–19–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
6. If the distance to the remote sensor is more than 8
inches, the use of twisted pair cable is recommended.
This will work up to about 6 to 12 feet.
INTERRUPTS
7. For really long distances (up to 100 feet) use shielded
twisted pair such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D- and the shield
to GND close to the ADT7316/17/18. Leave the remote end of the shield unconnected to avoid ground
loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect
the measurement. When using long cables, the filter capacitor may be reduced or removed.
Cable resistance can also introduce errors. 1⍀ series resistance introduces about 0.5oC error.
TEMPERATURE VALUE FORMAT
One LSB of the ADC corresponds to 0.25°C. The ADC
can theoretically measure a temperature span of 255°C.
The internal temperature sensor is guaranteed to a low
value limit of -40°C. It is possible to measure the full
temperature span using the external temperature sensor.
The temperature data format is shown in Tables 5.
The result of the internal or external temperature measurements is stored in the temperature value registers, and
is compared with limits programmed into the Internal or
External High and Low Registers.
TABLE 5. Temperature Data Format (Internal and
External Temperature)
Temperature
Digital Output
DB9..........DB0
-40 °C
11 0110 0000
-25 °C
11 1001 1100
-10 °C
11 1101 1000
-0.25 °C
11 1111 1111
0 °C
00 0000 0000
+0.25 °C
00 0000 0001
+10 °C
00 0010 1000
+25 °C
00 0110 0100
+50 °C
00 1100 1000
+75 °C
01 0010 1100
+100 °C
01 1001 0000
+105 °C
01 1010 0100
+125 °C
01 1111 0100
The measured results from the internal temperature sensor, external temperature sensor and the VDD pin are compared with the THIGH/VHIGH (greater than comparison)
and TLOW/VLOW (greater than or equal to comparison)
limits. An interrupt occurs if the measurement exceeds or
equals the limit registers. These limits are stored in onchip registers. Please note that the limit registers are 8 bits
long while the conversion results are 10 bits long. If the
limits are not masked out then any out-of-limit comparisons generate flags that are stored in Interrupt Status 1
Register (address = 00h) and Interrupt Status 2 Register
(address = 01h). One or more out-of limit results will
cause the INT/INT output to pull either high or low depending on the output polarity setting. It is good design
practice to mask out interrupts for channels that are of no
concern to the application.
Figure 13 shows the interrupt structure for the ADT7316/
17/18. It gives a block diagram representation of how the
various measurement channels affect the INT/INT pin.
ADT7316/7317/7318 REGISTERS
The ADT7316/17/18 contains registers that are used to
store the results of external and internal temperature measurements, VDD value measurements, high and low temperature and supply voltage limits, set output DAC
voltage levels, configure multipurpose pins and generally
control the device. A description of these registers follows.
The register map is divided into registers of 8-bits long.
Each register has it’s own individual address but some
consist of data that is linked with other registers. These
registers hold the 10-bit conversion results of measurements taken on the Temperature and VDD channels. For
example, the 8 MSBs of the VDD measurement are stored
in register address 06h while the 2 LSBs are stored in
register address 03h. The link involved between these
types of registers is that when the LSB register is read first
then the MSB registers associated with that LSB register
are locked to prevent any updates. To unlock these MSB
registers the user has only to read any one of them, which
will have the affect of unlocking all previously locked
MSB registers. So for the example given above if register
03h was read first then MSB registers 06h and 07h would
be locked to prevent any updates to them. If register 06h
was read then this register and register 07h would be subsequently unlocked.
1st READ
COMMAND
LSB
REGISTER
OUTPUT
DATA
LOCK ASSOCIATED
MSB REGISTERS
Figure 15. Phase 1 of 10-Bit Read
Temperature Conversion Formula:
1. Positive Temperature = ADC Code/4
2. Negative Temperature = (ADC Code* - 512)/4
*DB9 is removed from the ADC Code
–20–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
2nd READ
COMMAND
MSB
REGISTER
ADT7316/7317/7318
OUTPUT
DATA
22h
External Analog Temp Offset
D8h
23h
V DD V HIGH Limit
C7h
UNLOCK ASSOCIATED
MSB REGISTERS
24h
VDD V LOW Limit
62h
Figure 16. Phase 2 of 10-Bit Read
25h
Internal T HIGH Limit
64h
If an MSB register is read first, it’s corresponding LSB
register is not locked thus leaving the user with the option
of just reading back 8 bits (MSB) of a 10-bit conversion
result. Reading an MSB register first does not lock up
other MSB registers and likewise reading an LSB register
first does not lock up other LSB registers.
26h
Internal TLOW Limit
C9h
27h
External T HIGH
FFh
28h
External T LOW
00h
29h-4CH
RESERVED
Table 6. List of ADT7316/7317/7318 Registers
RD/WR
Name
Address
Power-on
4Dh
Device ID
01h/09h/05h
Default
4Eh
Manufacturer’s ID
41h
4Fh
Silicon Revision
00h
RESERVED
00h
SPI Lock Status
00h
RESERVED
00h
00h
Interrupt Status 1
00h
01h
Interrupt Status 2
00h
02h
RESERVED
00h
03h
Internal Temp & VDD LSBs
00h
04h
External Temp LSBs
00h
05h
RESERVED
00h
06h
VDD MSBs
00h
07h
Internal Temperature MSBs
00h
08h
External Temp MSBs
00h
Interrupt Status 1 Register (Read only) [Add. = 00h]
RESERVED
00h
10h
DAC A LSBs (ADT7316/17 only)
00h
This 8-bit read only register reflects the status of some of
the interrupts that can cause the INT/INT pin to go active. This register is reset by a read operation provided
that any out of limit event has been corrected. It is also
reset by a software reset.
11h
DAC A MSBs
00h
12h
DAC B LSBs (ADT7316/17 only)
00h
D7
D6
D5
D4
D3
D2
D1
D0
13h
DAC B MSBs
00h
N/A
N/A
N/A
0*
0*
0*
0*
0*
14h
DAC C LSBs (ADT7316/17 only)
00h
*Default settings at Power-up.
15h
DAC C MSBs
00h
16h
DAC D LSBs (ADT7316/17 only)
00h
17h
DAC D MSBs
00h
18h
Control CONFIG 1
00h
19h
Control CONFIG 2
00h
1Ah
Control CONFIG 3
00h
1Bh
DAC CONFIG
00h
1Ch
LDAC CONFIG
00h
1Dh
Interrupt Mask 1
00h
1Eh
Interrput Mask 2
00h
1Fh
Internal Temp Offset
00h
20h
External Temp Offset
00h
21h
Internal Analog Temp Offset
D8h
09h-0Fh
REV. Pr.O
50h-7Eh
7F
80-FF
Table 7. Interrupt Status 1 Register
Bit
Function
D0
1 when Internal Temp Value exceeds THIGH limit.
Any internal temperature reading greater than the
limit set will cause an out of limit event.
D1
1 when Internal Temp Value exceeds TLOW limit.
Any internal temperature reading less than or
equal to the limit set will cause an out of limit
event.
D2
1 when External Temp Value exceeds THIGH
limit. The default value for this limit register is
-1oC so any external temperature reading greater
than the limit set will cause an out of limit event.
D3
1 when External Temp Value exceeds TLOW limit.
The default value for this limit register is 0oC so
–21–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
any external temperature reading less than or equal
to the limit set will cause an out of limit event.
D4
Table 10.
D7
1 indicates a fault (open or short) for the external
temperature sensor.
External Temperature LSBs
D6
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
T1
LSB
N/A
N/A
N/A
N/A
N/A
N/A
0*
0*
*Default settings at Power-up.
Interrupt Status 2 Register (Read only) [Add. = 01h]
This 8-bit read only register reflects the status of the VDD
interrupt that can cause the INT/INT pin to go active.
This register is reset by a read operation provided that any
out of limit event has been corrected. It is also reset by a
software reset.
Bit
Function
D0
LSB of External Temperature Value
D1
B1 of External Temperature Value
Table 8. Interrupt Status 2 Register
D7
D6
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
0*
N/A
N/A
N/A
N/A
*Default settings at Power-up.
VDD VALUE REGISTER MSBS (Read only) [Add. = 06h]
This 8-bit read only register stores the supply voltage
value. The 8 MSBs of the 10-bit value are stored in this
register.
Table 11.
Bit
Function
D4
1 when VDD value is greater than corresponding
VHIGH limit.
1 when VDD is less than or equal to corresponding
VLOW limit.
VDD Value MSBs
D7
D6
D5
D4
D3
D2
D1
D0
V9
V8
V7
V6
V5
V4
V3
V2
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
INTERNAL TEMPERATURE VALUE/VDD VALUE
REGISTER LSBs (Read only) [Add. = 03h]
INTERNAL TEMPERATURE VALUE REGISTER
MSBS (Read only) [Add. = 07h]
This Internal Temperature Value and VDD Value Register
is a 8-bit read-only register. It stores the two LSBs of the
10-bit temperature reading from the internal temperature
sensor and also the two LSBs of the 10-bit supply voltage
reading.
This 8-bit read only register stores the Internal Temperature value from the internal temperature sensor in twos
complement format. The 8 MSBs of the 10-bit value are
stored in this register.
Table 12.
Table 9.
Internal Temp/VDD LSBs
D7
D6
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
N/A
V1
LSB
T1
LSB
N/A
N/A
N/A
N/A
0*
0*
0*
0*
Internal Temperature Value MSBs
D7
D6
D5
D4
D3
D2
D1
D0
T9
T8
T7
T6
T5
T4
T3
T2
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
*Default settings at Power-up.
Bit
Function
D0
LSB of Internal Temperature Value
D1
B1 of Internal Temperature Value
D2
LSB of VDD Value
D3
B1 of VDD Value
EXTERNAL TEMPERATURE VALUE REGISTER
LSBS (Read only) [Add. = 04h]
This External Temperature Value is a 8-bit read-only
register. It stores the two LSBs of the 10-bit temperature
reading from the external temperature sensor.
EXTERNAL TEMPERATURE VALUE REGISTER
MSBS (Read only) [Add. = 08h]
This 8-bit read only register stores the External Temperature value from the external temperature sensor in twos
complement format. The 8 MSBs of the 10-bit value are
stored in this register.
Table 13.
External Temperature Value MSBs
D7
D6
D5
D4
D3
D2
D1
D0
T9
T8
T7
T6
T5
T4
T3
T2
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
–22–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
*Default settings at Power-up.
DAC A REGISTER LSBS (Read/Write) [Add. = 10h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC A word respectively. The value in
this register is combined with the value in the DAC A
Register MSBs and converted to an analog voltage on the
VOUTA pin. On power-up the voltage output on the VOUTA
pin is 0 V.
Table 14.
DAC B REGISTER MSBS (Read/Write) [Add. = 13h]
This 8-bit read/write register contains the 8 MSBs of the
DAC B word. The value in this register is combined with
the value in the DAC B Register LSBs and converted to
an analog voltage on the VOUTB pin. On power-up the
voltage output on the VOUTB pin is 0 V.
DAC A (ADT7316) LSBs
Table 19.
D7
D6
D5
D4
D3
D2
D1
D0
B3
B2
B1
LSB
N/A
N/A
N/A
N/A
0*
0*
0*
0*
N/A
N/A
N/A
N/A
*Default settings at Power-up.
DAC B MSBs
D7
D6
D5
D4
D3
D2
D1
D0
MSB
B8
B7
B6
B5
B4
B3
B2
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
Table 15. DAC A (ADT7317) LSBs
DAC C REGISTER LSBS (Read/Write) [Add. = 14h]
D7
D6
D5
D4
D3
D2
D1
D0
B1
LSB
N/A
N/A
N/A
N/A
N/A
N/A
0*
0*
N/A
N/A
N/A
N/A
N/A
N/A
*Default settings at Power-up.
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC C word respectively. The value in
this register is combined with the value in the DAC C
Register MSBs and converted to an analog voltage on the
VOUTC pin. On power-up the voltage output on the VOUTC
pin is 0 V.
DAC A REGISTER MSBS (Read/Write) [Add. = 11h]
This 8-bit read/write register contains the 8 MSBs of the
DAC A word. The value in this register is combined with
the value in the DAC A Register LSBs and converted to
an analog voltage on the VOUTA pin. On power-up the
voltage output on the VOUTA pin is 0 V.
Table 16.
Table 20.
DAC C (ADT7316) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B3
B2
B1
LSB
N/A
N/A
N/A
N/A
0*
0*
0*
0*
N/A
N/A
N/A
N/A
*Default settings at Power-up.
DAC A MSBs
D7
D6
D5
D4
D3
D2
D1
D0
MSB
B8
B7
B6
B5
B4
B3
B2
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
B1
LSB
N/A
N/A
N/A
N/A
N/A
N/A
0*
0*
N/A
N/A
N/A
N/A
N/A
N/A
*Default settings at Power-up.
Table 21. DAC C (ADT7317) LSBs
*Default settings at Power-up.
DAC B REGISTER LSBS (Read/Write) [Add. = 12h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC B word respectively. The value in
this register is combined with the value in the DAC B
Register MSBs and converted to an analog voltage on the
VOUTB pin. On power-up the voltage output on the VOUTB
pin is 0 V.
Table 17.
This 8-bit read/write register contains the 8 MSBs of the
DAC C word. The value in this register is combined with
the value in the DAC C Register LSBs and converted to
an analog voltage on the VOUTC pin. On power-up the
voltage output on the VOUTC pin is 0 V.
DAC B (ADT7316) LSBs
D7
D6
D5
D4
D3
D2
D1
B3
B2
B1
LSB
N/A
N/A
0*
0*
0*
0*
N/A
N/A
Table 22.
DAC C MSBs
D0
D7
D6
D5
D4
D3
D2
D1
D0
N/A
N/A
MSB
B8
B7
B6
B5
B4
B3
B2
N/A
N/A
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
*Default settings at Power-up.
Table 18. DAC B (ADT7317) LSBs
DAC D REGISTER LSBS (Read/Write) [Add. = 16h]
D7
D6
D5
D4
D3
D2
D1
D0
B1
LSB
N/A
N/A
N/A
N/A
N/A
N/A
0*
0*
N/A
N/A
N/A
N/A
N/A
N/A
REV. Pr.O
DAC C REGISTER MSBS (Read/Write) [Add. = 15h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC D word respectively. The value in
this register is combined with the value in the DAC D
Register MSBs and converted to an analog voltage on the
–23–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
VOUTD pin. On power-up the voltage output on the
VOUTD pin is 0 V.
Table 23.
DAC D (ADT7316) LSBs
D7
D6
D5
D4
D3
D2
D1
B3
B2
B1
LSB
N/A
N/A
N/A
N/A
0*
0*
0*
0*
N/A
N/A
N/A
N/A
C6
Configures INT/INT output polarity.
0
Active low
1
Active High
C7
Power-down Bit. Setting this bit to 1 puts the
ADT7316/17/18 into standby mode. In this
mode both ADC and DACs are fully powered
down, but serial interface is still operational. To
power up the part again just write 0 to this bit.
D0
*Default settings at Power-up.
CONTROL CONFIGURATION 2 REGISTER (Read/
Write) [Add. = 19h]
Table 24. DAC D (ADT7317) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B1
LSB
N/A
N/A
N/A
N/A
N/A
N/A
0*
0*
N/A
N/A
N/A
N/A
N/A
N/A
*Default settings at Power-up.
DAC D REGISTER MSBS (Read/Write) [Add. = 17h]
This 8-bit read/write register contains the 8 MSBs of the
DAC D word. The value in this register is combined with
the value in the DAC D Register LSBs and converted to
an analog voltage on the VOUTD pin. On power-up the
voltage output on the VOUTD pin is 0 V.
Table 25.
DAC D MSBs
D7
D6
D5
D4
D3
D2
D1
D0
MSB
B8
B7
B6
B5
B4
B3
B2
0*
0*
0*
0*
0*
0*
0*
0*
This configuration register is an 8-bit read/write register
that is used to setup some of the operating modes of the
ADT7316/17/18.
Table 27.
D7
D6
D5
D4
D3
D2
D1
D0
C7
C6
C5
C4
C3
C2
C1
C0
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
Bit
Function
C1:0
In single channel mode these bits select between
VDD, the internal temperature sensor and the
external temperature sensor for conversion. Default is VDD.
00 = VDD
01 = Internal Temperature Sensor.
10 = External Temperature Sensor
11 - 11 = RESERVED
C2:C3
RESERVED
C4
Selects between single channel and Round Robin
conversion cycle. Default is Round Robin.
0 = Round Robin.
1 = Single Channel.
C5
Default condition is to average every measurement on all channels 16 times. This bit disables
this averaging. Channels affected are temperature and VDD.
0 = Enable averaging.
1 = Disable averaging.
C6
SMBus timeout on the serial clock puts a 25ms
limit on the pulse width of the clock. Ensures
that a fault on the master SCL does not lock up
the SDA line.
0 = Disable SMBus Timeout.
1 = Enable SMBus Timeout.
C7
Software Reset. Setting this bit to a 1 causes a
software reset. All registers and DAC outputs
will reset to their default settings.
*Default settings at Power-up.
CONTROL CONFIGURATION 1 REGISTER (Read/
Write) [Add. = 18h]
This configuration register is an 8-bit read/write register
that is used to setup some of the operating modes of the
ADT7316/17/18.
Table 26.
Control Configuration 1
D7
D6
D5
D4
D3
D2
D1
D0
PD
C6
C5
C4
C3
C2
C1
C0
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
Bit
Function
C0
This bit enables/disables conversions in Round
Robin and Single Channel mode. ADT7316/17/
18 powers up in Round Robin mode but monitoring is not initiated until this bit is set.
Default = 0.
0 = Stop monitoring.
1 = Start monitoring.
C1:4
RESERVED. Only write 0’s.
C5
0
1
Enable INT/INT Output
Disable INT/INT Output
Control Configuration 2
CONTROL CONFIGURATION 3 REGISTER (Read/
Write) [Add. = 1Ah]
This configuration register is an 8-bit read/write register
that is used to setup some of the operating modes of the
–24–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
ADT7316/17/18 and also indicates if the serial bus interface has been locked.
Table 28.
Function
D0
Selects the output range of DAC A.
0 = 0 V to VREF.
1 = 0 V to 2VREF.
D1
Selects the output range of DAC B.
0 = 0 V to VREF.
1 = 0 V to 2VREF.
D2
Selects the output range of DAC C.
0 = 0 V to VREF.
1 = 0 V to 2VREF.
D3
Selects the output range of DAC D.
0 = 0 V to VREF.
1 = 0 V to 2VREF.
D5:D4
00
Control Configuration 3
D7
D6
D5
D4
D3
D2
D1
D0
C7
C6
C5
C4
C3
C2
C1
C0
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
Bit
Function
C0
Selects between fast and normal ADC conversion speeds for all three monitoring channels.
0 = ADC clock at 1.4 KHz.
1 = ADC clock at 22.5 KHz.
C1
Bit
On the ADT7316 and ADT7317, this bit selects
between 8 bits and 10 bits DAC output resolution on the Thermal Voltage Output feature.
Default = 8 bits.
This bit has no affect on the ADT7318 output as
this part has only an 8-bit DAC. In the
ADT7318 case, write 0 to this bit.
0 = 8 bits resolution.
1 = 10 bits resolution.
C2
RESERVED. Only write 0.
C3
0 = LDAC pin controls updating of DAC outputs.
1 = DAC Configuration register and LDAC
Configuration register control updating of DAC
outputs.
C4
RESERVED. Only write 0.
C5
Setting this bit selects DAC A voltage output to
be proportional to the internal temperature measurement.
Setting this bit selects DAC B voltage output to
be proportional to the external temperature measurement.
C7
RESERVED. Only write 0.
This configuration register is an 8-bit read/write register
that is used to control the output ranges of all four DACs
and also to control the loading of the DAC registers if the
LDAC pin is disabled (bit C3 = 1, Control Configuration
3 register).
Table 29.
10
11
D6
Setting this bit allows the external VREF to bypass the reference buffer when supplying DACs
A and B.
D7
Setting this bit allows the external VREF to bypass the reference buffer when supplying DACs
C and D.
LDAC CONFIGURATION REGISTER (Write only)
[Add. = 1Ch]
C6
DAC CONFIGURATION REGISTER (Read/Write)
[Add. = 1Bh]
01
MSB write to any DAC register generates
LDAC command which updates that
DAC only.
MSB write to DAC B or DAC D register
generates LDAC command which updates DACs A, B or DACs C, D
respectivily.
MSB write to DAC D register generates
LDAC command which updates all 4
DACs.
LDAC command generated from LDAC
register.
This configuration register is an 8-bit write register that is
used to control the updating of the quad DAC outputs if
the LDAC pin is disabled and Bits D4 and D5 of DAC
Configuration register are both set to 1. Also selects either
the internal or external VREF for all four DACs. Bits D0D3 in this register are self clearing i.e. reading back from
this register will always give 0’s for these bits.
Table 30.
LDAC Configuration
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
DAC Configuration
D7
D6
D5
D4
D3
D2
D1
D0
Bit
Function
D7
D6
D5
D4
D3
D2
D1
D0
D0
0*
0*
0*
0*
0*
0*
0*
0*
Writing a 1 to this bit will generate the LDAC
command to update DAC A output only.
D1
Writing a 1 to this bit will generate the LDAC
command to update DAC B output only.
*Default settings at Power-up.
REV. Pr.O
–25–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
D2
Writing a 1 to this bit will generate the LDAC
command to update DAC C output only.
Bit
Function
D3
Writing a 1 to this bit will generate the LDAC
command to update DAC D output only.
D0:D3
RESERVED. Only write 0’s.
D4
0 = Enable VDD interrupts.
1 = Disable VDD interrupts.
D5:D7
RESERVED. Only write 0’s.
D4
D5
D6:D7
Selects either internal VREF or external VREFAB
for DACs A and B.
0 = External VREF
1 = Internal VREF
INTERNAL TEMPERATURE OFFSET REGISTER
(Read/Write) [Add. = 1Fh]
Selects either internal VREF or external VREFCD
for DACs C and D.
0 = External VREF
1 = Internal VREF
RESERVED. Only write 0’s.
INTERRUPT MASK 1 REGISTER (Read/Write) [Add. =
1Dh]
This mask register is an 8-bit read/write register that can
be used to mask out any interrupts that can cause the INT/
INT pin to go active.
Table 31.
This register contains the Offset Value for the Internal
Temperature Channel. A 2's complement number can be
written to this register which is then 'added' to the measured result before it is stored or compared to limits. In
this way a sort of one-point calibration can be done
whereby the whole transfer function of the channel can be
moved up or down. From a software point of view this
may be a very simple method to vary the characteristics of
the measurement channel if the thermal characteristics
change. As it is an 8-bit register the temperature resolution is 1oC.
Interrupt Mask 1
Table 33.
Internal Temperature Offset
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
*Default settings at Power-up.
Bit
Function
EXTERNAL TEMPERATURE OFFSET REGISTER
(Read/Write) [Add. = 20h]
D0
0 = Enable internal THIGH interrupt.
1 = Disable internal THIGH interrupt.
D1
0 = Enable internal TLOW interrupt.
1 = Disable internal TLOW interrupt.
D2
0 = Enable external THIGH interrupt.
1 = Disable external THIGH interrupt.
D3
0 = Enable external Tlow interrupt.
1 = Disable external Tlow interrupt.
D4
0 = Enable external temperature fault interrupt.
1 = Disable external temperature fault interrupt.
This register contains the Offset Value for the Internal
Temperature Channel. A 2's complement number can be
written to this register which is then 'added' to the measured result before it is stored or compared to limits. In
this way a sort of one-point calibration can be done
whereby the whole transfer function of the channel can be
moved up or down. From a software point of view this
may be a very simple method to vary the characteristics of
the measurement channel if the thermal characteristics
change. As it is an 8-bit register the temperature resolution is 1oC.
D5:D7
RESERVED. Only write 0’s.
Table 34.
INTERRUPT MASK 2 REGISTER (Read/Write) [Add. =
1Eh]
This mask register is an 8-bit read/write register that can
be used to mask out any interrupts that can cause the INT/
INT pin to go active.
Table 32.
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
INTERNAL ANALOG TEMPERATURE OFFSET
REGISTER (Read/Write) [Add. = 21h]
Interrupt Mask 2
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
External Temperature Offset
This register contains the Offset Value for the Internal
Thermal Voltage output. A 2's complement number can
be written to this register which is then 'added' to the measured result before it is converted by DAC A. Varying the
value in this register has the affect of varying the temperature span. For example, the output voltage can represent a
temperature span of -128oC to +127oC or even 0oC to
–26–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
+127oC. In essence this register changes the position of
0V on the temperature scale. Anything other than -128oC
to +127oC will produce an upper deadband on the DAC A
output. As it is an 8-bit register the temperature resolution
is 1oC. Default value is -40oC.
Table 35.
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
1*
1*
0*
1*
1*
0*
0*
0*
D6
D5
D4
D3
D2
D1
D0
0*
1*
1*
0*
0*
0*
1*
0*
*Default settings at Power-up.
INTERNAL THIGH LIMIT REGISTER (Read/Write)
[Add. = 25h]
Internal Analog Temperature Offset
D7
D7
This limit register is an 8-bit read/write register which
stores the 2’s complement of the internal temperature
upper limit that will cause an interrupt and activate the
INT/INT output (if enabled). For this to happen the
measured Internal Temperature Value has to be greater
than the value in this register. As it is an 8-bit register the
temperature resolution is 1oC. Default value is +100oC.
*Default settings at Power-up.
EXTERNAL ANALOG TEMPERATURE OFFSET
REGISTER (Read/Write)[Add. = 22h]
Table 39.
This register contains the Offset Value for the External
Thermal Voltage output. A 2's complement number can
be written to this register which is then 'added' to the measured result before it is converted by DAC B. Varying the
value in this register has the affect of varying the temperature span. For example, the output voltage can represent a
temperature span of -128oC to +127oC or even 0oC to
+127oC. In essence this register changes the position of
0V on the temperature scale. Anything other than -128oC
to +127oC will produce an upper deadband on the DAC B
output. As it is an 8-bit register the temperature resolution
is 1oC. Default value is -40oC.
Table 36.
External Analog Temperature Offset
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
1*
1*
0*
1*
1*
0*
0*
0*
Internal THIGH Limit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
1*
1*
0*
0*
1*
0*
0*
*Default settings at Power-up.
INTERNAL TLOW LIMIT REGISTER (Read/Write) [Add.
26h]
This limit register is an 8-bit read/write register which
stores the 2’s complement of the internal temperature
lower limit that will cause an interrupt and activate the
INT/INT output (if enabled). For this to happen the
measured Internal Temperature Value has to be more
negative than or equal to the value in this register. As it is
an 8-bit register the temperature resolution is 1oC. Default value is -55oC.
Table 40.
Internal TLOW Limit
*Default settings at Power-up.
D7
D6
D5
D4
D3
D2
D1
D0
VDD VHIGH LIMIT REGISTER (Read/Write) [Add. = 23h]
D7
D6
D5
D4
D3
D2
D1
D0
1*
1*
0*
0*
1*
0*
0*
1*
This limit register is an 8-bit read/write register which
stores the VDD upper limit that will cause an interrupt and
activate the INT/INT output (if enabled). For this to
happen the measured VDD value has to be greater than the
value in this register. Default value is 5.46 V.
Table 37.
VDD VHIGH Limit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
1*
1*
0*
0*
0*
1*
1*
1*
*Default settings at Power-up.
*Default settings at Power-up.
EXTERNAL THIGH LIMIT REGISTER (Read/Write)
[Add. = 27h]
This limit register is an 8-bit read/write register which
stores the 2’s complement of the external temperature
upper limit that will cause an interrupt and activate the
INT/INT output (if enabled). For this to happen the
measured External Temperature Value has to be greater
than the value in this register. As it is an 8-bit register the
temperature resolution is 1oC. Default value = -1oC.
Table 41.
VDD VLOW LIMIT REGISTER (Read/Write) [Add. = 24h]
This limit register is an 8-bit read/write register which
stores the VDD lower limit that will cause an interrupt and
activate the INT/INT output (if enabled). For this to
happen the measured VDD value has to be less than or
equal to the value in this register. Default value is 2.7 V.
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
1*
1*
1*
1*
1*
1*
1*
1*
*Default settings at Power-up.
Table 38. VDD VHIGH Limit
D7
D6
REV. Pr.O
D5
D4
D3
D2
D1
External THIGH Limit
D0
–27–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
EXTERNAL TLOW LIMIT REGISTER (Read/Write)
[Add. = 28h]
SPI LOCK STATUS REGISTER (Read only) [Add. =
7Fh]
This limit register is an 8-bit read/write register which
stores the 2’s complement of the external temperature
lower limit that will cause an interrupt and activate the
INT/INT output (if enabled). For this to happen the
measured External Temperature Value has to be more
negative than or equal to the value in this register. As it is
an 8-bit register the temperature resolution is 1oC. Default value = 0oC.
Bit
the
will
0
1
Table 42.
ADT7316/7317/7318 SERIAL INTERFACE
There are two serial interfaces that can be used on this
part, I2C and SPI. The device will power up with the serial interface in I2C mode but it is not locked into this
mode. To stay in I2C mode it is recommended that the
user ties the CS line to either VCC or GND. It is not possible to lock the I2C mode but it is possible to select and
lock the SPI mode.
External TLOW Limit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
D0 (LSB) of this read only register indicates whether
SPI interface is locked or not. Writing to this register
cause the device to malfunction. Default value is 00h.
= I2C interface
= SPI interface selected and locked.
To select and lock the interface into the SPI mode, a
number of pulses must be sent down the CS (pin 4) line.
The following section describes how this is done.
*Default settings at Power-up.
DEVICE ID REGISTER (READ ONLY) [ADD. = 4DH]
Once the SPI communication protocol has been locked in,
it cannot be unlocked while the device is still powered up.
Bit D0 of SPI Lock Status register (address = 7Fh) is set
to 1 when a successful SPI interface lock has been
acomplished. To reset the serial interface the user must
power down the part and power up again. A software reset
does not reset the serial interface.
This 8-bit read only register indicates which part the device is in the model range. ADT7316 = 01h, ADT7317 =
09h and ADT7318 = 05h.
MANUFACTURER’S ID REGISTER (Read only) [Add.
= 4Eh]
This register contains the manufacturers identification
number. ADI’s is 41h.
SERIAL INTERFACE SELECTION
SILICON REVISION REGISTER (Read only) [Add. =
4Fh]
The CS line controls the selection between I2C and SPI.
Figure 17 shows the selection process necessary to lock
the SPI interface mode.
This register is divided into the four lsbs representing the
Stepping and the four msbs representing the Version. The
Stepping contains the manufacturers code for minor revisions or steppings to the silicon. The Version is the
ADT7316/17/18 version number. The ADT7316/17/18’s
version number is 0100b (4h).
If the user wants to communicate to the ADT7316/17/18
using the SPI protocol, send three pulses down the CS
line as shown in figure 17(a) and 17(b). On the third rising edge (marked as C in figure 17) the part selects and
locks the SPI interface. The user is now limited to communicating to the device using the SPI protocol.
CS
(Start High)
A
B
C
SPI LOCKED ON
3RD RISING EDGE
SPI FRAMING
EDGE
Figure 17(a). Serial Interface - Selecting and Locking SPI Protocol
CS
(Start Low)
A
B
C
SPI LOCKED ON
3RD RISING EDGE
SPI FRAMING
EDGE
Figure 17(b). Serial Interface - Selecting and Locking SPI Protocol
–28–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
As per most SPI standards, the CS line must be low during every SPI communication to the ADT7316/17/18 and
high all other times. Typical examples of how to connect
up the dual interface as I2C or SPI is shown in figures
18(a) and 18(b).
CS
DIN
SPI FRAMING
EDGE
SCLK
VDD
ADT7316/17/18
LOCK AND
SELECT SPI
ADT7316/17/18
VDD
DOUT
CS
SDA
Figure 18(b). Typical SPI Interface Connection
SCL
2
I C ADDRESS = 1001 000
The following sections describe in detail how to use the
I2C and SPI protocols associated with the ADT7316/17/
18.
ADD
I2C SERIAL INTERFACE
Figure 18(a). Typical I2C Interface Connection
Like all I2C-compatible devices, the ADT7316/7317/7318
has an 7-bit serial address. The four MSBs of this address
for the ADT7316/7317/7318 are set to 1001. The three
LSBs are set by pin 11, ADD. The ADD pin can be configured three ways to give three different address options;
low, floating and high. Setting the ADD pin low gives a
serial bus address of 1001 000, leaving it floating gives the
address 1001 010 and setting it high gives the address
1001 011.
1
9
1
9
SCL
1
SDA
0
0
1
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
ACK. BY
ADT7316/17/18
START BY
MASTER
P0
ACK. BY
ADT7316/17/18
FR AME 1
SERIAL BUS ADDRESS B YTE
STOP BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 19. I2C - Writing to the Address Pointer Register to select a register for a subsequent Read operation
1
9
1
9
SCL
SDA
1
0
0
1
A2
A1
R/W
A0
P7
P6
P5
P4
P3
P2
P1
ACK. BY
ADT7316/17/18
START BY
MASTER
P0
ACK. BY
ADT7316/17/18
FRAME 1
SERIAL BUS ADDRESS B YTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7316/17/18
STOP BY
MASTER
FRAME 3
DATA BYTE
Figure 20. I2C - Writing to the Address Pointer Register followed by a single byte of data to the selected register
REV. Pr.O
–29–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
SCL remains high. This indicates that an address/data
stream will follow. All slave peripherals connected to
the serial bus respond to the START condition, and
shift in the next 8 bits, consisting of a 7-bit address
(MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be
written to or read from the slave device.
There is a programmable SMBus timeout. When this is
enabled the SMBus will timeout after 25 ms of no activity.
To enable it, set Bit 6 of Control Configuration 2 register. The power-up default is with the SMBus timeout
disabled.
The ADT7316/17/18 supports SMBus Packet Error
Checking (PEC) and it’s use is optional. It is triggered by
supplying the extra clocks for the PEC byte. The PEC is
calculated using CRC-8. The Frame Clock Sequence
(FCS) conforms to CRC-8 by the polynomial :
The peripheral whose address corresponds to the transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit. All other devices on the
bus now remain idle whilst the selected device waits for
data to be read from or written to it. If the R/W bit is a
0 then the master will write to the slave device. If the
R/W bit is a 1 the master will read from the slave device.
C(x) = x8 + x2 + x1 + 1
Consult SMBus specification (www.smbus.org) for more
information.
The serial bus protocol operates as follows:
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the receiver of data. Transitions on the data line
must occur during the low period of the clock signal
1. The master initiates data transfer by establishing a
START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
1
9
1
9
SCL
0
1
SDA
0
1
A2
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
ACK. BY
ADT7316/17/18
START BY
MASTER
D0
NO ACK. BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
STOP BY
MASTER
FRA ME 2
SINGL E D ATA BYTE FROM ADT7316/17/18
Figure 21. I2C - Reading a single byte of data from a selected register
CS
1
8
8
1
SCLK
DIN
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
START
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED)
1
8
SCLK (CONTINUED)
DIN (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
STOP
DATA BYTE
Figure 22. SPI - Writing to the Address Pointer Register followed by a single byte of data to the selected register
–30–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
and remain stable during the high period, as a low to
high transition when the clock is high may be interpreted as a STOP signal.
address. Any subsequent changes on this pin will have no
affect on the I2C serial bus address.
WRITING TO THE ADT7316/7317/7318
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse
to assert a STOP condition. In READ mode, the master device will pull the data line high during the low
period before the 9th clock pulse. This is known as No
Acknowledge. The master will then take the data line
low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a STOP
condition.
Depending on the register being written to, there are two
different writes for the ADT7316/7317/7318. It is not
possible to do a block write to this part i.e. no I2C autoincrement.
Writing to the Address Pointer Register for a subsequent
read.
In order to read data from a particular register, the Address Pointer Register must contain the address of that
register. If it does not, the correct address must be written
to the Address Pointer Register by performing a singlebyte write operation, as shown in Figure 19. The write
operation consists of the serial bus address followed by the
address pointer byte. No data is written to any of the data
registers. A read operation is then performed to read the
register.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix
read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.
The I2C address set up by the ADD pin is not latched by
the device until after this address has been sent twice. On
the 8th SCL cycle of the second valid communication, the
serial bus address is latched in. This is the SCL cycle
directly after the device has seen it’s own I2C serial bus
Writing data to a Register.
All registers are 8-bit registers so only one byte of data
can be written to each register. Writing a single byte of
data to one of these Read/Write registers consists of the
serial bus address, the data register address written to the
Address Pointer Register, followed by the data byte written
CS
1
8
8
1
SCLK
DIN
D6
D7
D5
D4
D3
D2
D1
D7
D0
D6
D5
D4
D3
D2
D1
D0
STOP
START
WRITE COMMAND
REGISTER ADDRESS
Figure 23. SPI - Writing to the Address Pointer Register to select a register for a subsequent read operation
CS
1
8
8
1
SCLK
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
STOP
START
READ COMMAND
DATA BYTE 1
Figure 24. SPI - Reading a single byte of data from a selected register
REV. Pr.O
–31–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
to the selected data register. This is illustrated in Figure
20. To write to a different register, another START or
repeated START is required. If more than one byte of
data is sent in one communication operation, the addressed register will be repeatedly loaded until the last
data byte has been sent.
SPI SERIAL INTERFACE
The SPI serial interface of the ADT7316/7317/7318 consists of four wires, CS, SCLK, DIN and DOUT. The CS
is used to select the device when more than one device is
connected to the serial clock and data lines. The CS is
also used to distinguish between any two separate serial
communications, reference Figure 26 for graphical explanation. The SCLK is used to clock data in and out of the
part. The DIN line is used to write to the registers and the
DOUT line is used to read data back from the registers.
READING DATA FROM THE ADT7316/7317/7318
Reading data from the ADT7516/7517/7518 is done in a
one byte operation. Reading back the contents of a register
is shown in Figure 21. The register address previously
having been set up by a single byte write operation to the
Address Pointer Register. If you want to read from another
register then you will have to write to the Address Pointer
Register again to set up the relevant register address. Thus
block reads are not possible i.e. no I2C auto-increment.
The part operates in a slave mode and requires an externally applied serial clock to the SCLK input. The serial
interface is designed to allow the part to be interfaced to
systems that provide a serial clock that is synchronized to
the serial data.
There are two types of serial operations, a read and a
write. Command words are used to distinguish between a
read and a write operation. These command words are
CS
1
8
8
1
SCLK
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
START
DATA BYTE 1
READ COMMAND
CS (CONTINUED)
1
8
SCLK (CONTINUED)
DIN (CONTINUED)
DOUT (CONTINUED)
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
STOP
DATA BYTE 2
Figure 25. SPI - Reading two bytes of data from two sequential registers
CS
SPI
READ OPERATION
WRITE OPERATION
Figure 26. SPI - Correct use of CS during SPI communication
–32–
REV. Pr.O
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
ADT7316/7317/7318
The INT/INT output becomes active when either the
Internal Temperature Value, the External Temperature
Value or the VDD Value exceed the values in their corresponding THIGH/V HIGH or TLOW/V LOW Registers. The
INT/INT output goes inactive again when a conversion
result indicates that all measurement channels are within
their trip limits. The two Interrupt Status registers show
which event caused the INT/INT pin to go active.
given in Table 43. Address auto-increment is possible in
SPI mode
Table 43. SPI COMMAND WORDS
WRITE
READ
90h (1001 0000)
91h (1001 0001)
Write Operation
Figures 22 and 23 show the timing diagrams for a write
operation to the ADT7316/7317/7318. Data is clocked
into the registers on the rising edge of SCLK. When the
CS line is high the DIN and DOUT lines are in threestate mode. Only when the CS goes from a high to a low
does the part accept any data on the DIN line. In SPI
mode the Address Pointer Register is capable of autoincrement to the next register in the register map without
having to load the Address Pointer register each time. In
Figure 22 the register address portion of the diagram
gives the first register that will be written to. Subsequent
data bytes will be written into sequential writable registers.
Thus after each data byte has been written into a register,
the Address Pointer Register auto increments it’s value to
the next available register. The Address Pointer Register
will auto-increment from 00h to 3Fh and will loop back
to start all over again at 00h when it reaches 3Fh.
The INT/INT output requires an external pull-up resistor. This can be connected to a voltage different from VDD
provided the maximum voltage rating of the INT/INT
output pin is not exceeded. The value of the pull-up resistor depends on the application, but should be large
enough to avoid excessive sink currents at the INT/INT
output, which can heat the chip and affect the temperature
reading.
Read Operation
Figures 24 and 25 show the timing diagrams necessary to
accomplish correct read operations. To read back from a
register you first have to write to the Address Pointer Register with the address of the register you wish to read
from. This operation is shown in Figure 23. Figure 24
shows the procedure for reading back a single byte of data.
The read command is first sent to the part during the first
8 clock cycles, during the following 8 clock cycles the
data contained in the register selected by the Address
Pointer register is outputted onto the DOUT line. Data is
outputted onto the DOUT line on the falling edge of
SCLK. Figure 25 shows the procedure when reading data
from two sequential registers. Multiple data reads are
possible in SPI interface mode as the Address Pointer
Register is auto-incremental. The Address Pointer Register will auto-increment from 00h to 3Fh and will loop
back to start all over again at 00h when it reaches 3Fh.
SMBUS/SPI INT/INT
The ADT7316/17/18 INT/INT output is an interrupt line
that signals an over/under-limit event on any of the measurement channels if the interrupt on that event has not
been disabled. The ADT7316/17/18 is a slave only device
and uses the SMBus/SPI INT/INT as it’s only means to
signal other devices that an event has occurred.
The INT/INT pin has an open-drain configuration which
allows the outputs of several devices to be wired-AND
together when the INT/INT pin is active low. Use C6 of
the Control Configuration 1 Register to set the active
polarity of the INT/INT output. The power-up default is
active low. The INT/INT output can be disabled or enabled by setting C5 of Control Configuration 1 Register
to a 1 or 0 respectively.
REV. Pr.O
–33–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Preliminary Technical Data
Outline Dimensions
(Dimensions shown in inches and mm )
16-Lead QSOP Package
( RQ-16 )
0.19 7 (5.00)
0.18 9 (4.80)
16
9
0.157 (3.99)
0.24 4 (6.20)
0.150 (3.81)
0.22 8 (5.79)
1
8
P IN 1
0.069 (1.75)
0 .059 (1.50 )
MAX
0.010 (0.25)
0.004 (0.10)
0.053 (1.35)
0.025
(0.64)
BSC
0.012 (0.30 )
0.008 (0.20 )
SEATING
PLANE
–34–
0.010 (0.20)
8o
o
0
0.007 (0.18)
REV. Pr.O