14BIT 10MSPS ADC adc1276x GENERAL DESCRIPTION FEATURES The adc1276x is a CMOS 14bit analog-to-digital Resolution : 14bit - Maximum Conversion Rate : 10MHz - Package Type : 48TSSOP - Power Supply : 3.3V - Power Consumption : 120mW (typical) - Reference Voltage : Internal reference or 2V, 1V (dual reference) - Input Range : 0.5V ~ 2.5V (2.0VP-P) - Differential Linearity Error : ±0.7 LSB - Integral Linearity Error : ±1.5 LSB - Signal to Noise & Distortion Ratio : 72dB - Total Harmonic Distortion : 80dB - Out of Range Indicator - Digital Output : CMOS Level - Operating Temperature Range : 0ºC ~ 70ºC converter (ADC). into 14bit binary It converts the analog input signal digital codes at a maximum sampling rate of 10MHz. The device is a monolithic ADC high-performance, sample-and-hold and current reference and voltage structure allows both differential input. with an on-chip, Amplifier (SHA) reference. The and single-ended TYPICAL APPLICATIONS CCD Imaging (Copiers, Scanners, Cameras) Medical Instruments Digital Communication Systems uADSL System - FUNCTIONAL BLOCK DIAGRAM Analog Input Reference Output SHA MDAC 1 MDAC 2 MDAC 3 FLASH 1 FLASH 2 FLASH 3 5 4 3 FLASH 4 3 Voltage Reference CLOCK GEN. DIGITAL LOGIC 14 Clock Ver 1.0 (April 2000) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD Digital Output ORI adc1276x 14BIT 10MSPS ADC CORE PIN DESCRIPTION I/O PAD PIN DESCRIPTION NAME I/O TYPE REFTOP AB phiar10_abb Reference Top Output/Force (2.0V) REFBOT AB phiar10_abb Reference Bottom Output/Force (1.0V) BGR AB phiar10_abb BGR output (1.23V) CML AB phiar10_abb Internal Bias CML1 AB phiar10_abb Internal Bias AVDD33A AVBB33A AVSS33A AP AG AG AINT AI vdd3t_abb Analog Power (3.3V) vbb3_abb Analog Sub Bias vss3t_abb Analog Ground phiar10_abb Analog Input + (Input Range : 1.0V ~ 2.0V) AINC AI phiar10_abb Analog Input (Input Range : 1.0V ~ 2.0V) ITEST AB phia_abb open=use internal bias point STBY DI phicc_abb VDD=power saving (standby), GND=normal CKIN D[13:0] ORI AVBB33D AVSS33D AVDD33D DI DO DO DG DG DP phicc_abb phot4_abb phot4_abb vbb3_abb vss3t_abb vdd3t_abb Sampling Clock Input Digital Output Out of Range Indicator Digital Sub Bias Digital GND Digital Power (3.3V) I/O TYPE ABBR. -AI : Analog Input -DI : Digital Input -AO : Analog Output -DO : Analog Output -AP -AG -DP -DG : : : : Analog Power Analog Ground Digital Power Digital Ground -AB : Analog Bidirection -DB : Digital Bidirection AVBB33D AVSS33D AVDD33D AVBB33A AVSS33A AVDD33A AINT AINC adc1276x REFTOP [MSB:LSB] DO[13:0] ORI REFBOT BGR CML CML1 ITEST STBY CKIN SEC ASIC 2/11 ANALOG adc1276x 14BIT 10MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Supply Voltage Value VDD Unit 4.5 V Analog Input Voltage AINT/AINC VSS to VDD V Digital Input Voltage CLK VSS to VDD V Storage Temperature Range Tstg -40 to 125 ºC Operating Temperature Range Topr 0 to 70 ºC NOTES 1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit 3.15 3.3 3.45 V 0.5 - 2.5 AVDD33A Supply Voltage AVDD33D AVDD33R Analog Input Voltage Operating Temperature AINT AINC Toper 1.5 0 - 70 V ºC NOTES It is strongly recommended that all the supply pins (AVDD33A, AVDD33D, AVDD33R) be powered from the same source to avoid power latch-up. SEC ASIC 3/11 ANALOG adc1276x 14BIT 10MSPS ADC DC ELECTRICAL CHARACTERISTICS Characteristics Differential Nonlinearity Integral Nonlinearity Offset Voltage Symbol Min Typ Max Unit Test Condition Internal Voltage Reference DNL ±0.7 - ±1 LSB REFTOP=2V REFBOT=1V Internal Voltage Reference ±1.5 - INL - LSB REFTOP=2V REFBOT=1V OFF - 10 - mV REFTOP=2V REFBOT=1V (Converter Specifications : AVDD33A=AVDD33D=AVDD33R=3.3V, AVSS33A=AVSS33D=AVSS33R=0V, Toper=25°C, REFTOP=2V, REFBOT=1V unless otherwise specified) AC ELECTRICAL CHARACTERISTICS Characteristics Maximum Conversion Rate Dynamic Supply Current Signal-to-Noise & Distortion Ratio Total Harmonic Distortion Symbol Min Typ fc - IVDD Max Unit Test Condition 10 MHz AIN=AINT-AINC - 36 mA SNDR - 72 - dB THD - 80 - dB fc=10MHz (without system load) AIN=1MHz, Differential Input AIN=1MHz, Differential Input (Conversion Specifications : AVDD33A=AVDD33D=AVDD33R=3.3V, AVSS33A=AVSS33D=AVSS33R=0V, Toper=25°C, REFTOP=2V, REFBOT=1V unless otherwise specified) SEC ASIC 4/11 ANALOG adc1276x 14BIT 10MSPS ADC I/O CHART Index AINT Input (V) AINC Input (v) Digital Output 0 0.5000 ~ 1.50012 1.5 00 0000 0000 0000 1 0.50012 ~ 1.50024 1.5 00 0000 0000 0001 2 0.5024 ~ 1.50037 1.5 00 0000 0000 0010 ~ ~ 8197 1.49988 ~ 1.5000 1.5 01 1111 1111 1111 8192 1.50000 ~ 1.50012 1.5 10 0000 0000 0000 8193 1.50012 ~ 1.50024 1.5 10 0000 0000 0001 ~ ~ 16381 2.49963 ~ 2.49976 1.5 11 1111 1111 1101 16382 2.49976 ~ 2.49988 1.5 11 1111 1111 1110 16383 2.49988 ~ 2.5000 1.5 11 1111 1111 1111 ~ 1LSB=0.122mV REFTOP=2.0V REFBOT=1.0V ~ TIMING DIAGRAM A1 A2 AINT A5 Input Sampling Period CKIN DO[13:0] D1 SEC ASIC D2 D3 5/11 D4 D5 ANALOG adc1276x 14BIT 10MSPS ADC FUNCTIONAL DESCRIPTION 1. The adc1276x is a CMOS four step pipelined Analog-to-Digital Converter. It contains 5-bit flash A/D Converters, 4bit, two 3bit flash A/D converters and three multiplying D/A Convertors. The N-bit flash ADC is composed of 2N-1 latched comparators, and multiplying DAC is composed of 2*(2N+1) capacitors and two fully-differential amplifiers. 2. The adc1276x operates as follows. During the first "L" cycle of external clock the analog input data is sampled, and the input is held from the rising edge of the external clock, which is fed to the first 5-bit flash ADC, and the first multiplying DAC. Multiplying DAC reconstructs a voltage corresponding to the first 5-bit ADC's output, and finally amplifies a residue voltage by 24. The second and third flash ADC, and MDAC are worked as same manner. Finally amplified residue voltage at the third multiplying DAC is fed to the last 3-bit flash ADC decides final 3-bit digital digital code. 3. adc1276x has the error correction scheme, which handles the output from mismatch in the first, second, third and fourth flash ADC. MAIN BLOCK DESCRIPTION 1. SHA designed that open-loop dc gain is higher than 70dB, phase margin is higher than 60 degrees. Its input block is designed to be the rail-to-rail architecture using complementary different pair. 2. FLASH The 5-bit flash converters compare analog signal (SAH output) with reference voltage, and that results transfer to MDAC and digital correction logic block. It is realized fully differential comparators of 31EA. Considering self-offset, dynamic feed through error, it should distinguish 40mV at least. First, the comparators charge the reference voltage at the sampling capacitors before transferred SHA output.That operation is performed on the phase of Q2, and discharging on the phase of Q1. That is, the comparators compare relative different values dual input voltage with dual reference voltage. Its output during Q1 operation is stored at the pre-latch block by Q1P. 3. MDAC MDAC is the most important block at this ADC and it decides the characteristics. MDAC is consist of two stage op amp, selection logic and capacitor array (c_array). c_array's compositions are the capacitors to charge the analog input and and the reference voltage, switches to control the path. Selection logic controls the c_array internal switches . If Q1 is high, selection's output are all low, the switches of tsw1 are off, the switches of tsw2 are all on. Therefore the capacitors of c_array can charge analog input values held at SHA. SHA (Sample-and-Hold Amplifier) is the circuit that samples the analog input signal and hold that value until next sample-time. It is good as small as its different value between analog input signal and output signal. SHA amp gain is higher than 70dB at 10MHz conversion rate, its settling-time must be shorten than 38ns with less than 1/2 LSB error voltage at 14bit resolution. This SHA is consist of fully differential op amp, switching tr. and sampling capacitor. The sampling clock is non-overlapping clock (Q1, Q2) and sampling capacitor value is about 4pF. SHA uses independent bias to protect interruption of any other circuit. SHA amp is SEC ASIC 6/11 ANALOG adc1276x 14BIT 10MSPS ADC CORE EVALUATION GUIDE 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. If User want the specific analog input range, the reference voltages may be forced. AVBB33D AVSS33D AVDD33D AVBB33A AVSS33A AVDD33A AINT AINC DO[13:0] [MSB:LSB] adc1276x ORI REFTOP REFBOT BGR CML CML1 ITEST STBY CKIN D[13:0] D[13:0] Digital Mux HOST DSP CORE D[13:0] Bidirectional PAD (ADC Function Test & externally forced Digital Input) SEC ASIC 7/11 ANALOG adc1276x 14BIT 10MSPS ADC PACKAGE CONFIGURATION NOTES 1. NC denotes "No Connection". 10u 0.1u 10u 0.1u 10u 0.1u 10u 0.1u 10u 0.1u 10u 10u 0.1u 0.1u Analog Digital II 10u 0.1u Digital I 1 BGR AVDD33D 48 2 REFTOP AVDD33D 47 3 REFBOT AVSS33D 46 4 CML AVSS33D 45 5 CML1 AVBB33D 44 6 AVDD33A NC 43 7 AVDD33A CKIN 42 8 AVBB33A NC 41 9 AVSS33A DO[13] 40 10 AVSS33A DO[12] 39 11 AINT DO[11] 38 12 NC 13 AINC DO[9] 36 14 NC DO[8] 35 15 NC DO[7] 34 16 ITEST DO[6] 33 17 STBY DO[5] 32 18 AVDD33R DO[4] 31 19 AVSS33R DO[3] 30 20 NC DO[2] 29 21 NC DO[1] 28 22 NC DO[0] 27 23 TRIST 24 RP adc1276x 0.1u 10u 50ohm DO[10] 37 ORI 26 Index Resistor RN 25 :25Kohm SEC ASIC 8/11 ANALOG adc1276x 14BIT 10MSPS ADC PACKAGE PIN DESCRIPTION I/O No. NAME 1 BGR AB Reference Voltage Output 2 REFTOP AB Reference Top Output/Force 3 REFBOT AB Reference bottom Output/Force 4 CML AB 5 CML1 6, 7 AVDD33A 8 AVBB33A 9, 10 AVSS33A TYPE PIN DESCRIPTION CONFIGURATION BGR 1 48 AVDD33D Internal Bias REFTOP 2 47 AVDD33D AB Internal Bias REFBOT 3 46 AVSS33D AP AG AG Analog Power (3.3V) Analog Sub Bias Analog Ground CML 4 45 AVSS33D CML1 5 44 AVBB33D AVDD33A 6 43 NC AVDD33A 7 42 CKIN AVBB33A 8 41 NC AVSS33A 9 40 DO[13] AVSS33A 10 39 DO[12] AINT 11 38 DO[11] NC 12 37 DO[10] AINC 13 36 DO[9] NC 14 35 DO[8] NC 15 34 DO[7] ITEST 16 33 DO[6] STBY 17 32 DO[5] AVDD33R 18 31 DO[4] AVSS33R 19 30 DO[3] NC 20 29 DO[2] NC 21 28 DO[1] NC 22 27 DO[0] TRIST 23 26 ORI 25 NC 11 AINT AI Analog Input + 13 AINC AI Analog Input - 16 ITEST AB open=use internal bias circuit VDDA=Power saving (Standby), 17 STBY DI 18 19 AVDD33R AVSS33R PP PG PAD Power (3.3V) PAD Ground Tri-state Buffer Input 23 TRIST DI VDD=High Impedance, GNP=Normal GND=Normal adc1276x Out of Range Indicator 26 ORI DO Normal='Low' Out of Range='High' 27 DO[0] DO Digital Output (LSB) 28~39 DO[1:12] DO Digital Output 40 DO[13] DO Digital Output (MSB) 42 CKIN DI Sampling Clock Input DG DG DP Digital Sub Bias Digital GND Digital Power (3.3V) 44 AVBB33D 45, 46 AVSS33D 47, 48 AVDD33D NC 24 NOTES 1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively SEC ASIC 9/11 ANALOG adc1276x 14BIT 10MSPS ADC USER GUIDE 1. Input Range - If you want to using the single-ended input, you should use he input range as below. AINT : 0.5V ~ 2.5V, AINC : 1.5V. - If you want to using the differential input, you should use the input range as below. AINT : 1.0V ~ 2.0V, AINC : 1.0V ~ 2.0V. AIN : AINT - AINC - If you want to changing input range (AIN span), you can force reference voltages. AIN span = -REF ~ +REF REF = REFTOP - REFBOT 2. Power Consumption/Speed Optimization Yon can optimize the power consumption, as control the ITEST voltage level precisely . You can optimize the ADC's speed also, as control the ITEST voltage level. SEC ASIC 10/11 ANALOG adc1276x 14BIT 10MSPS ADC FEEDBACK REQUEST ADC Specification Parameter Min Typ Max Unit Supply voltage V Reference Input voltage V Analog Input voltage Vpp Operating temperature ºC Integral non-linearity error LSB Differential non-linearity error LSB Offset voltage error Remarks mV (Bottom) Offset voltage error mV (Top) Maximum conversion rate MSPS Dynamic supply current mA Power dissipation mW Signal-to-noise ratio dB Digital output format (Provide detailed description & timing diagram) - What do you want to choose as power supply voltages? For example, the analog VDD needs to be 5V. the digital VDD can be 3.3V/5V. - What resolution do you need for ADC? - How about conversion speed(data in → data out)? - How many cycles do exist during the latency of ADC (pipelined delay)? - What's the input range? And then what do you need between single input and differential input? - Can the bus interface be compatible with TTL? - Could you explain external/internal pin configurations as required? Specially requested function list : SEC ASIC 11/11 ANALOG