ETC AHA3410CSTARLITE

Product Specification
AHA3410C StarLiteTM
25 MBytes/sec Simultaneous Lossless Data
Compression/Decompression Coprocessor IC
2365 NE Hopkins Court
Pullman, WA 99163-5601
tel: 509.334.1000
fax: 509.334.9000
e-mail: sales@aha.com
www.aha.com
advancedhardwarearchitectures
PS3410C-0600
Notes to Customers
Am29K and Fusion29K are Trademarks of Advanced Micro Devices; i960 and
Solutions 960 are Trademarks of Intel Corporation; ColdFIRE is a Trademark of Motorola
Corporation.
PS3410C-0600
Advanced Hardware Architectures, Inc.
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Data Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Pad Word Handling in Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 DMA Request Signals and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.1 FIFO Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.2 Request During an End-of-Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.3 Request Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6 Odd Byte Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6.1 Compression Input and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6.2 Compression Output and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6.3 Decompression Input, Pad Bytes and Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6.4 Decompression Output and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7 Video Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7.1 Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7.2 Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 Compression Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 Decompression Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.11 Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.12 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 System Configuration 0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 System Configuration 1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Input FIFO Thresholds, Address 0x02 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Compression Ports Status, Address 0x04 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 Decompression Ports Status, Address 0x05 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.7 Port Control, Address 0x06 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 Interrupt Status/Control, Address 0x07 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.9 Interrupt Mask, Address 0x09 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.10 Version, Address 0x0A - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.11 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . . . . . . . . . . . . . . . 21
4.12 Record Length, Address 0x10, 0x11, 0x12, 0x13 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.13 Compression Control, Address 0x14 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.14 Compression Reserved, Address 0x15 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.15 Compression Configuration, Address 0x16, 0x17 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.16 Decompression Control, Address 0x18 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.17 Decompression Reserved, Address 0x1A - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.18 Decompression Configuration, Address 0x1C, 0x1D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PS3410C-0600
i
Advanced Hardware Architectures, Inc.
5.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.0 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.0 AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.0 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.2 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.0 Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1 AHA Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.2 Other Technical Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Appendix A:Additional Timing Diagrams for DMA Mode Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
ii
PS3410C-0600
Advanced Hardware Architectures, Inc.
Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure A1:
Figure A2:
Figure A3:
Figure A4:
Figure A5:
Figure A6:
Figure A7:
Figure A8:
Figure A9:
Figure A10:
Figure A11:
Figure A12:
Figure A13:
Figure A14:
Figure A15:
Figure A16:
Figure A17:
Figure A18:
Figure A19:
Figure A20:
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Microprocessor Port Write (PROCMODE[1:0]=“01”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Microprocessor Port Read (PROCMODE[1:0]=“01”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Microprocessor Port Write (PROCMODE[1:0]=“11”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Microprocessor Port Read (PROCMODE[1:0]=“11”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . . 7
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . . 7
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=100. . . . . . . . 7
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=100 . . . . . . . 8
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=100 . . . . . . . 8
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=100 . . . . . . . 8
FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Request vs. End-of-Record, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing Diagram, Video Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing Diagram, Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power vs. Data Rate at 25 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . 31
Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . 32
Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . . . 32
Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output Enable Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Video Input Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Video Output Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Microprocessor Interface Timing (PROCMODE[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Microprocessor Interface Timing (PROCMODE[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . . 41
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . . 41
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=000. . . . . . . 41
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=000 . . . . . . 42
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=000 . . . . . . 42
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000 . . . . . . 42
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . . 43
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . . 43
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=010. . . . . . . 43
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=010 . . . . . . 44
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=010 . . . . . . 44
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=010 . . . . . . 44
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . . 45
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . . 45
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011. . . . . . . 45
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=011 . . . . . . 46
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=011 . . . . . . 46
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=011 . . . . . . 46
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . . 47
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . . 47
PS3410C-0600
iii
Advanced Hardware Architectures, Inc.
Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
iv
Data Bus and FIFO Sizes Supported by StarLiteTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
StarLiteTM Connection to Host Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Microprocessor Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal Strobe Conditions for DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Request vs. EOR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Output Enable Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Video Input Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Video Output Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Microprocessor Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power On Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PS3410C-0600
Advanced Hardware Architectures, Inc.
1.0
INTRODUCTION
StarLite™ is a single chip CMOS VLSI
coprocessor device that implements a lossless
compression and decompression algorithm. The
algorithm exhibits an average compression ratio
over 13 to 1 for bitmap image data. The device
supports simultaneous compression and decompression operations at 25 MBytes/sec each.
The device interfaces directly to various RISC
and CISC processors from AMD, Intel and
Motorola. Compression and decompression data
transfers normally occur over a high speed
bidirectional 32-bit data bus capable of up to 100
MBytes/sec synchronous data rates. Two 8-bit
synchronous video data ports provide ability to
optionally interface to scanner and print engine
respectively for applications such as multifunction
laser printers and copiers.
A low power mode is achieved by stopping all
data transfers and the clock signal. All outputs may
be tristated to facilitate board level testing.
This document contains functional description,
system configurations, register descriptions and
timing diagrams. It is intended for system designers
considering a compression coprocessor in their
embedded applications. Software simulation and an
analysis of the algorithm for printer and copier
images of various complexity are also available for
evaluation. A comprehensive Designer’s Guide
complementing this document is also available from
AHA to assist with the system design. Section 11.0
contains a list of related technical publications.
1.1
CONVENTIONS, NOTATIONS AND
DEFINITIONS
– Active low signals have an “N” appended to the
end of the signal name. For example, CSN and
RDYN.
– A “bar” over a signal name indicates an inverse of
the signal. For example, SD indicates an inverse
of SD. This terminology is used only in logic
equations.
– “Signal assertion” means the output signal is
logically true.
– Hex values are represented with a prefix of “0x”,
such as Register “0x00”. Binary values do not
contain a prefix, for example, DSC=000.
– A range of signal names or register bits is denoted
by a set of colons between the numbers. Most
significant bit is always shown first, followed by
least significant bit. For example, VOD[7:0]
indicates signal names VOD7 through VOD0.
– A logical “AND” function of two signals is
expressed with an “&” between variables.
PS3410C-0600
– Mega Bytes per second is referred to as MBytes/
sec or MB/sec.
– In referencing microprocessors, an x or xx is used
as suffix to indicate more than one processor. For
example, Am290xx processor family includes the
Am29000, 29005, 29030 and 29035.
– Reserved bits in registers are referred as “res”.
– REQN or ACKN refer to either CI, DI, CO or DO
Request or Acknowledge signals, as applicable.
1.2
FEATURES
PERFORMANCE:
• 25 MB/sec compression and decompression rates
• 100 MB/sec burst data rate over a 32-bit data bus
• 25 MB/sec synchronous 8-bit video in and video
out ports
• Simultaneous compression and decompression
operation at full bandwidth
• Average 13 to 1 compression performance for
bitmap image data
FLEXIBILITY:
• Configurable I/O interface for DMA mode; Big
Endian or Little Endian; and 32-bit or 16-bit bus
widths
• Interfaces directly with Am29K or i960 family of
RISC processors and Motorola 68xxx CISC
processors
• Optional 8-bit video input and output ports
• Pass-through mode passes raw data through
compression and decompression engines
• Optional counter enables error checking in
decompression operation
SYSTEM INTERFACE:
• Single chip compression and decompression
solution
• No external SRAM required
• Four 16 × 32-bit FIFOs
• Programmable interrupts
• 25 MHz maximum clock frequency
• Output signals may be tristated to facilitate board
level testing
OTHERS:
• Low power modes
• Software emulation program available
• 120 pin quad flat package
Page 1 of 47
Advanced Hardware Architectures, Inc.
DOREQN
COREQN
DIREQN
CIREQN
SD
DOACKN
COACKN
DIACKN
Functional Block Diagram
CIACKN
Figure 1:
DATA PORT CONTROL
(From Scanner)
VIREQN
VID[7:0]
8
VID
PORT
CI
FIFO
VIACKN
8
COEORN
CO
FIFO
8
COMPRESSOR
16x32
16x32
32
D[31:0]
DRIVEN
DATA
PORT
32
32
(To Printer)
DI
FIFO
8
DO
FIFO
8
DECOMPRESSOR
16x32
16x32
1.3
FUNCTIONAL OVERVIEW
The coprocessor device has three external high
speed synchronous data ports capable of
transferring once every 25 MHz clock. These are a
32-bit bidirectional data port, an 8-bit Video Input
Data (VID) port and a Video Output Data (VOD)
port. The 32-bit port is capable of transferring up to
100 MBytes/sec. The VID and VOD are capable of
up to 25 MBytes/sec each.
The device accepts uncompressed data through
the 8-bit VID port or the 32-bit data port into its
Compression In FIFO (CI FIFO). The 32-bit data
port may be configured for 16-bit transfers.
Compressed data is available through the 32-bit
data port via the Compressed Output FIFO (CO
Table 1:
INTRN
RDYN
DIR
CSN
FIFO). The sustained data rate through the
compression engine is 25 MBytes/sec.
Decompression data may be simultaneously
processed by the device. Decompression data is
accepted through the 32-bit data port, buffered in
the Decompression Input FIFO (DI FIFO) and
decompressed. The output data is made available on
the 32-bit data port via the Decompression Output
FIFO (DO FIFO) or the 8-bit Video Output port.
The decompression engine runs on the 25 MHz
clock and is capable of processing an uncompressed
byte every clock, i.e., 25 MB/sec.
The four FIFOs are organized as 16 × 32 each.
For data transfers through the three ports, the
“effective” FIFO sizes differ according to their data
bus widths. The table below shows the size of the
data port and the “effective” FIFO size for the
various configurations supported by the device.
Data Bus and FIFO Sizes Supported by StarLiteTM
OPERATION
DATA BUS WIDTH
Compression Data In
Compression Data In/Out
Compression Data In/Out
Decompression Data In/Out
Decompression Data In/Out
Decompressed Data Out
8
32
16
32
16
8
Page 2 of 47
VOEORN
VOREQN
VOD[7:0]
VOACKN
5
PA[4:0]
PD[7:0]
8
VOD
PORT
AHA3410C
StarLiteTM
MICROPROCESSOR INTERFACE
PROCMODE[1:0]
RSTN
CLK
TEST
CLOCK
8
PORT
Video In
Data Port
Data Port
Data Port
Data Port
Video Out
EFFECTIVE FIFO SIZE
16 × 8
16 × 32
16 × 16
16 × 32
16 × 16
16 × 8
PS3410C-0600
Advanced Hardware Architectures, Inc.
Table 2:
StarLiteTM Connection to Host Microprocessors
PIN NAME
Am290xx
Am292xx
i960Cx
i960Kx
PA
CSN
DIR
PD
SD
RDYN
DRIVEN
CLOCK
A
CS
R/W
D
VDD
DRDY
System Dependent
SYSCLK
A
PIACS
R/W
ID
VDD
No Connect
PIAOE
MEMCLK
A
CS
W/R
D
WAIT
No Connect
DEN
PCLK
LAD
CS
W/R
LAD
READY
READY
System Dependent
No Connect
Movement of data for compression or
decompression is performed using synchronous
DMA over the 32-bit data port. The Video ports
support synchronous DMA mode transfers. The
DMA strobe conditions are configurable for the 32bit data port depending upon the RISC processor of
the system and the DMA controller available.
Data transfer for compression or decompression
is synchronous over the three data ports functioning
as DMA masters. To initiate a transfer into or out of
the Video ports, the device asserts VxREQN, the
external device responds with VxACKN and begins
to transfer data over the VID or VOD busses on each
succeeding rising edge of the clock until VxREQN
is deasserted. The 32-bit port relies on the FIFO
Threshold settings to determine the transfer.
The sections below describe the various
configurations, programming and other special
considerations in developing a compression system
using StarLiteTM.
2.0
SYSTEM CONFIGURATION
This section provides information on
connecting StarLiteTM to various microprocessors in
DMA mode.
2.1
MICROPROCESSOR INTERFACE
The device is capable of interfacing directly to
various processors for embedded application. The
table below shows how StarLiteTM should be
connected to various host microprocessors.
All register accesses to StarLiteTM are
performed on the 8-bit PD bus. The PD bus is the
lowest byte of the 32-bit microprocessor bus.
During reads of the internal registers, the upper 24
bits are not driven. System designers should
terminate these lines with Pullup resistors.
StarLiteTM provides four modes of operation for
the microprocessor port. Both active high and active
low write enable signals are allowed as well as two
modes for chip select. The mode of operation is set by
PS3410C-0600
the PROCMODE[1:0] pins. The PROCMODE[1]
signal selects when CSN must be active and also how
long an access lasts.
When PROCMODE[1] is high, CSN determines
the length of the access. CSN must be at least 5
clocks in length. On a read, valid data is driven onto
PD[7:0] during the 5th clock. If CSN is longer than 5
clocks, then valid data continues to be driven out
onto PD[7:0]. When CSN goes inactive (high),
PD[7:0] goes tristate (asynchronously) and RDYN is
driven high asynchronously. CSN must be high for at
least two clocks. RDYN is always driven (it is not
tristated when PROCMODE[1] is high). The mode is
typical of processors such as the Motorola 68xxx.
When PROCMODE[1] is low, accesses are
fixed at 5 clocks, PD[7:0] is only driven during the
fifth clock, and RDYN is driven high for the first 4
clocks and low during the fifth clock. RDYN is
tristated at all other times. Write data must be driven
the clock after CSN is sampled low. Accesses may
be back to back with no delays in between. This
mode is typical of RISC processors such as the i960
and Am29K.
PROCMODE[0] determines the polarity of the
DIR pin. If PROCMODE[0] is high, then the DIR
pin is an active low write enable. If PROCMODE[0]
is low, then the DIR pin is an active high write
enable. Figure 2 through Figure 5 illustrate the
detailed timing diagrams for the microprocessor
interface.
For additional notes on interfacing to various
microprocessors, refer to AHA Application Note
(ANDC12), StarLiteTM Designer’s Guide.
Page 3 of 47
Advanced Hardware Architectures, Inc.
Table 3:
Microprocessor Port Configuration
PROCMODE[1:0]
00
01
10
11
Figure 2:
DIR
CYCLE LENGTH EXAMPLE PROCESSOR
Active high write
Active low write
Active high write
Active low write
fixed
fixed
variable
variable
i960
Am29K
68xxx
Microprocessor Port Write (PROCMODE[1:0]=“01”)
CLOCK
PA[4:0]
A0
A1
CSN
DIR
PD[7:0]
D0
D1
RDYN
Figure 3:
Microprocessor Port Read (PROCMODE[1:0]=“01”)
CLOCK
PA[4:0]
A0
A1
A2
CSN
DIR
PD[7:0]
D0
D1
RDYN
Page 4 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
Figure 4:
Microprocessor Port Write (PROCMODE[1:0]=“11”)
CLOCK
A0
PA[4:0]
A1
CSN
DIR
PD[7:0]
D0
RDYN
Figure 5:
Microprocessor Port Read (PROCMODE[1:0]=“11”)
CLOCK
PA[4:0]
A0
A1
CSN
DIR
PD[7:0]
D0
RDYN
PS3410C-0600
Page 5 of 47
Advanced Hardware Architectures, Inc.
3.0
FUNCTIONAL DESCRIPTION
This section describes the various data ports,
special handling, data formats and clocking
structure.
3.1
DATA PORTS
StarLiteTM contains two data input ports, CI and
DI, and two data output ports, CO and DO on the
same 32-bit data bus, D[31:0]. Data transfers can be
controlled by an external DMA control. The logical
conditions under which data is written to the input
FIFOs or read from the output FIFOs are set by the
DSC (Data Strobe Condition) field of the System
Configuration 1 register.
A strobe condition defines under what logical
conditions the input FIFOs are written or the output
FIFOs read. CIACKN, COACKN, DIACKN,
DOACKN, and SD pins combine to strobe data in a
manner similar to DMA controllers. The DMA
Mode sub-section describes the various data strobe
options.
Table 4:
3.2
DMA MODE
DMA data strobes are indicated by setting the
most significant bit of the data strobe condition to
zero (DSC[3]=0).
On the rising edge of CLOCK when the strobe
condition is met, the port with the active
acknowledge either strobes data into or out of the
chip. No more than one port may assert acknowledge
at any one time. Table 4 shows the various
conditions that may be programmed into register
DSC.
Figure 6 through Figure 11 illustrate the DMA
mode timings for single, four word and eight word
burst transfers for DSC=100 selection. For other
DSC settings, please refer to Appendix A. Note that
the only difference between odd and even values of
DSC is the polarity of SD. Waveforms are only
shown for polarities of SD corresponding to specific
systems.
Internal Strobe Conditions for DMA Mode
DSC[3:0]
LOGIC EQUATION
SYSTEM CONFIGURATION
0000
( ACKN ) & ( ACKN delayed ) & ( SD )
i960Cx with internal DMA controller. SD is connected to
WAITN.
0001
( ACKN ) & ( ACKN delayed ) & ( SD ) No specific system
0010
( ACKN ) & ( SD )
General purpose DMA controller
0011
( ACKN ) & ( SD )
i960Kx or Am290xx with external, bus master type DMA
controller. SD is connected to RDYN.
0100
( ACKN delayed ) & ( SD delayed )
Am2924x with internal DMA controller
0101
( ACKN delayed ) & ( SD delayed )
No specific system
0110
( ACKN ) & ( ACKN delayed )
Am2920x with internal DMA controller
0111
( ACKN ) & ( ACKN delayed )
Am2920x with internal DMA controller
ACKN delayed = ACKN delayed 1 clock
SD delayed = SD delayed 1 clock
Page 6 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
Figure 6:
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
Figure 7:
D0
D1
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
Figure 8:
D0
D1
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
PS3410C-0600
D0
D1
D2
D3
Page 7 of 47
Advanced Hardware Architectures, Inc.
Figure 9:
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
D4
D5
D6
D7
Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
Page 8 of 47
D0
D1
D2
D3
D4
D5
D6
D7
PS3410C-0600
Advanced Hardware Architectures, Inc.
3.3
PAD WORD HANDLING IN
BURST MODE
If a word containing an End-of-Record comes
out during a burst read, the words after the End-ofRecord are invalid (pad) words. This prevents a
burst read from crossing record boundaries. The
first word of the next burst read is the first word of
the next record. The pad words must be deleted
during decompression by using the Decompression
Pause on Record Boundaries bit (DPOR), in the
Decompression Control register. After the part is
paused, the DI FIFO must be reset by asserting the
DIRST bit in the Port Control register.
Decompressor must also be reset by asserting DDR
bit in Decompression Control register.
The COEORN signal is asserted when an Endof-Record is present on the output of the CO FIFO.
COEORN is active while the EOR is strobed out. In
some systems COEORN can be used to generate a
DMA-done condition.
3.4
DMA REQUEST SIGNALS
AND STATUS
StarLiteTM requests data using request pins
(CIREQN, DIREQN, COREQN, DOREQN). The
requests are controlled by programmable FIFO
thresholds. Both input and output FIFOs have
programmable empty and full thresholds set in the
Input FIFO Threshold and Output FIFO Threshold
registers. By requesting only when a FIFO can
sustain a certain burst size, the bus is used more
efficiently.
The input requests, CIREQN and DIREQN,
operate under the following prioritized rules:
1) If the FIFO reset in the Port Control register
is active, the request is inactive.
2) If a FIFO overflow interrupt is active, the
request is inactive.
3) If the FIFO is at or below the empty
threshold, the request will go active.
4) If the FIFO is at or above the full threshold,
the request will go inactive.
The output requests, COREQN and DOREQN,
operate under the following prioritized rules:
1) If the FIFO reset in the Port Control register
is active, the request is inactive.
2) If the output FIFO underflow interrupt is
active, the request is inactive.
3) If an EOR is present in the output FIFO, the
request will go active.
4) If the output FIFO is at or above the full
threshold, the request will go active.
PS3410C-0600
5) If an EOR is read (strobed) out of the FIFO,
the request will go inactive during the same
clock as the strobe (if ERC=0), otherwise it
will go inactive on the next clock.
6) If the output FIFO is at or below the empty
threshold, the request will go inactive.
3.4.1
FIFO THRESHOLDS
For maximum efficiency, the FIFO thresholds
should be set in such a way that the compressor
seldom runs out of data from the CI FIFO or
completely fills the output FIFO. The FIFOs are 16
words deep.
For example, in a system with fixed 8-word
bursts, good values for the thresholds are:
IET=3, IFT=4,
OFT=D, OET=C
Setting the input full threshold to one higher
than the input empty threshold simply guarantees
that the request will deassert as soon as possible. The
latency between a word being strobed in and the
request changing due to a FIFO threshold condition
is 3 clocks. This should be kept in mind when
programming threshold values. Refer to AHA
Application Note (ANDC12), StarLiteTM Designer’s
Guide for a more thorough discussion of FIFO
thresholds. The following figure shows an example
of an input FIFO crossing its full threshold.
Page 9 of 47
Advanced Hardware Architectures, Inc.
Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)
CLOCK
D
1
2
3
4
5
6
7
8
2
3
4
5
6
7
CIACKN
CIREQN
Threshold
Counter
Note:
1
8
9
CIREQN deasserted when threshold counter exceeded IFT=4.
Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010
CLOCK
ACKN
D
EOR-2
EOR-1
EOR
REQN
(ERC=0)
REQN
(ERC=1)
3.4.2
REQUEST DURING AN END-OF-RECORD
The request deasserts at an EOR in one of two
ways. If ERC bit in System Configuration 1 is ‘0’,
the request will deassert asynchronously during the
clock where the EOR is strobed out of the FIFO.
This leads to a long output delay for REQN, but may
be necessary in some systems. For DSC values of 4
or 5, the request deasserts the first clock after the
acknowledge pulse for the EOR. If ERC is set to ‘1’,
then the request deasserts synchronously the clock
after the EOR is strobed out. The minimum low
time on the request in this case is one clock.
The request delay varies between the different
strobe conditions. See the timing section for further
details.
Page 10 of 47
3.4.3
REQUEST STATUS BITS
An external microprocessor can also read the
value of each request using the CIREQ and COREQ
bits in the Compression Port Status register and the
DIREQ and DOREQ bits in the Decompression
Port Status register. Please note that the request
status bits are active high while the pins are active
low.
PS3410C-0600
Advanced Hardware Architectures, Inc.
3.5
DATA FORMAT
The width of the D bus is selected with the WIDE
bit in System Configuration 0. If WIDE=1, then D is
a 32-bit bus. If WIDE=0, D is a 16-bit bus. If the bus is
configured to be 16-bits wide (WIDE=0), all data
transfers occur on D[15:0] and the upper 16 bits of the
bus, D[31:16], should be terminated with Pullup
resistors. If WIDE=0, the FIFO is sixteen words deep.
Since the compression algorithm is byte
oriented, it is necessary for StarLiteTM to know the
ordering of the bytes within the word. The BIG bit
in System Configuration 0 selects between big
endian and little endian byte ordering. Little endian
stores the first byte in the lower eight bits of a word
(D[7:0]). Big endian stores the first byte in the
uppermost eight bits of a word (D[31:24] for
WIDE=1, D[15:8] for WIDE=0).
3.6
ODD BYTE HANDLING
All data transfers to or from either the
compression or decompression engines are performed
on the D bus on word boundaries. Since no provision
is made for single byte transfers, occasionally words
will contain pad bytes. Following is a description of
when these pad bytes are necessary for each of the
data interfaces.
3.6.1
COMPRESSION INPUT AND PAD BYTES
Uncompressed data input into StarLiteTM is
treated as records. The length of these records is
fixed by the value in the Record Length or RLEN
register. This register contains the number of
uncompressed bytes in each record. If the value in
RLEN is not an integer multiple of number of bytes
per word as selected by WIDE, the final word in the
transfer of the record will contain pad bytes which
are discarded and have no effect on either the
dictionary or the output data stream. The next record
must begin on a word boundary.
The minimum value for RLEN is 4.
3.6.2
3.6.3
DECOMPRESSION INPUT, PAD BYTES
AND ERROR CHECKING
This port recognizes the end of a record by the
appearance of a special End-of-Record sequence in
the data stream. Once this is seen, the remaining
bytes in the current word are treated as pad bytes
and discarded. The word following the end of the
record is the beginning of the next record.
When operating in decompression mode, the
Decompression Record Length (DRLEN) register
can be used to provide error checking. The expected
length of the decompressed record is programmed
into the DRLEN register. The decompressor then
counts down from the value in DRLEN to ‘0’.
A DERR interrupt is issued if an EOR is not
read out of the decompressor when the counter
expires or if an EOR occurs before the counter
expires (i.e., when the record lengths do not match).
If the DERR interrupt is masked, use of the DRLEN
register is optional.
When operating in pass-through mode, there is
no End-of-Record codeword for the decompressor
to see. In pass-through mode, the user must set the
record length in the DRLEN register.
3.6.4
DECOMPRESSION OUTPUT AND
PAD BYTES
When the decompressor detects an End-ofRecord codeword, it will add enough pad bytes of
value 0x00 to complete the current word.
COMPRESSION OUTPUT AND
PAD BYTES
If a record ends on a byte other than the last byte
in a word, the final word will contain 1, 2 or 3 pad
bytes. The pad bytes have a value of 0x00.
PS3410C-0600
Page 11 of 47
Advanced Hardware Architectures, Inc.
3.7
VIDEO INTERFACES
3.7.2
3.7.1
VIDEO INPUT
The video output port is enabled by the VDOE
bit in the System Configuration 1 register. The port
uses VOREQN to indicate that the byte on
VOD[7:0] is valid. An 8-bit word is read each clock
when both VOREQN and VOACKN are sampled
low on a rising edge of CLOCK. Pad bytes at an end
of record are discarded by the video output port and
do not appear on VOD[7:0]. When the byte on
VOD[7:0] is the last byte in a record, the VOEORN
signal will go low. VOEORN is active while an
EOR is read out. Unlike a DMA transfer, there are
no pad bytes after an End-of-Record.
The port requests whenever a valid byte is
present on the output. The values in OET and OFT
are all ignored. The decompression output FIFO is
16 bytes deep in this mode. The video output port
can output up to one byte per clock (25 MB/sec).
The DMA interface cannot access the
decompression output FIFO when VDOE is set.
The video input port is enabled by the VDIE bit
in the System Configuration 1 register. The port uses
VIREQN to indicate that the port can accept another
byte. The value on VID[7:0] is written into
StarLiteTM each clock that VIREQN and VIACKN
are both low.
The video input port asserts VIREQN whenever
there is room in the CI FIFO. The values in IET and
IFT are all ignored. The compression input FIFO is
16 bytes deep in this mode. The video input port can
transfer up to one byte per clock (25 MB/sec). The
DMA interface cannot access the compression input
FIFO when VDIE is set.
VIDEO OUTPUT
Figure 14: Timing Diagram, Video Input
CLOCK
VIREQN
VIACKN
VID[7:0]
don’t
care
0
1
2
don’t care
3
4
5
don’t
care
Figure 15: Timing Diagram, Video Output
CLOCK
VOREQN
VOACKN
VOD[7:0]
0
1
2
3
4
5
VOEORN
Page 12 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
3.8
COMPRESSION ENGINE
The compression engine supports either
compression or pass-through processes. The
compression engine is enabled with the COMP bit
in the Compression Control register. When the
engine is enabled, it takes data from the CI FIFO as
it becomes available. This data is either compressed
by the engine or passed through unaltered. This
pass-through mode is selected with the CPASS bit in
the Compression Control register. The CPASS bit
may only be changed when COMP is set to ‘0’. The
contents of the dictionary are preserved when
COMP is changed. However, when CPASS is
changed, the contents are lost. Consequently,
StarLiteTM can not be changed from pass-through
mode to compression mode or vice versa without
losing the contents of the dictionary.
The compressor can be instructed to halt input
at the end of each record. If the CPOR bit is set, the
compressor will stop taking bytes out of the CI
FIFO immediately after the last byte of a record. In
addition, the COMP bit will be cleared. The CEMP
bit will then indicate when all of the data has left the
compressor. Compression is restarted by setting the
COMP bit.
The compression engine takes data from the
compression input FIFO at a maximum rate of 25
MBytes/sec. Two conditions cause the data rate to
drop below the maximum. The first is caused by the
compression input FIFO running empty of data to
be compressed. The second condition is caused by
the output FIFO filling. When this occurs, the
engine halts and waits for the FIFO. While halted,
the engine goes into a low power standby mode.
Refer to the table in Section 7.1 for the extent of
power savings.
3.9
DECOMPRESSION ENGINE
The decompression engine is enabled with the
DCOMP bit in the Decompression Control register.
When the engine is enabled, it takes data from the
DI FIFO as it becomes available. This data is either
decompressed by the engine or passed through
unaltered. Pass-through mode is selected with the
DPASS bit. DPASS may only be changed when
DCOMP is set to ‘0’ and DEMP is set to ‘1’. The
contents of the dictionary are preserved when
DCOMP is changed. However, when DPASS is
changed, the contents are lost. Consequently,
StarLiteTM can not be changed from pass-through
mode to decompression mode or vice versa without
losing the contents of the dictionary.
The decompressor can be instructed to halt
operation at the end of each record. If the DPOR bit
is set, the decompressor will stop processing
PS3410C-0600
additional data after it decodes an End-of-Record
and DCOMP will be cleared. If DPOR is set and
data from a second record enters the FIFO
immediately after the first record, bytes from the
second record will have entered the decompressor
prior to decoding the EOR. An implication of this is
that bytes from the second record will remain in the
decompressor and prevent DEMP from setting after
all of the data from the first record has left the
decompressor. This differs from operation of the
compression engine. In either mode, a DOEOR
interrupt is generated when the last byte of a
compressed record is read out of the chip.
The decompressor takes data from the
decompression input FIFO at a maximum rate of
25 MBytes/sec. StarLiteTM can maintain this data
rate as long as the decompression input FIFO is not
empty or the decompression output FIFO is not full.
3.10 INTERRUPTS
Seven conditions are reported in the Interrupt
Status/Control register as individual bits. All
interrupts are maskable by setting the corresponding
bits in the Interrupt Mask register. A ‘1’ in the
Interrupt Mask register means the corresponding bit
in the Interrupt Status/Control register is masked
and does not affect the interrupt pin (INTRN). The
INTRN pin is active whenever any unmasked
interrupt bit is set to a ‘1’.
End-of-Record interrupts are posted when a
word containing an end-of-record is strobed out of
the compression or decompression output FIFOs
(CEOR and DEOR respectively). A DEOR interrupt
is also reported if an end-of-record is read from the
video output port.
Four FIFO error conditions are also reported.
Overflowing the input FIFOs generates a CIOF or
DIOF interrupt. An overflow can only be cleared by
resetting the respective FIFO via the Port Control
register.
Underflowing the output FIFOs (reading when
they are not ready) generates a COUF or DOUF.
Underflow interrupts are cleared by writing a ‘1’ to
COUF or DOUF. In the event of an underflow, the
respective FIFO must be reset. Note that in systems
using fixed length bursts which rearbitrate during a
burst, the CO FIFO may request another burst when
the record actually finishes near the end of the
current burst. In this scenario a second burst takes
place causing a FIFO underflow. As long as a pause
on End-of-Record is used, data is not corrupted. The
FIFO simply must be reset.
Page 13 of 47
Advanced Hardware Architectures, Inc.
3.11
LOW POWER MODE
The AHA3410C is a data-driven system. When
no data transfers are taking place, only the clock and
on-chip RAMs including the FIFOs require power.
To reduce power consumption to its absolute
minimum, the user can stop the clock when it is
high. With the system clock stopped and at a high
level, the only current required is due to leakage.
Control and Status registers are preserved in this
mode. Reinitialization of Control registers are not
necessary when switching from Low Power to
Normal operating mode.
Page 14 of 47
3.12 TEST MODE
In order to facilitate board level testing, the
AHA3410C provides the ability to tristate all
outputs. When the TEST pin is high, all outputs of
the chip are tristated. When test is low, the chip
returns to normal operation.
PS3410C-0600
Advanced Hardware Architectures, Inc.
4.0
REGISTER DESCRIPTIONS
The microprocessor configures, controls and monitors IC operation through the use of the registers
defined in this section. All write registers are readable with the exception of Record Length registers. All
registers are reset to ‘0’ on RSTN unless otherwise stated. The bits labeled “res” are reserved and must be
set to ‘0’ when writing to registers unless otherwise noted.
A summary of registers is listed below.
Table 5:
Internal Registers
ADDRESS R/W
DESCRIPTION
00
R/W System Configuration 0
01
R/W System Configuration 1
02
R/W Input FIFO Thresholds
03
R/W Output FIFO Thresholds
04
R
Compression Ports Status
05
R
Decompression Ports Status
06
07
09
0A
R/W
R/W
R/W
R
0C
R/W
Port Control
Interrupt Status/Control
Interrupt Mask
Version
FUNCTION
Big Endian vs. Little Endian, 32bit vs. 16-bit
Data Strobe Condition, EOR
Request Control, VDO Port
Enable, VDI Port Enable
Undefined
Input FIFOs Empty Threshold,
Full Threshold
Output FIFOs Empty Threshold,
Full Threshold
FIFO Status, Request Status, EOR
Status
FIFO Status, Request Status, EOR
Status
Reset Individual FIFOs
EOR, Overflow, Underflow
Interrupt Mask bits
Die Version Number
Undefined
Bytes Remaining in Transfer,
Byte 0
0F
Decompression Record
Length 0
Decompression Record
R/W
Length 1
Decompression Record
R/W
Length 2
Decompression Record
R/W Length 3
10
R/W Record Length 0
11
12
13
R/W Record Length 1
R/W Record Length 2
R/W Record Length 3
Length of Uncompressed Data in
Bytes, Byte 0
"
" , Byte 1
"
" , Byte 2
"
" , Byte 3
0D
0E
14
R/W Compression Control
15
16
17
R/W Compression Reserved
R/W Compression Configuration 0
R/W Compression Configuration 1
PS3410C-0600
DEFAULT
AFTER RSTN
0x00
Undefined
Undefined
Undefined
0x0F
0x00
0xFF
0x21
0xFF
"
"
, Byte 1
0xFF
"
"
, Byte 2
0xFF
"
"
, Byte 3
0xFF
Pause on Record Boundaries,
Enable Compression, Compression Engine Empty Status, Compression Dictionary Reset, Select
Pass-Through Mode
For Production Testing Only
Line Length Register Lower 8 bits
Line Length Register Upper 3 bits
Undefined
Undefined
Undefined
Undefined
0x04
0x00
Undefined
Undefined
Page 15 of 47
Advanced Hardware Architectures, Inc.
ADDRESS R/W
18
R/W
1A
1C
1D
R/W
R/W
R/W
4.1
DESCRIPTION
DEFAULT
AFTER RSTN
FUNCTION
Pause on Record Boundaries,
Enable Decompression Engine,
Decompression Control
Decompression Engine Empty
Status, Dictionary Reset, Enable
Pass-Through Mode
Decompression Reserved
For Production Testing Only
Decompression Configuration 0 Line Length Register Lower 8 bits
Decompression Configuration 1 Line Length Register Upper 3 bits
0x04
0x00
Undefined
Undefined
SYSTEM CONFIGURATION 0, ADDRESS 0x00 - READ/WRITE
Address
(hex)
00
bit7
bit6
bit5
BIG
WIDE
res
bit4
bit3
bit2
bit1
bit0
res
This register is not cleared by reset and must be initialized prior to any data transfer.
X
WIDE -
Selects between 32 and 16-bit D buses.
BIG -
Select between little and big endian data orders. The least significant bit in a byte is always in
position ‘0’.
BIG
WIDE
0
0
0
1
1
Page 16 of 47
1
0
1
DESCRIPTION
Little Endian data order
Little Endian data order
D[31:24]
Byte 3
D[23:16]
Byte 2
Big Endian data order
Big Endian data order
D[31:24]
Byte 0
D[23:16]
Byte 1
16-bit words
D[15:8]
Byte 1
D[7:0]
Byte 0
32-bit words
D[15:8]
Byte 1
D[7:0]
Byte 0
16-bit words
D[15:8]
Byte 0
D[7:0]
Byte 1
32-bit words
D[15:8]
Byte 2
D[7:0]
Byte 3
PS3410C-0600
Advanced Hardware Architectures, Inc.
4.2
SYSTEM CONFIGURATION 1, ADDRESS 0x01 - READ/WRITE
Address
(hex)
01
bit7
bit6
bit5
bit4
res
VDIE
VDOE
ERC
bit3
bit2
bit1
bit0
DSC[3:0]
This register is cleared by reset.
DSC[3:0] - Data Strobe Condition. Control the condition used to strobe data into and out of the data ports
on the D bus. Table 4 shows the programming for the strobe condition for DMA data transfer
modes.
ERC -
EOR Request Control. Determines when COREQN and DOREQN deassert at an End-ofRecord. If ERC=0 then the request deasserts asynchronously during the clock when an EOR is
strobed out. If ERC=1 then the request deasserts synchronously the clock after an EOR is
strobed out. See Figure 19.
VDOE -
VDO Port Enable. When this bit is set, the data from the decompression output FIFO goes to
the VDO port. When the bit is clear, the decompressed data is read by DMA on the D bus.
VDIE -
VDI Port Enable. When this bit is set, the VDI port will handshake data and write it into the
compression input FIFO. When the bit is clear, the compression input FIFO is written by DMA
from the D bus.
4.3
INPUT FIFO THRESHOLDS, ADDRESS 0x02 - READ/WRITE
Address
(hex)
02
bit7
bit6
bit5
bit4
bit3
IFT[3:0]
bit2
bit1
bit0
IET[3:0]
This register is readable and writable. After reset, its contents are undefined. It must be written before
any input or output data movement may be performed.
IET[3:0] - Empty threshold for input FIFOs. If the number of words in the input FIFO (CI or DI) is less
than or equal to this number, the request for that channel will be asserted.
IFT[3:0] - Full threshold for input FIFOs. If the number of words in the input FIFO (CI or DI) is greater
than or equal to this number, the request for the channel is deasserted.
4.4
OUTPUT FIFO THRESHOLDS, ADDRESS 0x03 - READ/WRITE
Address
(hex)
03
bit7
bit6
bit5
OFT[3:0]
bit4
bit3
bit2
bit1
bit0
OET[3:0]
This register is readable and writable. After reset, its contents are undefined. It must be written before
any input or output data movement may be performed.
OET[3:0] - Empty threshold for output FIFOs. If the number of words in the output FIFO (CO or DO) is
less than or equal to this number, the request for the channel will be deasserted (except in the
case of an End-of-Record).
OFT[3:0] - Full threshold for output FIFOs. If the number of words in the output FIFO (CO or DO) is
greater than or equal to this number, the request for that channel will be asserted.
PS3410C-0600
Page 17 of 47
Advanced Hardware Architectures, Inc.
4.5
COMPRESSION PORTS STATUS, ADDRESS 0x04 - READ ONLY
Address
(hex)
04
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
COEMP
CIEMP
res
COEOR
COREQ
COET
CIREQ
CIFT
This is a read only register. Writing to this register has no effect. After reset, its contents are undefined.
CIFT -
Compression input FIFO full threshold. This signal is active when the CI FIFO is greater than
or equal to the programmed FIFO full threshold. After reset and the Input FIFO Threshold
register has been written, this bit contains a ‘0’.
CIREQ -
Compression input request signal state. Reports the current state for the CIREQN pin. Notice
that this bit is active high while the pin is active low. Therefore, the value of this bit will always
be the inverse of the value of the signal. After reset this bit contains a ‘0’.
COET -
Compression output FIFO empty threshold. This signal is active when the CO FIFO is less than
or equal to the programmed FIFO empty threshold. After reset and the Output FIFO Threshold
register has been written, this bit contains a ‘1’.
COREQ - Compression output request signal state. Reports the current state for the COREQN pin. Notice
that this bit is active high while the pin is active low. Therefore, the value of this bit will always
be the inverse of the value of the signal. After reset this bit contains a ‘0’.
COEOR - Compression output end of record. This signal is active when the output FIFO contains the endof-record code. After reset this bit contains a ‘0’.
CIEMP -
Compression input empty. This bit is active when the CI FIFO is empty. After reset this bit
contains a ‘1’.
COEMP - Compression output empty. This bit is active when the CO FIFO is empty. After reset this bit
contains a ‘1’.
4.6
DECOMPRESSION PORTS STATUS, ADDRESS 0x05 - READ ONLY
Address
(hex)
05
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DOEMP
DIEMP
res
DOEOR
DOREQ
DOET
DIREQ
DIFT
This is a read only register. Writing to this register has no effect. After reset, its contents are undefined.
DIFT -
Decompression input FIFO full threshold. This signal is active when the DI FIFO is at or above
the programmed FIFO full threshold. After reset and the Input FIFO Threshold register has
been written, this bit contains a ‘0’.
DIREQ -
Decompression input request signal state. Reports the current state for the DIREQN pin. Notice
that this bit is active high while the pin is active low. Therefore, the value of this bit will always
be the inverse of the value of the signal. After reset this bit contains a ‘0’.
DOET -
Decompression output FIFO empty threshold. This signal is active when the DO FIFO is at or
below the programmed FIFO empty threshold. After reset and the Output FIFO Threshold
register has been written, this bit contains a ‘1’.
DOREQ - Decompression output request signal state. Reports the current state for the DOREQN pin.
Notice that this bit is active high while the pin is active low. Therefore, the value of this bit will
always be the inverse of the value of the signal. After reset this bit contains a ‘0’.
DOEOR - Decompression output end of record. This signal is active when the output FIFO contains the
End-of-Record code. After reset this bit contains a ‘0’.
DIEMP -
Decompression input empty. This bit is active when the DI FIFO is empty. After reset this bit
contains a ‘1’.
DOEMP - Decompression output empty. This bit is active when the DO FIFO is empty. After reset this bit
contains a ‘1’.
Page 18 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
4.7
PORT CONTROL, ADDRESS 0x06 - READ/WRITE
Address
(hex)
06
bit7
bit6
bit5
bit4
res
bit3
bit2
bit1
bit0
DORST
DIRST
CORST
CIRST
This register is initialized to ‘0F’ after reset.
CIRST -
Compression input reset. Setting this bit to a ‘1’ resets the CI FIFO and clears state machines on
the compression input port. The reset condition will remain active until the microprocessor
writes a ‘0’ to this bit.
CORST -
Compression output reset. Setting this bit to a ‘1’ resets the CO FIFO and clears state machines
on the compression output port. The reset condition will remain active until the microprocessor
writes a ‘0’ to this bit.
DIRST -
Decompression input reset. Setting this bit to a ‘1’ resets the DI FIFO and clears the state
machines in the decompression input port. The reset condition will remain active until the
microprocessor writes a ‘0’ to this bit.
DORST -
Decompression output reset. Setting this bit to a ‘1’ resets the DO FIFO and clears the state
machines in the decompression output port. The reset condition will remain active until the
microprocessor writes a ‘0’ to this bit.
4.8
INTERRUPT STATUS/CONTROL, ADDRESS 0x07 - READ/WRITE
Address
(hex)
07
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DOUF
COUF
DIOF
CIOF
res
DERR
DEOR
CEOR
This register is initialized to ‘00’ after reset.
CEOR -
Compression End-of-Record interrupt. This bit is set when an End-of-Record codeword is
strobed out of the compression output port. To clear this interrupt the microprocessor must
write a ‘1’ to this bit.
DEOR -
Decompression End-of-Record interrupt. This bit is set when the last byte of a record is strobed
out of the decompression DMA or video output port. To clear this interrupt the microprocessor
must write a ‘1’ to this bit.
DERR -
Decompression Error. This bit is set if an EOR leaves the decompressor before DRLEN has
counted down to zero or if DRLEN counts to zero and the last byte is not an EOR. DERR is
only active in decompression mode (DPASS=0). To clear this interrupt, the microprocessor
must write a ‘1’ to this bit.
CIOF -
Compression Input FIFO Overflow. This interrupt is generated when a write to the CI FIFO is
performed when it is full. All data written when the FIFO is full is lost. The only means of
recovery from this error is to reset the FIFO with the CIRST bit. Resetting the FIFO causes this
interrupt to clear. While the interrupt is set CIREQN is inactive.
DIOF -
Decompression Input FIFO Overflow. This interrupt is generated when a write to the DI FIFO
is performed when it is full. All data written when the FIFO is full is lost. The only means of
recovery from this error is to reset the FIFO with the DIRST bit. Resetting the FIFO causes this
interrupt to clear. While the interrupt is set DIREQN is inactive.
PS3410C-0600
Page 19 of 47
Advanced Hardware Architectures, Inc.
COUF -
Compression Output FIFO underflow. This interrupt is generated when a read from the CO
FIFO is performed when it is empty. Once this interrupt is set, the CO FIFO must be reset with
the CORST bit. To clear this interrupt the microprocessor must write a ‘1’ to this bit. While the
interrupt is set, COREQN is inactive.
DOUF -
Decompression Output FIFO underflow. This interrupt is generated when a read from the DO
FIFO is performed when it is empty. Once this interrupt is set, the DO FIFO must be reset with
the DORST bit. To clear this interrupt the microprocessor must write a ‘1’ to this bit. While the
interrupt is set, DOREQN is inactive.
4.9
INTERRUPT MASK, ADDRESS 0x09 - READ/WRITE
Address
(hex)
09
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DOUFM
COUFM
DIOFM
CIOFM
res
DERRM
DEORM
CEORM
This register is initialized to ‘FF’ after reset.
CEORM - Compression End-of-Record Interrupt Mask. When set to a ‘1’, prevents Compression End-ofRecord from causing INTRN to go active.
DEORM - Decompression End-of-Record Interrupt Mask. When set to a ‘1’, prevents Decompression
End-of-Record from causing INTRN to go active.
DERRM - Decompression Error Mask. When set to a ‘1’, prevents a decompression error (DERR) from
causing INTRN to go active.
CIOFM -
Compression Input FIFO Overflow Mask. When set to a ‘1’, prevents a compression input
FIFO overflow (CIOF) from causing INTRN to go active.
DIOFM -
Decompression Input FIFO Overflow Mask. When set to a ‘1’, prevents a decompression input
FIFO overflow (DIOF) from causing INTRN to go active.
COUFM - Compression Output FIFO Underflow Mask. When set to a ‘1’, prevents a compression output
FIFO underflow (COUF) from causing INTRN to go active.
DOUFM - Decompression Output FIFO Underflow Mask. When set to a ‘1’, prevents a decompression
output FIFO underflow (DOUF) from causing INTRN to go active.
4.10 VERSION, ADDRESS 0x0A - READ ONLY
Address
(hex)
0A
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
VERSION[7:0]
This is a read only register. Writing to this register has no effect on IC operation.
VERSION[7:0] - Contains version number of the die. Initial version is 0x21.
Page 20 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
4.11
DECOMPRESSION RECORD LENGTH, ADDRESS 0x0C, 0x0D, 0x0E, 0x0F READ/WRITE
Address
(hex)
0C
0D
0E
0F
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DRLEN[7:0]
DRLEN[15:8]
DRLEN[23:16]
DRLEN[31:24]
These registers are initialized to ‘FF’ after reset.
DRLEN[31:0]-Decompression Record Length. Contains the number of bytes in a decompressed record.
These registers provide different functions depending on whether the decompressor is in passthrough or decompression mode. In decompress mode, the data itself contains EOR
information and DRLEN is only used for error checking. DRLEN is decremented each time a
byte leaves the decompressor.
In decompression mode, a DERR interrupt is issued if an EOR is not read out of the
decompressor when the counter expires or if an EOR occurs before the counter expires (i.e.,
when the record lengths do not match). If the DERR interrupt is masked, use of the DRLEN
register is optional in decompression mode.
In pass-through mode, DRLEN determines the size of records read out of the decompressor.
The counter is decremented for each byte read into the decompressor.
In either mode, the counter reloads when it reaches zero or when DRLEN[31:24] is written.
Reading DRLEN returns the number of bytes left in the count.
4.12 RECORD LENGTH, ADDRESS 0x10, 0x11, 0x12, 0x13 - READ/WRITE
Address
(hex)
10
11
12
13
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RLEN[7:0]
RLEN[15:8]
RLEN[23:16]
RLEN[31:24]
These registers are undefined after reset.
RLEN[31:0]- Record Length. Length of an uncompressed record in bytes. Writing these addresses sets a
register containing the length of a record. Reading these addresses returns a counter indicating
the number of bytes remaining in the current record. The counter is decremented each time a
byte leaves the CI FIFO. The counter automatically reloads from the register at the end of a
record. The counter is also reloaded when RLEN[31:24] is written. The record length register
is also valid during pass-through operation.
The minimum value for RLEN is 4.
PS3410C-0600
Page 21 of 47
Advanced Hardware Architectures, Inc.
4.13 COMPRESSION CONTROL, ADDRESS 0x14 - READ/WRITE
Address
(hex)
14
bit7
bit6
bit5
res
bit4
bit3
bit2
bit1
bit0
CPASS
CDR
CEMP
COMP
CPOR
This register is initialized to ‘04’ after reset.
CPOR -
Compression Pause on record boundaries. When this bit is set to ‘1’, the compressor stops
taking data from the input FIFO once a record boundary is found. A record boundary is
indicated by the RLEN register decrementing to ‘0’. Upon finding the record boundary, COMP
is cleared. This bit may only be changed when COMP is set to ‘0’. After system reset, this bit
is cleared.
COMP -
Compression. Setting this bit to a ‘1’ enables the data compression engine (or pass-through mode
if CPASS is set) to take data from the compression input FIFO. If this bit is cleared, compression
stops. The bit is automatically cleared at the end of a record if CPOR is set. The compression can
be restarted without loss of data by setting COMP. After reset, this bit is cleared.
CEMP -
Compression engine empty. This bit is set to a ‘1’ when no data is present inside the
compressor. Writing to this bit has no effect. After system reset, this bit is set.
CDR -
Compression Dictionary Reset. Setting this bit immediately resets the compressor including the
compression dictionary. The reset condition will remain active until the microprocessor writes
a ‘0’ to this bit.
CPASS -
Compression pass-through mode. While this bit is set, data is passed directly through the
compression engine without any effect on either the dictionary or the data itself. This bit may only
be changed when compression is disabled (COMP=0) and the compression engine is empty of
data (CEMP=0). The pass-through operation is started by setting COMP. To stop the passthrough operation, COMP should be cleared (to pause operation) and then CPASS may be
cleared.
bit[5] -
Reserved. Set to ‘0’.
bit[7:6] -
Reserved. Set to ‘0’.
4.14 COMPRESSION RESERVED, ADDRESS 0x15 - READ/WRITE
Address
(hex)
15
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
res
This register is used for production testing. Must be written with ‘0’ if at all. Resets to ‘0’.
4.15 COMPRESSION CONFIGURATION, ADDRESS 0x16, 0x17 - READ/WRITE
Address
(hex)
16
17
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LINE[7:0]
res
LINE[10:8]
This register contains information necessary for the compression operation. It must be set prior to any
compression operation. It should only be changed when COMP is cleared and CEMP is set. After changing
compression configuration, the compressor should be reset using CDR. These registers are undefined after
reset.
LINE[10:0]-Line length. The number of bytes in the scan line is programmed here. Minimum value is 16.
Page 22 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
4.16 DECOMPRESSION CONTROL, ADDRESS 0x18 - READ/WRITE
Address
(hex)
18
bit7
bit6
bit5
res
bit4
bit3
bit2
bit1
bit0
DPASS
DDR
DEMP
DCOMP
DPOR
This register is initialized to ‘04’ after reset.
DPOR -
Decompression Pause on record boundaries. When this bit is set to ‘1’, the decompressor stops
taking data from the input FIFO once a record boundary is found. Upon finding the record
boundary, DCOMP is cleared. This bit may only be changed when DCOMP is set to ‘0’. After
system reset or DDR, this bit is cleared.
DCOMP - Decompression. Setting this bit to a ‘1’ enables the decompression engine (or pass-through
mode if DPASS is set) to take data from the decompression input FIFO. If this bit is cleared,
decompression stops. The bit is automatically cleared at the end of a record if DPOR is set.
Decompression can be restarted without loss of data by setting DCOMP. After system reset or
DDR, this bit is cleared.
DEMP -
Decompression engine empty. This bit is set when the decompression engine is cleared of data.
Writing to this bit has no effect. After system reset, this bit is set.
DDR -
Decompression Dictionary Reset. Setting this bit immediately resets the decompressor
including the decompression dictionary. The reset condition will remain active until the
microprocessor writes a ‘0’ to this bit.
DPASS -
Decompression pass-through mode. While this bit is set, data is passed directly through the
decompression engine without any effect on the data. This bit may only be changed when
decompression is disabled (DCOMP=0) and the decompression engine is empty of data
(DEMP=1). The pass-through operation is started by setting DCOMP. To stop the pass-through
operation, DCOMP should be cleared (to pause operation) and then DPASS may be cleared.
4.17 DECOMPRESSION RESERVED, ADDRESS 0x1A - READ/WRITE
Address
(hex)
1A
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
res
This register is used for production testing only. Must be written with ‘0’ if at all. Initialized to ‘00’ after
reset.
4.18 DECOMPRESSION CONFIGURATION, ADDRESS 0x1C, 0x1D - READ/WRITE
Address
(hex)
1C
1D
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LINE[7:0]
res
LINE[10:8]
This register contains information necessary for the decompression operation. It must be set prior to any
decompression operation. It should only be changed between records when DCOMP is cleared and DEMP
is set. These registers are undefined after reset.
LINE[10:0]-Line length. The number of bytes in the scan line is programmed here. Minimum value is 16.
For scan line lengths larger than the maximum allowed, set to 16.
PS3410C-0600
Page 23 of 47
Advanced Hardware Architectures, Inc.
5.0
SIGNAL DESCRIPTIONS
This section contains descriptions for all the pins. Each signal has a type code associated with it. The
type codes are described in the following table.
TYPE CODE
I
O
I/O
S
A
5.1
DESCRIPTION
Input only pin
Output only pin
Input/Output pin
Synchronous signal
Asynchronous signal
MICROPROCESSOR INTERFACE
SIGNAL
MICROPROCESSOR INTERFACE
TYPE
DESCRIPTION
PD[7:0]
I/O
S
PA[4:0]
I
S
I
S
CSN
DIR
I
S
RDYN
O
A,S
INTRN
O
S
PROCMODE[1:0]
I
S
Page 24 of 47
Processor Data. Data for all microprocessor reads and writes of
registers within StarLiteTM are performed on this bus. This bus may
be tied to the Data bus, D[31:0], provided microprocessor accesses
do not occur at the same time as DMA accesses.
Processor Address Bus. Used to address internal registers within
StarLiteTM.
Chip Select. Selects StarLiteTM as the source or destination of the
current microprocessor bus cycle. CSN needs only be active for one
clock cycle to start a microprocessor access.
Direction. This signal indicates whether the access to the register
specified by the PA bus is a read or a write. The polarity of this signal
is programmed with the PROCMODE0 pin.
Ready. Indicates valid data is on the data bus during read operation
and completion of write operation. Its operation depends on
PROCMODE[1:0] settings.
Interrupt. The compression and decompression processes generate
interrupts that are reported with this signal. INTRN is low whenever
any non-masked bits are set in the Interrupt Status/Control register.
Microprocessor Port Configuration Mode. Selects the polarity of the
DIR pin and operation of the CSN pin.
00 Active high write, fixed cycle
01 Active low write, fixed cycle
10 Active high write, variable cycle
11 Active low write, variable cycle
(See Figure 2 through Figure 5 for details.)
PS3410C-0600
Advanced Hardware Architectures, Inc.
5.2
DATA INTERFACE
SIGNAL
D[31:0]
TYPE
I/O
S
DRIVEN
I
A
SD
I
S
CIREQN
O
S
I
S
CIACKN
COREQN
COACKN
O
A,S
I
S
COEORN
O
S
DIREQN
O
S
I
S
DIACKN
DOREQN
DOACKN
PS3410C-0600
O
A, S
I
S
DATA INTERFACE
DESCRIPTION
Data for all channels is transmitted on this bus. The ACKN or FA[1:0] is
used to distinguish between the four channels. Data being written to
StarLiteTM is latched on the rising edge of CLOCK when the strobe
condition is met. Data setup and hold times are relative to CLOCK. If the
bus is configured to 16-bit transfers (WIDE=0), data is carried on
D[15:0]. In this case, D[31:16] should be terminated with pullup
resistors.
Drive Enable. Active low output driver enable. This input must be low in
order to drive data onto D[31:0] in accordance with the current strobe
condition.
Strobe Delay. Allows insertion of wait states for DMA access to the
FIFOs. The strobe condition, as programmed in the DSC field of System
Configuration 1, enables this signal and selects its polarity.
Compression Input Data Request, active low. This signal, when active,
indicates the ability of the CI FIFO to accept data.
Compression Input Data Acknowledge for DMA mode (DSC[3]=0).
Active low compression data input. This signal, when active, indicates
the data on D is for the compression input FIFO. Data on D is latched on
the rising edge of CLOCK when the strobe condition is met.
Compression Output Data Request, active low. When this signal is
active, it indicates the ability of the CO FIFO to transmit data.
Compression Output Data Acknowledge for DMA mode (DSC[3]=0).
The definition of COACKN varies with the data strobe condition in
System Configuration 1.
Compression Output End-of-Record, active low. COEORN is active
when the word currently on the output of the CO FIFO contains an Endof-Record.
Decompression Input Data Request, active low. When this signal is
active, it indicates the ability of the DI port to accept data.
Decompression Input Data Acknowledge for DMA mode (DSC[3]=0).
Active low decompression data input. When this signal is active, it
indicates the data on D is for the decompression input port. Data on D is
latched on the rising edge of CLOCK when the strobe condition is met.
Decompression Output Data Request, active low. When this signal is
active, it indicates the ability of the DO port to transmit data.
Decompression Output Data Acknowledge for DMA mode (DSC[3]=0).
The definition of DOACKN varies with the data strobe condition in
System Configuration 1.
Page 25 of 47
Advanced Hardware Architectures, Inc.
5.3
VIDEO INTERFACE
SIGNAL
VIREQN
VIACKN
VID[7:0]
VOREQN
VOACKN
VOD[7:0]
VOEORN
5.4
TYPE
O
S
I
S
I
S
O
S
I
S
O
S
O
S
VIDEO INTERFACE
DESCRIPTION
Video Input Request. Active low output indicating that the VDI port is
ready to accept another byte on VID[7:0].
Video Input Acknowledge. Active low input indicating that VID[7:0] is
being driven with a valid byte.
Video Input Data. The value on this input bus is written into StarLiteTM
when both VIREQN and VIACKN are active.
Video Output Request. Active low output indicating that the byte on
VOD[7:0] is valid.
Video Output Acknowledge. Active low input indicating that the external
system is ready to read VOD[7:0].
Video Output Data. The value on this output bus is read when both
VOREQN and VOACKN are low.
Video Output End-of-Record. Active low output indicating that the byte
on VOD[7:0] contains the last byte in a record.
SYSTEM CONTROL
SIGNAL
TYPE
CLOCK
I
RSTN
I
A
TEST
I
A
Page 26 of 47
SYSTEM CONTROL
DESCRIPTION
System Clock. This signal is connected to the clock of the
microprocessor. For AMD microprocessors, this pin is either called
MEMCLK (29030 and 29200) or SYSCLK (29000). The Intel i960Cx
calls this pin PCLK.
Power on Reset. Active low reset signal. StarLiteTM must be reset before
any DMA or microprocessor activity is attempted. RSTN should be a
minimum of 10 CLOCK periods.
Board Test mode. When TEST is high, all outputs are tristated. When
TEST is low, the chip performs normally.
PS3410C-0600
Advanced Hardware Architectures, Inc.
6.0
PINOUT
PIN DESIGNATION
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
PIN
VID[4]
VID[3]
VID[2]
VID[1]
VID[0]
INTRN
VSS
VDD
DRIVEN
SD
DOACKN
COACKN
DIACKN
CIACKN
VSS
VDD
DOREQN
COREQN
DIREQN
CIREQN
VIREQN
D[0]
VSS
VDD
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D[7]
D[8]
D[9]
D[10]
D[11]
VSS
VDD
D[12]
D[13]
D[14]
VSS
VSS
VDD
CLK
VSS
VDD
VSS
VDD
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
VSS
VDD
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
D[25]
D[26]
D[27]
D[28]
D[29]
D[30]
VDD
VSS
D[31]
VOREQN
VOEORN
VOD[0]
VOD[1]
VOD[2]
VDD
VSS
VOD[3]
VOD[4]
VOD[5]
VOD[6]
VOD[7]
COEORN
VDD
VSS
VOACKN
TEST
PA[0]
PA[1]
PA[2]
PA[3]
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
VDD
VSS
PA[4]
VDD
PROCMODE[1]
PROCMODE[0]
CSN
VDD
VSS
DIR
RSTN
PD[7]
PD[6]
PD[5]
VDD
VSS
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]
VDD
VSS
RDYN
VIACKN
VID[7]
VID[6]
VID[5]
VDD
VSS
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
PS3410C-0600
Page 27 of 47
Advanced Hardware Architectures, Inc.
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PA3
PA2
PA1
PA0
TEST
VOACKN
VSS
VDD
COEORN
VOD7
VOD6
VOD5
VOD4
VOD3
VSS
VDD
VOD2
VOD1
VOD0
VOEORN
VOREQN
D31
VSS
VDD
D30
D29
D28
D27
D26
D25
Figure 16: Pinout
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
AHA3410C-025 PQC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VDD
VSS
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
VDD
VSS
VDD
VSS
CLK
VDD
VSS
VSS
D14
D13
D12
VDD
VSS
D11
D10
D9
D8
D7
VID4
VID3
VID2
VID1
VID0
INTRN
VSS
VDD
DRIVEN
SD
DOACKN
COACKN
DIACKN
CIACKN
VSS
VDD
DOREQN
COREQN
DIREQN
CIREQN
VIREQN
D0
VSS
VDD
D1
D2
D3
D4
D5
D6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
VSS
PA4
VDD
PROCMODE1
PROCMODE0
CSN
VDD
VSS
DIR
RSTN
PD7
PD6
PD5
VDD
VSS
PD4
PD3
PD2
PD1
PD0
VDD
VSS
RDYN
VIACKN
VID7
VID6
VID5
VDD
VSS
Page 28 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
7.0
DC ELECTRICAL SPECIFICATIONS
7.1
OPERATING CONDITIONS
SYMBOL
Vdd
Idd
Idd
Idd
Ta
Vil
Vih
Ii
Vol
Voh
Voh
Iol
Ioh
Ioz
Ioz
Cin
Cout
Cio
Comax
OPERATING CONDITIONS
PARAMETER
MIN
Supply voltage
Supply current (active)
Supply current (standby)
Supply current (low power)
Ambient temperature
Input low voltage
Input high voltage
Input leakage current
Output low voltage (Iol=-4mA)
Output high voltage (Ioh=4mA)
Output high voltage (Ioh=100µA)
Output low current
Output high current
Output leakage current
High impedance leakage current
Input capacitance
Output capacitance
Input/Output capacitance
Maximum capacitance load for all
signals (including self loading)
4.75
0
Vss-0.5
2.0
-10
MAX
UNITS
5.25
300
26
1
70
0.8
Vdd+0.5
10
0.4
4
-4
10
10
5
7
7
V
mA
mA
mA
°C
V
V
µA
V
V
V
mA
mA
µA
µA
pF
pF
pF
50
pF
2.4
Vdd-0.8
-10
-10
NOTES
1
2
3
5
5
5
4
Notes:
1)
Dynamic current (Iout=0mA) - see Figure 17
2)
Dynamic current; no data transfers
3)
Static current (clock high)
4)
Timings referenced to this load
5)
Output AC timings referenced to Vol for high to low transitions and Voh for low to high transitions.
7.2
ABSOLUTE MAXIMUM STRESS RATINGS
ABSOLUTE MAXIMUM STRESS RATINGS
PARAMETER
MIN
MAX
SYMBOL
Tstg
Vdd
Vin
Ilp
ESD
Storage temperature
Supply voltage
Input voltage
Latch-up current
Electro-static discharge
-50
-0.5
Vss-0.5
-2,000
150
7
Vdd+0.5
100
+2,000
UNITS
NOTES
°C
V
V
mA
V
1
Notes:
1)
Human body model
PS3410C-0600
Page 29 of 47
Advanced Hardware Architectures, Inc.
Figure 17: Power vs. Data Rate at 25 MHz Operation
400
300
Idd (mA)
200
100
10
15
20
25
Rate (MB/s)
Notes:
1)
Power scales linearly with frequency at a given data rate.
2)
Iout=0 mA into 50 pF output loads.
Page 30 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
8.0
AC ELECTRICAL SPECIFICATIONS
Figure 18: Data Interface Timing
CLOCK
1
2
3
4
ACKN,
SD
Valid
D
5
6
REQN
7
8
D,
COEORN
Table 6:
Valid 0
Valid 1
Data Port Timing Requirements
NUMBER
1
2
3
4
5
6
7
8
PARAMETER
MIN
CIACKN, DIACKN, COACKN, DOACKN and SD
setup time
CIACKN, DIACKN, COACKN, DOACKN and SD
hold time
D-bus input setup time
D-bus input hold time
REQN delay (non-EOR case)
REQN hold (non-EOR case)
D-bus, COEORN output delay
D-bus, COEORN output hold
MAX
UNITS
8
ns
2
ns
8
2
ns
ns
ns
ns
ns
ns
18
2
23
2
NOTES
2
1
Notes:
1) Production test condition is 50 pF. Delay is decreased 2 ns with 25 pF load guaranteed by design or
characterization.
2) Input timings are referenced to 1.4 volts.
Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0
CLOCK
SD
ACKN
1
2
REQN
D
PS3410C-0600
EOR-1
EOR
Page 31 of 47
Advanced Hardware Architectures, Inc.
Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1
CLOCK
SD
ACKN
3
REQN
D
EOR-1
EOR
Figure 21: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0
CLOCK
SD
ACKN
4
REQN
D
EOR-1
EOR
Figure 22: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1
CLOCK
SD
ACKN
5
REQN
D
Page 32 of 47
EOR-1
EOR
PS3410C-0600
Advanced Hardware Architectures, Inc.
Table 7:
Request vs. EOR Timing
NUMBER
PARAMETER
1
MIN
ACKN, SD to REQN DSC=0-15; ERC=0
CLOCK to REQN DSC=0-3, 6-9; ERC=0
CLOCK to REQN DSC=10-15; ERC=0
CLOCK to REQN DSC=0-3, 6-15; ERC=1
CLOCK to REQN DSC=4, 5; ERC=0
CLOCK to REQN DSC=4, 5; ERC=1
2
3
4
5
MAX
UNITS
NOTES
20
21
23
18
21
18
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
Notes:
1) Production test condition is 50 pF. Delay is decreased 2 ns with 25 pF load guaranteed by design or
characterization.
Figure 23: Output Enable Timing
CLOCK
ACKN
DRIVEN
D
1
Table 8:
2
3
4
5
Output Enable Timing Requirements
NUMBER
1
2
3
4
5
PS3410C-0600
PARAMETER
DRIVEN to D valid
DRIVEN to D tristate
Signal to D valid
Signal to D tristate
CLOCK to D tristate (DSC=100, 101)
MIN
MAX
UNITS
15
10
15
10
15
ns
ns
ns
ns
ns
NOTES
Page 33 of 47
Advanced Hardware Architectures, Inc.
Figure 24: Video Input Port Timing
CLOCK
VIREQN
2
1
VIACKN
3
4
VID[7:0]
5
Table 9:
Video Input Port Timing Requirements
NUMBER
1
2
3
4
5
6
6
PARAMETER
MIN
VIREQN delay
VIREQN hold
VIACKN setup
VIACKN hold
VID setup
VID hold
MAX
UNITS
16
ns
ns
ns
ns
ns
ns
MAX
UNITS
NOTES
19
ns
ns
ns
ns
ns
ns
ns
ns
1
2
8
2
8
2
NOTES
Figure 25: Video Output Port Timing
CLOCK
VOREQN
1
2
VOACKN
3
4
VOD[7:0]
5
6
7
8
VOEORN
Table 10:
NUMBER
1
2
3
4
5
6
7
8
Video Output Port Timing Requirements
PARAMETER
VOREQN delay
VOREQN hold
VOACKN setup
VOACKN hold
VOD delay
VOD hold
VOEORN hold
VOEORN delay
MIN
4
8
3
21
3.7
3.7
21
1
1
Notes:
1) Production test condition is 50 pF. Delay is decreased 2 ns with 25 pF load guaranteed by design or
characterization.
Page 34 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
Figure 26: Microprocessor Interface Timing (PROCMODE[1]=0)
1
2
3
4
5
1
2
CLOCK
1
PA
2
1
2
4
3
4
Valid
3
CSN
7
6
8
RDYN
tristate
READ
9
9
10
10
DIR
12
PD
13
tristate
Valid
WRITE
9
10
9
10
DIR
15
14
PD
PS3410C-0600
Valid
Page 35 of 47
Advanced Hardware Architectures, Inc.
Figure 27: Microprocessor Interface Timing (PROCMODE[1]=1)
1
2
3
4
5
N
CLOCK
1
2
PA
A0
3
4
CSN
7
16
RDYN
17
READ
DIR
13
12
PD
tristate
Valid
14
WRITE
15
PD
Valid
10
9
DIR
Table 11:
NUMBER
1
2
3
4
6
7
8
9
10
12
13
14
15
16
17
Page 36 of 47
Microprocessor Interface Timing Requirements
PARAMETER
PA setup time
PA hold time
CSN setup time
CSN hold time
CSN to valid RDYN
RDYN valid delay
RDYN drive disable
DIR setup time
DIR hold time
PD valid delay
PD drive disable
PD setup time
PD hold time
CSN high to PD tristate
CSN high to RDYN high
MIN
MAX
10
3
10
3
15
20
10
10
3
20
12
10
3
10
15
UNITS
NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PS3410C-0600
Advanced Hardware Architectures, Inc.
Figure 28: Interrupt Timing
CLOCK
INTRN
1
Table 12:
2
Interrupt Timing Requirements
NUMBER
PARAMETER
1
2
MIN
INTRN delay time
INTRN hold time
MAX
UNITS
15
ns
ns
3
NOTES
Figure 29: Clock Timing
1
2
2.0V
1.4V
0.8V
CLK
3
4
5
Table 13:
Clock Timing Requirements
NUMBER
PARAMETER
1
2
3
4
5
MIN
CLOCK rise time
CLOCK fall time
CLOCK high time
CLOCK low time
CLOCK period
MAX
UNITS
5
5
ns
ns
ns
ns
ns
MAX
UNITS
NOTES
clocks
ns
ns
1
1
15
16
40
NOTES
Figure 30: Power On Reset Timing
CLOCK
2
3
RSTN
1
Table 14:
Power On Reset Timing Requirements
NUMBER
1
2
3
PARAMETER
RSTN low pulsewidth
RSTN setup to CLOCK rise
RSTN hold time
MIN
10
15
2
Notes:
1) RSTN signal can be asynchronous to the CLOCK signal. It is internally synchronized to the rising edge of
CLOCK.
PS3410C-0600
Page 37 of 47
Advanced Hardware Architectures, Inc.
9.0
PACKAGE SPECIFICATIONS
A
A2 A
L
DETAIL A
A1
D
D1
P
B
91
92
93
94
AHA3410C-025 PQC
(LCA)
E1 E
117
118
119
P
120
26 27 28 29 30
(LCB)
Package is JEDEC MO-108
Page 38 of 47
PS3410C-0600
Advanced Hardware Architectures, Inc.
PLASTIC QUAD FLAT PACK PACKAGE DIMENSIONS
(All dimensions are in mm)
NUMBER OF PIN AND SPECIFICATION DIMENSION
120
SB
NOM
30
30
3.7
0.33
3.37
31.2
28
31.2
28
0.88
0.8
0.35
SYMBOL
MIN
(LCA)
(LCB)
A
A1
A2
D
D1
E
E1
L
P
B
0.25
3.2
30.95
27.99
30.95
27.99
0.73
0.3
MAX
4.07
3.6
31.45
28.12
31.45
28.12
1.03
0.4
JEDEC Outline MO-108
10.0 ORDERING INFORMATION
10.1 AVAILABLE PARTS
PART NUMBER
AHA3410C-025 PQC
DESCRIPTION
25 MBytes/sec Simultaneous Lossless Data Compression/
Decompression Coprocessor IC
10.2 PART NUMBERING
AHA
3410
C-
025
P
Q
C
Manufacturer
Device
Number
Revision
Level
Speed
Designation
Package
Material
Package
Type
Test
Specification
Device Number:
3410
Revision Letter:
C
Package Material Codes:
P
Plastic
Package Type Codes:
Q
Quad Flat Pack
Test Specifications:
C
PS3410C-0600
Commercial 0°C to +70°C
Page 39 of 47
Advanced Hardware Architectures, Inc.
11.0 RELATED PUBLICATIONS
11.1
AHA TECHNICAL PUBLICATIONS
DOCUMENT #
PB3410C
PB3411
PB3422
PB3431
PS3411
PS3422
PS3431
ANDC12
ANDC13
ANDC14
ANDC15
ANDC16
ANDC17
GLGEN1
STARSW
PCTP127
DESCRIPTION
AHA Product Brief – AHA3410C StarLiteTM 25 MBytes/sec Simultaneous
Lossless Data Compression/Decompression Coprocessor IC
AHA Product Brief – AHA3411 StarLiteTM 33 MBytes/sec Simultaneous
Compressor/Decompressor IC
AHA Product Brief – AHA3422 StarLiteTM 16 MBytes/sec Lossless
Decompressor IC
AHA Product Brief – AHA3431 StarLite™ 40 MBytes/sec Simultaneous
Compressor/Decompressor IC, 3.3V
AHA Product Specification – AHA3411 StarLiteTM 33 MBytes/sec Simultaneous
Compressor/Decompressor IC
AHA Product Specification – AHA3422 StarLiteTM 16 MBytes/sec Lossless
Decompressor IC
AHA Product Specification – AHA3431 StarLiteTM 40 MBytes/sec Simultaneous
Compressor/Decompressor IC, 3.3V
AHA Application Note – AHA3410 StarLiteTM Designer’s Guide
AHA Application Note – Compression Performance on Bitonal Images
AHA Application Note – StarLiteTM Evaluation Software
AHA Application Note – ENCODEB2 Compression Algorithm Description
AHA Application Note – Designer’s Guide for StarLiteTM Family Products:
AHA3411, AHA3422 and AHA3431
AHA Application Note – StarLiteTM Compression on Continuous Tone Images
General Glossary of Terms
StarLiteTM Evaluation Software (WindowsTM)
T. Summers, “Applying Compression/Decompression in High-Performance
Printers and Copiers”, Conference Proceeding: The 1995 Silicon Valley Personal
Computer Design Conference and Exposition
T. Summers, “Compression Technologies in Printers”, A paper presentation at
Seybold Conference, 1995
* Evaluation Software is also available for UNIX operating system, upon request.
11.2
OTHER TECHNICAL PUBLICATIONS
DOCUMENT #
7th Edition, 1995
6th Edition, 1995
1996 Edition
Page 40 of 47
DESCRIPTION
AMD’s Fusion29K® Catalog
Intel’s Solutions 960® Catalog
Motorola’s 68K & ColdFIRE® Source Book: High Performance
Embedded Systems
PS3410C-0600
Advanced Hardware Architectures, Inc.
APPENDIX A: ADDITIONAL TIMING DIAGRAMS FOR DMA MODE TRANSFERS
Figure A1:
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Figure A2:
D0
D1
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Figure A3:
D0
D1
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
PS3410C-0600
D0
D1
D2
D3
Page 41 of 47
Advanced Hardware Architectures, Inc.
Figure A4:
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Figure A5:
D0
D1
D2
D3
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Figure A6:
D0
D1
D2
D3
D4
D5
D6
D7
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Page 42 of 47
D0
D1
D2
D3
D4
D5
D6
D7
PS3410C-0600
Advanced Hardware Architectures, Inc.
Figure A7:
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
Figure A8:
D0
D1
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
Figure A9:
D0
D1
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
PS3410C-0600
D0
D1
D2
D3
Page 43 of 47
Advanced Hardware Architectures, Inc.
Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
D4
D5
D6
D7
Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
Page 44 of 47
D0
D1
D2
D3
D4
D5
D6
D7
PS3410C-0600
Advanced Hardware Architectures, Inc.
Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
PS3410C-0600
D0
D1
D2
D3
Page 45 of 47
Advanced Hardware Architectures, Inc.
Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
D4
D5
D6
D7
Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
Page 46 of 47
D0
D1
D2
D3
D4
D5
D6
D7
PS3410C-0600
Advanced Hardware Architectures, Inc.
Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111
CLOCK
ACKN
SD
DRIVEN
D
PS3410C-0600
D0
D1
D2
Page 47 of 47