ETC AS7C31024L-15TC

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• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil PDIP and SOJ
Socket compatible with 7C512 (64K×8)
- 400 mil SOJ
- 8mm × 20mm TSOP
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• 3.3V and 5.0V versions available
• Industrial and commercial temperature available
• Intelliwatttm low power and CPG versions available
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• Organization: 131,072 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Low power consumption available
- Active: 180 mW max (3V, 15 ns)
- Standby: 1.8 mW max, CMOS I/O
- Very low DC component in active power
• 2.0V data retention
• Equal access and cycle times
• Easy memory expansion with CE1, CE2, OE inputs
DIP, SOJ
Vcc
GND
Input buffer
512×256×8
Array
(1,048,576)
Sense amp
I/O7
Row decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
NC
A10
CE1 A16
A14
I/O7
I/O6 A12
A7
I/O5
I/O4
A6
I/O3
A5
GND
A4
I/O2
A3
I/O1
A2
I/O0
A1
A0
A0
A1
I/O0
A2
I/O1
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O2
GND
WE
OE
CE1
CE2
Control
circuit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A9
A10
A11
A12
A13
A14
A15
A16
Column decoder
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
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-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
3
3
4
5
ns
Maximum operating current
AS7C1024
175
160
120
110
mA
AS7C1024L
–
120
95
80
mA
AS7C31024
150
100
70
65
mA
AS7C31024L
–
60
50
45
mA
0.1
0.1
0.1
0.1
mA
Maximum static standby current (L)
Shaded areas contain advance information.
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The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memories (SRAM) organized as 131,072
words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for
high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems.
When CE1 is HIGH or CE2 is LOW the device enters standby mode. If inputs are still toggling, the devices will consume ISB power. If the bus
is static, then full standby power is reached (ISB1 or ISB2). The 31024L for example, is guaranteed not to exceed 0.33mW under nominal full
standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL/LVTTL-compatible, and operation is from a single 5V supply or 3.3V supply. 128Kx8 and 64Kx16
SRAMs are also available in ultra-low power Intelliwatttm versions. For Intelliwatt specifications, please see the AS7C31024LL and
AS7C31026LL datasheets respectively. The revolutionary pinout (CPG) version of the 128Kx8 may be found as AS7C1025, AS7C31025.
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Parameter
Symbol
Min
Max
Unit
Voltage on any pin relative to GND
Vt
–0.5
+7.0
V
Power dissipation
PD
–
1.0
W
Storage temperature (plastic)
Tstg
–55
+150
oC
Temperature under bias
Tbias
–10
+85
oC
DC output current
Iout
–
20
mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
7UXWKWDEOH
CE1
CE2
WE
OE
Data
Mode
H
X
X
X
High Z
Standby (ISB, ISB1)
X
L
X
X
High Z
Standby (ISB, ISB1)
L
H
H
H
High Z
Output disable
L
H
H
L
Dout
Read
L
H
L
X
Din
Write
Key: X = Don’t Care, L = LOW, H = HIGH
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Parameter
Min
Nominal
Max
Unit
VCC
4.5
5.0
5.5
V
3.3V devices
VCC
3.0
3.3
3.6
V
GND
0.0
0.0
0.0
V
VIH
2.2
–
VCC + 0.5
V
VIH
2.0
–
VCC + 0.5
V
VIL†
–0.5
–
0.8
V
AS7C1024
AS7C31024
Input voltage
†V
IL
65$0
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Supply voltage
Symbol
5V devices
min = –3.0V for pulse width less than tRC/2.
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Parameter
Symbol
Test conditions
-12
-15
-20
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Input leakage
current
| ILI |
VCC = Max,
Vin = GND to VCC
–
1
–
1
–
1
–
1
µA
Output leakage
current
| ILO |
CE1 = VIH or CE2 = VIL,
VCC = Max,
Vout = GND to VCC
–
1
–
1
–
1
–
1
µA
VOL
IOL = 8 mA, VCC = Min
–
0.4
–
0.4
–
0.4
–
0.4
V
2.4
–
2.4
–
2.4
–
2.4
–
V
Output voltage
VOH IOH =
Shaded areas contain advance information.
–4 mA, VCC = Min
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Parameter
Symbol
Operating
power supply
current
ICC
CE1 = VIL, CE2 = VIH,
f = fmax, Iout = 0 mA
L
ISB
CE1 = VIH or CE2 = VIL,
f = fmax, all inputs toggling
L
Standby
power supply
current
ISB1
ISB2
Test conditions
Chip disabled, f = 0,
-12
-15
-20
Min
Max
Min
Max
Min
Max
Min
Max
Unit
–
175
–
160
–
120
–
110
mA
–
–
–
120
–
95
–
80
mA
–
55
–
50
–
40
–
40
mA
–
–
–
35
–
25
–
25
mA
–
5
–
5
–
5
–
5
mA
Vin ≤ 0.2V or Vin ≥ VCC–0.2V
L
–
–
–
0.5
–
0.5
–
0.5
mA
Chip disabled, f = 0,tA = 25°C
L
–
–
–
0.1
–
0.1
–
0.1
mA
Vin ≤ 0.2V or Vin ≥ VCC–0.2V,
Shaded areas contain advance information.
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Parameter
Symbol
Operating
power supply
current
Standby
power supply
current
Test conditions
ICC
CE1 = VIL, CE2 = VIH,
f = fmax, Iout = 0 mA
L
ISB
CE1 = VIH or CE2 = VIL,
f = fmax
L
ISB1
ISB2
-12
Min Max
Chip disabled, f = 0,
-15
-20
Min
Max
Min
Max
Min
Max
Unit
–
150
–
100
–
70
–
65
mA
–
–
–
60
–
50
–
45
mA
–
55
–
50
–
40
–
40
mA
–
–
–
35
–
25
–
25
mA
–
5
–
5
–
5
–
5
mA
Vin ≤ 0.2V or Vin ≥ VCC–0.2V
L
–
–
–
0.5
–
0.5
–
0.5
mA
Chip disabled, f = 0,tA = 25C
L
–
–
–
0.1
–
0.1
–
0.1
mA
Vin ≤ 0.2V or Vin ≥ VCC–0.2V,
Shaded areas contain advance information.
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Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CE1, CE2, WE, OE
Vin = 0V
5
pF
I/O capacitance
CI/O
I/O
Vin = Vout = 0V
7
pF
5HDGF\FOH3,9,12
-10
Parameter
Symbol
Min
Read cycle time
tRC
Address access time
tAA
Chip enable (CE1) access time
-12
Max
Min
10
–
–
10
tACE1
–
Chip enable (CE2) access time
tACE2
Output enable (OE) access time
-15
Max
Min
12
–
–
12
10
–
–
10
tOE
–
Output hold from address change
tOH
CE1 LOW to output in Low Z
tCLZ1
CE2 HIGH to output in Low Z
-20
Max
Min
15
–
20
–
ns
–
15
–
20
ns
3
12
–
15
–
20
ns
3, 12
–
12
–
15
–
20
ns
3, 12
3
–
3
–
4
–
5
ns
2
–
3
–
3
–
3
–
ns
5
3
–
3
–
3
–
3
–
ns
4, 5, 12
tCLZ2
3
–
3
–
3
–
3
–
ns
4, 5, 12
CE1 HIGH to output in High Z
tCHZ1
–
3
–
3
–
4
–
5
ns
4, 5, 12
CE2 LOW to output in High Z
tCHZ2
–
3
–
3
–
4
–
5
ns
4, 5, 12
OE LOW to output in Low Z
tOLZ
0
–
0
–
0
–
0
–
ns
4, 5
OE HIGH to output in High Z
tOHZ
–
3
–
3
–
4
–
5
ns
4, 5
Power up time
tPU
0
–
0
–
0
–
0
–
ns
4, 5, 12
Power down time
tPD
–
10
–
12
–
15
–
20
ns
4, 5, 12
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Max
Unit
Notes
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Rising input
Falling input
Undefined output/don’t care
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tRC
Address
tAA
tO H
Dout
Data valid
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tRC1
CE1
CE2
tOE
OE
Dout
Current
supply
',' % tOHZ
tCHZ1, tCHZ2
tOLZ
tACE1, tACE2
tCLZ1, tCLZ2
tPU
D ata v alid
tPD
50%
50%
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ICC
ISB
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-10
-12
-15
-20
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Write cycle time
tWC
10
–
12
–
15
–
20
–
ns
Chip enable (CE1) to write end
tCW1
9
–
10
–
12
–
12
–
ns
12
Chip enable (CE2) to write end
tCW2
9
–
10
–
12
–
12
–
ns
12
Address setup to write end
tAW
9
–
10
–
12
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
0
–
ns
Write pulse width
tWP
7
–
8
–
9
–
12
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
0
–
ns
Data valid to write end
tDW
6
–
6
–
9
–
10
–
ns
Data hold time
12
tDH
0
–
0
–
0
–
0
–
ns
4, 5
Write enable to output in High Z tWZ
–
5
–
5
–
5
–
5
ns
4, 5
Output active from write end
3
–
3
–
3
–
3
–
ns
4, 5
tOW
Shaded areas contain advance information.
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tWC
tAW
tAH
Address
tWP
WE
tAS
tDW
Din
tDH
Data valid
tWZ
tOW
Dout
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tAW
tWC
tAH
Address
tAS
tCW1, tCW2
CE1
CE2
tWP
WE
tWZ
Din
tDW
tDH
Data valid
Dout
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Symbol
VCC for data retention
VDR
Data retention current
ICCDR
Chip deselect to data retention time
tCDR
Operation recovery time
tR
Input leakage current
| ILI |
Test conditions
Min
Max
Unit
VCC = 2.0V
2.0
–
V
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V
–
500 (100 L) µA
0
–
ns
Vin ≥ VCC–0.2V or
Vin ≤ 0.2V
tRC
–
ns
–
1
µA
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Parameter
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Data retention mode
VCC
VDR ≥ 2.0V
4.5V or 2.7V
4.5V or 2.7V
tCDR
VDR
VIH
CE
tR
VIH
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– 5V output load: see Figure B,
except as noted see Figure C.
– 3.3V output load: see Figure D,
except as noted see Figure E.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 5 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
Thevenin equivalent:
168Ω
Dout
+1.728V
+5V
+5V
480Ω
+3.0V
GND
90%
10%
Dout
255Ω
90%
10%
30 pF*
GND
Figure B: Output load
Figure A: Input waveform
480Ω
Dout
255Ω
+3.3V
320Ω
30 pF*
GND
Figure D: Output load
',' % 320Ω
Dout
350Ω
5 pF*
*including scope
and jig capacitance
GND
Figure C: Output load for tCLZ, tCHZ, tOLZ, tOHZ, tOW
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*including scope
and jig capacitance
GND
Figure C: Output load for tCLZ, tCHZ, tOLZ, tOHZ, tOW
+3.3V
Dout
350Ω
5 pF*
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1.4
0.8
0.6
0.4
4.5
5.0
5.5
Supply voltage (V)
Normalized access time tAA
vs. supply voltage VCC
1.3
Normalized access time
0.8
0.7
4.5
5.0
5.5
Supply voltage (V)
Output source current IOH
vs. output voltage VOH
100
VCC = 5.0V
Ta = 25°C
80
60
40
20
0
0.0
1.25
2.5
3.75
Output voltage (V)
1
0.2
0.04
–10
35
80
125
Ambient temperature (°C)
-55
Normalized access time tAA
vs. ambient temperature Ta
1.4
1.0
1.0
0.9
0.8
0.8
0.6
0.4
0.2
0.7
0.0
–10
35
80
125
Ambient temperature (°C)
0
1/(2tRC)
1/tRC
Cycle frequency (MHz)
Typical access time change ∆tAA
vs. output capacitive loading
Output sink current IOL
vs. output voltage VOL
35
30
120
100
-10
35
80
125
Ambient temperature (°C)
Normalized supply current ICC
vs. cycle frequency
VCC = 5.0V
Ta = 25°C
80
60
40
25
20
15
10
5
20
0
1.25
2.5
3.75
Output voltage (V)
5.0
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5
1.1
0
0.0
5.0
25
1.2
140
120
625
1.2
0.6
–55
6.0
Output sink current (mA)
Normalized access time
Output source current (mA)
Ta = 25°C
0.9
140
0.4
0.0
–55
6.0
1.0
0.6
4.0
0.6
0.2
1.2
1.1
0.8
Normalized ICC
1.3
1.0
Change in tAA (ns)
0.2
Normalized supply current ISB1
vs. ambient temperature Ta
Normalized ISB1 (log scale)
1.0
0.0
4.0
Normalized supply current ICC, ISB
vs. ambient temperature Ta
1.2
Normalized ICC, ISB
1.2
Normalized ICC, ISB
65$0
1.4
Normalized supply current ICC, ISB
vs. supply voltage VCC
0
250
500
750
Capacitance (pF)
1000
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During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
This parameter is sampled and not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed but not tested.
WE is HIGH for read cycle.
CE1 and OE are LOW and CE2 is HIGH for read cycle.
Address valid prior to or coincident with CE transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE1 or WE must be HIGH or CE2 LOW during address transitions.
All write cycle timings are referenced from the last valid address to the first transitioning address.
CE1 and CE2 have identical timing.
This data applicable to the AS7C1024. The AS7C31024 functions similarly.
2V data retention applies to commercial temperature operating range only.
65$0
65$0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
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Package \ Access time
Plastic DIP, 300 mil
10 ns
12 ns
AS7C1024-10TJC
Plastic SOJ, 300 mil
15 ns
20 ns
New designs using PDIP are discouraged. Contact Alliance Sales for PDIP availability of limited production.
AS7C1024-12TJC
AS7C1024-15TJC
AS7C1024-20TJC
AS7C1024L-12TJC
AS7C1024L-15TJC
AS7C1024L-20TJC
AS7C31024-12TJC
AS7C31024-15TJC
AS7C31024-15TJI
AS7C31024-20TJC
AS7C31024-20TJI
AS7C31024L-12TJC
AS7C31024L-15TJC
AS7C31024L-20TJC
AS7C1024-12JC
AS7C1024-15JC
AS7C1024-15JI
AS7C1024-20JC
AS7C1024-20JI
AS7C1024L-12JC
AS7C1024L-15JC
AS7C1024L-20JC
AS7C31024-12JC
AS7C31024-15JC
AS7C31024-15JI
AS7C31024-20JC
AS7C31024-20JI
AS7C31024L-12JC
AS7C31024L-15JC
AS7C31024L-20JC
AS7C31024-10TJC
AS7C1024-10JC
Plastic SOJ, 400 mil
AS7C31024-10JC
TSOP 8×20
AS7C1024-12TC
AS7C1024-15TC
AS7C1024-20TC
AS7C1024L-12TC
AS7C1024L-15TC
AS7C1024L-20TC
AS7C31024-12TC
AS7C31024-15TC
AS7C31024-20TC
AS7C31024L-12TC
AS7C31024L-15TC
AS7C31024L-20TC
Shaded areas contain advance information.
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AS7C
X
1024
X
–XX
X
X
SRAM
prefix
Blank=5V CMOS
3=3.3V CMOS
Device
number
L = low
power
Access
time
Package:TP =PDIP 300 mil T =TSOP 8×20
J =SOJ 400 mil TJ =SOJ 300 mil
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
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