ETC AT24C04AN-10SC-2.7

Features
• Write Protect Pin for Hardware Data Protection
– Utilizes Different Array Protection Compared to the AT24C02/04/08
• Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
•
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
Internally Organized 256 x 8 (2K), 512 x 8 (4K) or 1024 x 8 (8K)
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Supperssion
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate
8-byte Page (2K), 16-byte Page (4K, 8K) Write Modes
Partial Page Writes are Allowed
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3000V
Automotive Grade and Extended Temperature Devices Available
8-lead JEDEC SOIC, 8-pin PDIP, and 8-lead TSSOP Packages
2-wire Serial
EEPROM
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
Description
The AT24C02A/04A/08A provides 2048/4096/8192 bits of serial electrically erasable
and programmable read only memory (EEPROM) organized as 256/512/1024 words
of 8 bits each. The device is optimized for use in many industrial and commercial
applications where low power and low voltage operation are essential. The
AT24C02A/04A/08A is available in space saving 8-pin PDIP, 8-lead JEDEC SOIC,
and 8-lead TSSOP (AT24C02A/04A) packages and is accessed via a 2-wire serial
interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V
to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
AT24C02A
AT24C04A
AT24C08A
Pin Configurations
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
NC
No Connect
8-pin PDIP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
AT24C02A/04A/
08A
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
VCC
WP
SCL
SDA
8
7
6
5
8-lead TSSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Rev. 0976C–04/01
1
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC Output Current........................................................ 5.0 mA
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1
and A0 pins are device address inputs that are hard wired
for the AT24C02A. As many as eight 2K devices may be
addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
2
AT24C02A/04A/08A
The AT24C04A uses the A2 and A1 inputs for hard wire
addressing and a total of four 4K devices may be
addressed on a single bus system. The A0 pin is a no connect.
The AT24C08A only uses the A2 input for hardwire
addr es si ng a nd a total of two 8K de vi ces ma y be
addressed on a single bus system. The A0 and A1 pins are
no connects.
WRITE PROTECT (WP): The AT24C02A/04A/08A has a
Write Protect pin that provides hardware data protection.
The Write Protect pin allows normal read/write operations
when connected to ground (GND). When the Write Protect
AT24C02A/04A/08A
pin is connected to V CC, the write protection feature is
enabled and operates as shown in the following table.
Part of the Array Protected
WP Pin
Status
24C02A
24C04A
24C08A
At VCC
Upper Half
(1K) Array
Upper Half
(2K) Array
Full (8K)
Array
At GND
Normal Read/Write Operations
Memory Organization
AT24C02A, 2K SERIAL EEPROM: Internally organized
with 256 pages of 1-byte each, the 2K requires an 8 bit
data word address for random word addressing.
AT24C04A, 4K SERIAL EEPROM: The 4K is internally
organized with 256 pages of 2-bytes each. Random word
addressing requires a 9 bit data word address.
AT24C08A, 8K SERIAL EEPROM: The 8K is internally
organized with 4 blocks of 256 pages of 4-bytes each.
Random word addressing requires a 10 bit data word
address.
Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol
Test Condition
CI/O
CIN
Note:
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Test Condition
Max
Units
1.8
5.5
V
Supply Voltage
2.5
5.5
V
VCC3
Supply Voltage
2.7
5.5
V
VCC4
Supply Voltage
4.5
5.5
V
ICC
Supply Current VCC = 5.0V
READ at 100 kHz
0.4
1.0
mA
ICC
Supply Current VCC = 5.0V
WRITE at 100 kHz
2.0
3.0
mA
ISB1
Standby Current VCC = 1.8V
VIN = VCC or VSS
0.6
3.0
µA
ISB2
Standby Current VCC = 2.5V
VIN = VCC or VSS
1.4
4.0
µA
ISB3
Standby Current VCC = 2.7V
VIN = VCC or VSS
1.6
4.0
µA
ISB4
Standby Current VCC = 5.0V
VIN = VCC or VSS
8.0
18.0
µA
ILI
Input Leakage Current
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output Leakage Current
VOUT = VCC or VSS
0.05
3.0
µA
-0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
(1)
Min
Typ
VIL
Input Low Level
VIH
Input High Level (1)
VOL2
Output Low Level VCC = 3.0V
IOL = 2.1 mA
0.4
V
VOL1
Output Low Level VCC = 1.8V
IOL = 0.15 mA
0.2
V
Note:
1. VIL min and VIH max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
2.7-, 2.5-, 1.8-volt
Symbol
Parameter
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
tHIGH
Clock Pulse Width High
Min
Max
5.0-volt
Min
100
Max
Units
400
kHz
4.7
1.2
µs
4.0
0.6
µs
(1)
tI
Noise Suppression Time
tAA
Clock Low to Data Out Valid
0.1
tBUF
Time the bus must be free before
a new transmission can start(1)
4.7
1.2
µs
tHD.STA
Start Hold Time
4.0
0.6
µs
tSU.STA
Start Set-up Time
4.7
0.6
µs
tHD.DAT
Data In Hold Time
0
0
µs
tSU.DAT
Data In Set-up Time
200
100
ns
tR
Inputs Rise Time(1)
1.0
0.3
µs
tF
Inputs Fall Time(1)
300
300
ns
tSU.STO
Stop Set-up Time
4.7
0.6
µs
tDH
Data Out Hold Time
100
50
ns
tWR
Write Cycle Time
Endurance(1)
5.0V, 25°C, Page Mode
Note:
100
4.5
0.1
10
1M
50
ns
0.9
µs
10
1M
ms
Write
Cycles
1. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
4
AT24C02A/04A/08A
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8 bit words .
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.
STANDBY MODE: The AT24C02A/04A/08A features a low
power standby mode which is enabled: (a) upon power-up
and (b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by following these steps:(a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.
AT24C02A/04A/08A
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
8th BIT
ACK
WORD n
tWR(1)
STOP
CONDITION
Note:
1.
START
CONDITION
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the interval
clear/write cycle.
5
Data Validity
Start and Stop Definition
Output Acknowledge
6
AT24C02A/04A/08A
AT24C02A/04A/08A
Device Addressing
The 2K, 4K and 8K EEPROM devices all require an 8 bit
device address word following a start condition to enable
the chip for a read or write operation (refer to Figure 1).
The device address word consists of a mandatory one,
zero sequence for the first four most significant bits as
shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits
for the 2K EEPROM. These 3 bits must compare to their
corresponding hard-wired input pins.
The 4K EEPROM only uses the A2 and A1 device address
bits with the third bit being a memory page address bit. The
two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with
the next 2 bits being for memory page addressing. The A2
bit must compare to its corresponding hard-wired input pin.
The A1 and A0 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zero. If a compare is not made, the chip will return
to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8 bit data
word address following the device address word and
acknowledgement. Upon receipt of this address, the
EEPROM will again respond with a zero and then clock in
the first 8 bit data word. Following receipt of the 8 bit data
word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write
sequence with a stop condition. At this time the EEPROM
enters an internally-timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and
the EEPROM will not respond until the write is complete
(refer to Figure 2).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte
page write, and the 4K and 8K devices are capable of 16byte page writes.
A page write is initiated the same as a byte write, but the
microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K)
more data words. The EEPROM will respond with a zero
after each data word received. The microcontroller must
terminate the page write sequence with a stop condition
(refer to Figure 3).
The data word address lower three (2K) or four (4K, 8K)
bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page row location. When the
word address, internally generated, reaches the page
boundary, the following byte is placed at the beginning of
the same page. If more than eight (2K) or sixteen (4K, 8K)
data words are transmitted to the EEPROM, the data word
address will “roll over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed
write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves
sending a start condition followed by the device address
word. The read/write bit is representative of the operation
desired. Only if the internal write cycle has completed will
the EEPROM respond with a zero allowing the read or
write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to one. There are three read
operations: current address read, random address read
and sequential read.
CURRENT ADDRESS READ: The internal data word
address counter maintains the last address accessed during the last read or write operation, incremented by one.
This address stays valid between operations as long as the
chip power is maintained. The address “roll over” during
read is from the last byte of the last memory page to the
first byte of the first page. The address “roll over” during
write is from the last byte of the current page to the first
byte of the same page.
Once the device address with the read/write select bit set
to one is clocked in and acknowledged by the EEPROM,
the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but
does generate a following stop condition (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte
write sequence to load in the data word address. Once the
device address word and data word address are clocked in
and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller
now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM
acknowledges the device address and serially clocks out
the data word. The microcontroller does not respond with a
zero but does generate a following stop condition (refer to
Figure 5).
SEQUENTIAL READ: Sequential reads are initiated by
either a current address read or a random address read.
After the microcontroller receives a data word, it responds
7
with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word
address and serially clock out sequential data words. When
the memory address limit is reached, the data word
address will “roll over” and the sequential read will continue. The sequential read operation is terminated when
the microcontroller does not respond with a zero but does
generate a following stop condition (refer to Figure 6).
Figure 1. Device Address
2K
1
0
1
0
A2 A1 A0 R/W
LSB
MSB
4K
1
0
1
0
A2 A1 P0 R/W
8K
1
0
1
0
A2 P 1 P0 R/W
Figure 2. Byte Write
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E
WORD ADDRESS
S
T
O
P
DATA
SDA LINE
M
S
B
L R A
S / C
BW K
M
S
B
L
S
B
A
C
K
A
C
K
Figure 3. Page Write
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E WORD ADDRESS (n)
DATA (n)
DATA (n + 1)
S
T
O
P
DATA (n + x)
SDA LINE
M
S
B
8
L R A
S / C
BW K
AT24C02A/04A/08A
A
C
K
A
C
K
A
C
K
A
C
K
AT24C02A/04A/08A
Figure 4. Current Address Read
S
T
A
R
T
DEVICE
ADDRESS
R
E
A
D
S
T
O
P
SDA LINE
M
S
B
DATA
L R A
S / C
BW K
N
O
A
C
K
Figure 5. Random Read
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E
S
T
A
R
T
WORD
ADDRESS n
R
E
A
D
DEVICE
ADDRESS
S
T
O
P
SDA LINE
M
S
B
L R A
S / C
BW K
M
S
B
L A
S C
B K
M
S
B
L
S
B
A
C
K
DATA n
N
O
A
C
K
DUMMY WRITE
Figure 6. Sequential Read
9
AT24C02A Ordering Information
tWR (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
10
3000
18
3000
10
10
10
Ordering Code
Package
400
AT24C02A-10PC
AT24C02AN-10SC
AT24C02A-10TC
8P3
8S1
8T
Commercial
(0°C to 70°C)
18
400
AT24C02A-10PI
AT24C02AN-10SI
AT24C02A-10TI
8P3
8S1
8T
Industrial
(-40°C to 85°C)
1500
4
100
AT24C02A-10PC-2.7
AT24C02AN-10SC-2.7
AT24C02A-10TC-2.7
8P3
8S1
8T
Commercial
(0°C to 70°C)
1500
4
100
AT24C02A-10PI-2.7
AT24C02AN-10SI-2.7
AT24C02A-10TI-2.7
8P3
8S1
8T
Industrial
(-40°C to 85°C)
1000
4
100
AT24C02A-10PC-2.5
AT24C02AN-10SC-2.5
AT24C02A-10TC-2.5
8P3
8S1
8T
Commercial
(0°C to 70°C)
1000
4
100
AT24C02A-10PI-2.5
AT24C02AN-10SI-2.5
AT24C02A-10TI-2.5
8P3
8S1
8T
Industrial
(-40°C to 85°C)
800
3
100
AT24C02A-10PC-1.8
AT24C02AN-10SC-1.8
AT24C02A-10TC-1.8
8P3
8S1
8T
Commercial
(0°C to 70°C)
800
3
100
AT24C02A-10PI-1.8
AT24C02AN-10SI-1.8
AT24C02A-10TI-1.8
8P3
8S1
8T
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8T
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank
Standard Operation (4.5V to 5.5V)
-2.7
Low Voltage (2.7V to 5.5V)
-2.5
Low Voltage (2.5V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
10
AT24C02A/04A/08A
Operation Range
AT24C02A/04A/08A
AT24C04A Ordering Information
tWR (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
10
3000
18
3000
10
10
10
Ordering Code
Package
Operation Range
400
AT24C04A-10PC
AT24C04AN-10SC
AT24C04A-10TC
8P3
8S1
8T
Commercial
(0°C to 70°C)
18
400
AT24C04A-10PI
AT24C04AN-10SI
AT24C04A-10TI
8P3
8S1
8T
Industrial
(-40°C to 85°C)
1500
4
100
AT24C04A-10PC-2.7
AT24C04AN-10SC-2.7
AT24C04A-10TC
8P3
8S1
8T
Commercial
(0°C to 70°C)
1500
4
100
AT24C04A-10PI-2.7
AT24C04AN-10SI-2.7
AT24C04A-10TI-2.7
8P3
8S1
8T
Industrial
(-40°C to 85°C)
1000
4
100
AT24C04A-10PC-2.5
AT24C04AN-10SC-2.5
AT24C04A-10TC-2.5
8P3
8S1
8T
Commercial
(0°C to 70°C)
1000
4
100
AT24C04A-10PI-2.5
AT24C04AN-10SI-2.5
AT24C04A-10TI-2.5
8P3
8S1
8T
Industrial
(-40°C to 85°C)
800
3
100
AT24C04A-10PC-1.8
AT24C04AN-10SC-1.8
AT24C04A-10TC-1.8
8P3
8S1
8T
Commercial
(0°C to 70°C)
800
3
100
AT24C04A-10PI-1.8
AT24C04AN-10SI-1.8
AT24C04A-10TI-1.8
8P3
8S1
8T
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8T
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank
Standard Operation (4.5V to 5.5V)
-2.7
Low Voltage (2.7V to 5.5V)
-2.5
Low Voltage (2.5V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
11
AT24C08A Ordering Information
tWR (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
10
3000
18
3000
10
10
10
Ordering Code
Package
400
AT24C08A-10PC
AT24C08AN-10SC
8P3
8S1
Commercial
(0°C to 70°C)
18
400
AT24C08A-10PI
AT24C08AN-10SI
8P3
8S1
Industrial
(-40°C to 85°C)
1500
4
100
AT24C08A-10PC-2.7
AT24C08AN-10SC-2.7
8P3
8S1
Commercial
(0°C to 70°C)
1500
4
100
AT24C08A-10PI-2.7
AT24C08AN-10SI-2.7
8P3
8S1
Industrial
(-40°C to 85°C)
1000
4
100
AT24C08A-10PC-2.5
AT24C08AN-10SC-2.5
8P3
8S1
Commercial
(0°C to 70°C)
1000
4
100
AT24C08A-10PI-2.5
AT24C08AN-10SI-2.5
8P3
8S1
Industrial
(-40°C to 85°C)
800
3
100
AT24C08A-10PC-1.8
AT24C08AN-10SC-1.8
8P3
8S1
Commercial
(0°C to 70°C)
800
3
100
AT24C08A-10PI-1.8
AT24C08AN-10SI-1.8
8P3
8S1
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
Blank
Standard Operation (4.5V to 5.5V)
-2.7
Low Voltage (2.7V to 5.5V)
-2.5
Low Voltage (2.5V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
12
AT24C02A/04A/08A
Operation Range
AT24C02A/04A/08A
Packaging Information
8P3, 8-pin, 0.300" Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
8S1, 8-lead, 0.150" Wide,
Plastic Gull Wing Small Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
.013 (.330)
.400 (10.16)
.355 (9.02)
PIN
1
.280 (7.11)
.240 (6.10)
.157 (3.99)
.150 (3.81)
N1
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
.244 (6.2
.228 (5.7
.050 (1.27) BSC
.100 (2.54) BSC
.196 (4.98)
.189 (4.80)
SEATING
PLANE
.068 (1.73)
.053 (1.35)
.015 (.380) MIN
.150 (3.81)
.115 (2.92)
.022 (.559)
.014 (.356)
.070 (1.78)
.045 (1.14)
.010 (.254)
.004 (.102)
.325 (8.26)
.300 (7.62)
0
REF
15
.012 (.305)
.008 (.203)
0
REF
8
.010 (.254)
.007 (.203)
.430 (10.9) MAX
050 (1 27)
8T, 8-lead, 0.170" Wide, Plastic Thin Small Outline
Package (TSSOP)
Dimensions in Millimeters and (Inches)*
PIN 1
6.50 (.256)
6.25 (.246)
0.30 (.012)
0.19 (.008)
3.10 (.122)
2.90 (.114)
1.05 (.041)
0.80 (.033)
.65 (.026) BSC
1.20 (.047) MAX
0.15 (.006)
0.05 (.002)
4.5 (.177)
4.3 (.169)
0.20 (.008)
0.09 (.004)
0 REF
8
0.75 (.030)
0.45 (.018)
*Controlling dimension: millimeters
13
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© Atmel Corporation 2001.
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