ETC AT24C16AY1-10YI-2.7

Features
• Write Protect Pin for Hardware Data Protection
– Utilizes Different Array Protection Compared to the AT24C02/04/08/16
• Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
•
•
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
Internally Organized 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate for AT24C02A, 04A and 08A
100 kHz (1.8V) and 400 kHz (2.5V, 2.7V and 5V) Clock Rate for AT24C16A
8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes
Partial Page Writes are Allowed
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Automotive Grade and Extended Temperature Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP Packages
2-wire Serial
EEPROM
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
Description
The AT24C02A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as
256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low power and low voltage operation are
essential. The AT24C02A/04A/08A/16A is available in space saving 8-lead PDIP, 8lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP packages and is accessed via a 2wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
and 1.8V (1.8V to 5.5V) versions.
AT24C02A
AT24C04A
AT24C08A
AT24C16A
Pin Configurations
8-lead PDIP
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
NC
No-connect
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
VCC
WP
SCL
SDA
8
7
6
5
8-lead MAP
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
Bottom View
A0
A1
A2
GND
8-lead TSSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Rev. 0976G–SEEPR–11/02
1
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC Output Current........................................................ 5.0 mA
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that must be hard wired for the AT24C02A. As many as eight 2K devices
may be addressed on a single bus system (device addressing is discussed in detail
under the Device Addressing section).
The AT24C04A uses the A2 and A1 inputs for hard wire addressing and a total of four
4K devices may be addressed on a single bus system. The A0 pin is a no-connect.
2
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
AT24C02A/04A/08A/16A
The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are noconnects.
The AT24C16A does not use the device address pins, which limits the number of
devices on a single bus to one. The A0, A1 and A2 pins are no-connects.
WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to
V CC, the write protection feature is enabled and operates as shown in the following
table.
Part of the Array Protected
WP Pin Status
At VCC
At GND
Memory Organization
24C02A
24C04A
24C08A
24C16A
Upper Half
(1K) Array
Upper Half
(2K) Array
Full (8K)
Array
Full (16K)
Array
Normal Read/Write Operations
AT24C02A, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.
AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16
bytes each. Random word addressing requires a 9-bit data word address.
AT24C08A, 8K SERIAL EEPROM: The 8K is internally organized with 64 pages of 16
bytes each. Random word addressing requires a 10-bit data word address.
AT24C16A, 16K SERIAL EEPROM: The 16K is internally organized with 128 pages of
16 bytes each. Random word addressing requires an 11-bit data word address.
Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol
Test Condition
CI/O
CIN
Note:
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
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0976G–SEEPR–11/02
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Test Condition
Max
Units
1.8
5.5
V
Supply Voltage
2.5
5.5
V
VCC3
Supply Voltage
2.7
5.5
V
VCC4
Supply Voltage
4.5
5.5
V
ICC
Supply Current VCC = 5.0V
READ at 100 kHz
0.4
1.0
mA
ICC
Supply Current VCC = 5.0V
WRITE at 100 kHz
2.0
3.0
mA
ISB1
Standby Current VCC = 1.8V
VIN = VCC or VSS
0.6
3.0
µA
ISB2
Standby Current VCC = 2.5V
VIN = VCC or VSS
1.4
4.0
µA
ISB3
Standby Current VCC = 2.7V
VIN = VCC or VSS
1.6
4.0
µA
ISB4
Standby Current VCC = 5.0V
VIN = VCC or VSS
8.0
18.0
µA
ILI
Input Leakage Current
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output Leakage Current
VOUT = VCC or VSS
0.05
3.0
µA
-0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
(1)
Min
Typ
VIL
Input Low Level
VIH
Input High Level (1)
VOL2
Output Low Level VCC = 3.0V
IOL = 2.1 mA
0.4
V
VOL1
Output Low Level VCC = 1.8V
IOL = 0.15 mA
0.2
V
Note:
4
1. VIL min and VIH max are reference only and are not tested.
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
AT24C02A/04A/08A/16A
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
AT24C02A/
04A/08A/16A
1.8V
Symbol
Parameter
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
tHIGH
Clock Pulse Width High
Min
Max
AT2402A/04A/
08A
2.5V, 2.7V
Min
100
Max
AT24C16A
2.5V
Min
100
Max
AT24C02A/
04A/08A/16A
5.0V
Min
400
Max
Units
400
kHz
4.7
4.7
1.3
1.2
µs
4.0
4.0
0.6
0.6
µs
(1)
tI
Noise Suppression Time
tAA
Clock Low to Data Out Valid
0.1
tBUF
Time the bus must be free before
a new transmission can start(2)
4.7
4.7
1.3
1.2
µs
tHD.STA
Start Hold Time
4.0
4.0
0.6
0.6
µs
tSU.STA
Start Set-up Time
4.7
4.7
0.6
0.6
µs
tHD.DAT
Data In Hold Time
0
0
0
0
µs
tSU.DAT
Data In Set-up Time
200
200
100
100
ns
tR
Inputs Rise Time(2)
1.0
1.0
0.3
0.3
µs
tF
Inputs Fall Time(2)
300
300
300
300
ns
tSU.STO
Stop Set-up Time
4.7
4.7
0.6
0.6
µs
tDH
Data Out Hold Time
100
100
100
50
ns
tWR
Write Cycle Time
Endurance(2)
5.0V, 25°C, Page Mode
Notes:
100
4.5
100
0.1
10
1M
4.5
100
0.2
10
1M
0.9
0.1
10
1M
50
ns
0.9
µs
10
1M
ms
Write
Cycles
1. This parameter is characterized and is not 100% tested (TA = 25°C).
2. This parameter is characterized and is not 100% tested.
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0976G–SEEPR–11/02
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8 bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02A/04A/08A/16A features a low power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
6
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
AT24C02A/04A/08A/16A
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
8th BIT
ACK
WORD n
tWR(1)
STOP
CONDITION
Note:
START
CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the interval
clear/write cycle.
7
0976G–SEEPR–11/02
Data Validity
Start and Stop Definition
Output Acknowledge
8
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
AT24C02A/04A/08A/16A
Device Addressing
The 2K, 4K and 8K EEPROM devices all require an 8 bit device address word following
a start condition to enable the chip for a read or write operation (refer to Figure 1).
The device address word consists of a mandatory one, zero sequence for the first four
most significant bits as shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3
bits must compare to their corresponding hard-wired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a
memory page address bit. The two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no-connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for
memory page addressing. The A2 bit must compare to its corresponding hard-wired
input pin. The A1 and A0 pins are no-connect.
The 16K EEPROM does not use the device address pins, which limits the number of
devices on a single bus to one. The A0, A1 and A2 pins are no-connects.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the chip will return to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8 bit data word address following the
device address word and acknowledgement. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8 bit data word. Following
receipt of the 8 bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (refer to Figure 2).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and
16K devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero
after each data word received. The microcontroller must terminate the page write
sequence with a stop condition (refer to Figure 3).
The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are
not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words
are transmitted to the EEPROM, the data word address will “roll over” and previous data
will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero allowing the read or write sequence to continue.
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0976G–SEEPR–11/02
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page to the first
byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 5).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6).
Figure 1. Device Address
2K
1
0
1
0
A2
MSB
10
A1 A0 R/W
LSB
A1 P0 R/W
4K
1
0
1
0
A2
8K
1
0
1
0
A2 P 1 P0 R/W
16K
1
0
1
0
P2
P1 P0 R/W
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
AT24C02A/04A/08A/16A
Figure 2. Byte Write
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E
WORD ADDRESS
S
T
O
P
DATA
SDA LINE
M
S
B
L R A
S / C
BW K
M
S
B
L
S
B
A
C
K
A
C
K
Figure 3. Page Write
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E WORD ADDRESS (n)
DATA (n)
DATA (n + 1)
S
T
O
P
DATA (n + x)
SDA LINE
M
S
B
L R A
S / C
BW K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 4. Current Address Read
S
T
A
R
T
DEVICE
ADDRESS
R
E
A
D
S
T
O
P
SDA LINE
M
S
B
L R A
S / C
BW K
DATA
N
O
A
C
K
11
0976G–SEEPR–11/02
Figure 5. Random Read
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E
S
T
A
R
T
WORD
ADDRESS n
R
E
A
D
DEVICE
ADDRESS
S
T
O
P
SDA LINE
M
S
B
L R A
S / C
BW K
M
S
B
L A
S C
B K
M
S
B
L
S
B
A
C
K
DATA n
N
O
A
C
K
DUMMY WRITE
Figure 6. Sequential Read
12
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
AT24C02A/04A/08A/16A
AT24C02A Ordering Information
Ordering Code
Package
AT24C02A-10PI-2.7
AT24C02AN-10SI-2.7
AT24C02A-10TI-2.7
AT24C02AY1-10YI-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C02A-10PI-1.8
AT24C02AN-10SI-1.8
AT24C02A-10TI-1.8
AT24C02AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C02AN-10SE-2.7
8S1
High Grade/Extended Temperature
(-40°C to 125°C)
Note:
Operation Range
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
-2.7
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
13
0976G–SEEPR–11/02
AT24C04A Ordering Information
Ordering Code
Package
AT24C04A-10PI-2.7
AT24C04AN-10SI-2.7
AT24C04A-10TI-2.7
AT24C04AY1-10YI-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C04A-10PI-1.8
AT24C04AN-10SI-1.8
AT24C04A-10TI-1.8
AT24C04AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C04AN-10SE-2.7
8S1
High Grade/Extended Temperature
(-40°C to 125°C)
Note:
Operation Range
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
-2.7
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
14
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
AT24C02A/04A/08A/16A
AT24C08A Ordering Information
Ordering Code
Package
AT24C08A-10PI-2.7
AT24C08AN-10SI-2.7
AT24C08A-10TI-2.7
AT24C08AY1-10YI-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C08A-10PI-1.8
AT24C08AN-10SI-1.8
AT24C08A-10TI-1.8
AT24C08AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C08AN-10SE-2.7
8S1
High Grade/Extended Temperature
(-40°C to 125°C)
Note:
Operation Range
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
-2.7
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
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0976G–SEEPR–11/02
AT24C16A Ordering Information
Ordering Code
Package
AT24C16A-10PI-2.7
AT24C16AN-10SI-2.7
AT24C16A-10TI-2.7
AT24C16AY1-10YI-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C16A-10PI-1.8
AT24C16AN-10SI-1.8
AT24C16A-10TI-1.8
AT24C16AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C16AN-10SE-2.7
8S1
High Grade/Extended Temperature
(-40°C to 125°C)
Note:
Operation Range
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
-2.7
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
16
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
AT24C02A/04A/08A/16A
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
SYMBOL
MIN
NOM
A
b2
b3
b
4 PLCS
Side View
L
0.210
NOTE
2
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
e
3
3
0.100 BSC
eA
L
Notes:
MAX
0.300 BSC
0.115
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
17
0976G–SEEPR–11/02
8S1 – JEDEC SOIC
3
2
1
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
A2
C
L
SYMBOL
MIN
NOM
MAX
A
–
–
1.75
B
–
–
0.51
C
–
–
0.25
D
–
–
5.00
E
–
–
4.00
e
E
End View
NOTE
1.27 BSC
H
–
–
6.20
L
–
–
1.27
Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
R
18
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
A
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
AT24C02A/04A/08A/16A
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.40
4.50
3, 5
E
E1
e
D
A2
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
4
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
19
0976G–SEEPR–11/02
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
2
4
PIN 1 INDEX AREA
E1
D1
D
L
8
6
5
b
A1
E
7
e
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
–
–
0.90
A1
0.00
–
0.05
D
4.70
4.90
5.10
E
2.80
3.00
3.20
D1
0.85
1.00
1.15
E1
0.85
1.00
1.15
b
0.25
0.30
0.35
e
L
NOTE
0.65 TYP
0.50
0.60
0.70
7/25/02
R
20
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
DRAWING NO.
REV.
8Y1
B
AT24C02A/04A/08A/16A
0976G–SEEPR–11/02
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0976G–SEEPR–11/02
xM