Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • Medium-voltage and Standard-voltage Operation • • • • • • • – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) 3 MHz Clock Rate 64-byte Page Mode and Byte Write Operation Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection Self-timed Write Cycle (5 ms Typical) High-reliability – Endurance: 100,000 Write Cycles – Data Retention: >200 Years 8-pin PDIP, 8-pin JEDEC SOIC and 8-pin EIAJ SOIC Packages SPI Serial Automotive EEPROMs 128K (16,384 x 8) Description 256K (32,768 x 8) The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-pin PDIP (AT25128/256), 8-pin JEDEC SOIC (AT25128) and 8-pin EIAJ SOIC (AT25256) packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions. Continued AT25128 AT25256 Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect DC Don't Connect 8-pin PDIP CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 8-pin SOIC CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI Rev. 3262A–SEEPR–02/02 1 The AT25128/256 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Block Diagram 16384/32768 x 8 2 AT25128/256 3262A–SEEPR–02/02 AT25128/256 Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Symbol Test Conditions COUT CIN Note: Max Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from TA = -40°C to +125°C, VCC = +2.7V to +5.5V Symbol Parameter Max Units VCC1 Supply Voltage 2.7 5.5 V VCC2 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read 2.0 3.0 mA ICC2 Supply Current VCC = 5.0V at 2 MHz, SO = Open, Read, Write 3.0 5.0 mA ISB1 Standby Current VCC = 2.7V, CS = VCC 0.2 2.0 µA ISB2 Standby Current VCC = 5.0V, CS = VCC 2.0 5.0 µA IIL Input Leakage VIN = 0V to VCC -3.0 3.0 µA Output Leakage VIN = 0V to VCC -3.0 3.0 µA IOL VIL Test Condition Min Typ (1) Input Low-voltage -1.0 VCC x 0.3 V (1) Input High-voltage VCC x 0.7 VCC + 0.5 V 0.4 V VIH VOL1 VOH1 Note: Output Low-voltage Output High-voltage 4.5 ≤ VCC ≤ 5.5V IOL = 3.0 mA IOH = -1.6 mA VCC - 0.8 V 1. VIL and V IH max are reference only and are not tested. 3 3262A–SEEPR–02/02 AC Characteristics Applicable over recommended operating range from TA = -40°C to +125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 - 5.5 2.7 - 5.5 0 0 3.0 2.1 MHz tRI Input Rise Time 4.5 - 5.5 2.7 - 5.5 2 2 µs tFI Input Fall Time 4.5 - 5.5 2.7 - 5.5 2 2 µs tWH SCK High Time 4.5 - 5.5 2.7 - 5.5 150 200 ns tWL SCK Low Time 4.5 - 5.5 2.7 - 5.5 150 200 ns tCS CS High Time 4.5 - 5.5 2.7 - 5.5 250 250 ns tCSS CS Setup Time 4.5 - 5.5 2.7 - 5.5 100 250 ns tCSH CS Hold Time 4.5 - 5.5 2.7 - 5.5 150 250 ns tSU Data In Setup Time 4.5 - 5.5 2.7 - 5.5 30 50 ns tH Data In Hold Time 4.5 - 5.5 2.7 - 5.5 50 50 ns tHD Hold Setup Time 4.5 - 5.5 2.7 - 5.5 100 100 ns tCD Hold Hold Time 4.5 - 5.5 2.7 - 5.5 200 300 ns tV Output Valid 4.5 - 5.5 2.7 - 5.5 0 0 tHO Output Hold Time 4.5 - 5.5 2.7 - 5.5 0 0 tLZ Hold to Output Low Z 4.5 - 5.5 2.7 - 5.5 0 0 tHZ Hold to Output High Z tDIS 150 200 ns ns 100 200 ns 4.5 - 5.5 2.7 - 5.5 100 200 ns Output Disable Time 4.5 - 5.5 2.7 - 5.5 200 250 ns tWC Write Cycle Time 4.5 - 5.5 2.7 - 5.5 5 10 ms Endurance(1) 5.0V, 25°C, Page Mode Note: 4 100K Write Cycles 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. AT25128/256 3262A–SEEPR–02/02 AT25128/256 Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25128/256 always operates as a slave. TRANSMITTER/RECEIVER: The AT25128/256 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128/256, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25128/256 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128/256. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25128/256 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. 5 3262A–SEEPR–02/02 SPI Serial Interface AT25128/256 Functional Description The AT25128/256 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25128/256 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition.. Table 1. Instruction Set for the AT25128/256 6 Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array AT25128/256 3262A–SEEPR–02/02 AT25128/256 WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 2. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Table 3. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. Bit 2 (BP0) See Table 4. Bit 3 (BP1) See Table 4. Bits 4 - 6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5. Bits 0 - 7 are 1s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128/256 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 4. Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP1 BP0 AT25128 AT25256 0 0 0 None None 1(1/4) 0 1 3000 - 3FFF 6000 - 7FFF 2(1/2) 1 0 2000 - 3FFF 4000 - 7FFF 3(All) 1 1 0000 - 3FFF 0000 - 7FFF 7 3262A–SEEPR–02/02 The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low. Table 5. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable READ SEQUENCE (READ): Reading the AT25128/256 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code is transmitted via the SI line followed by the byte address to be read (Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. WRITE SEQUENCE (WRITE): In order to program the AT25128/256, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address and the data (D7 - D0) to be programmed (Refer to Table 6). Programming will start after the CS pin is brought high. (The LOW-to-High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during the WRITE programming cycle. 8 AT25128/256 3262A–SEEPR–02/02 AT25128/256 The AT25128/256 is capable of a 64-byte PAGE WRITE operation. After each byte of data is received, the six low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25128/256 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6. Address Key Address AT25128 AT25256 AN A13 - A 0 A14 - A0 Don’t Care Bits A15 - A14 A15 9 3262A–SEEPR–02/02 Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing t CS VIH CS VIL t CSH t CSS VIH t WH SCK t WL VIL tH t SU VIH SI VALID IN VIL tV VOH SO HI-Z t HO t DIS HI-Z VOL WREN Timing WRDI Timing 10 AT25128/256 3262A–SEEPR–02/02 AT25128/256 RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 7 6 5 11 12 13 14 2 1 SCK SI SO INSTRUCTION HIGH IMPEDANCE DATA OUT 4 3 0 MSB WRSR Timing READ Timing 11 3262A–SEEPR–02/02 WRITE Timing HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ SO tLZ 12 AT25128/256 3262A–SEEPR–02/02 AT25128/256 AT25128 Ordering Information tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) 5 5000 5.0 10 2000 2.0 Ordering Code Package Operation Range 3000 AT25128-10PA-5.0C AT25128N-10SA-5.0C 8P3 8S1 Automotive (-40°C to 125°C) 2100 AT25128-10PA-2.7C AT25128N-10SA-2.7C 8P3 8S1 Automotive (-40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options -5.0 Standard Device (4.5V to 5.5V) -2.7 Low-voltage (2.7V to 5.5V) 13 3262A–SEEPR–02/02 AT25256 Ordering Information tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) 5 5000 5.0 10 2000 2.0 Ordering Code Package Operation Range 3000 AT25256-10PA-5.0C AT25256W-10SA-5.0C 8P3 8S2 Automotive (-40°C to 125°C) 2100 AT25256-10PA-2.7C AT25256W-10SA-2.7C 8P3 8S2 Automotive (-40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) Options -5.0 Standard Device (4.5V to 5.5V) -2.7 Low-voltage (2.7V to 5.5V) 14 AT25128/256 3262A–SEEPR–02/02 AT25128/256 Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A MIN NOM A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 SYMBOL A b2 b3 b 4 PLCS Side View L Notes: 0.210 0.100 BSC eA 0.300 BSC 0.115 NOTE 2 3 3 e L MAX 0.130 4 0.150 2 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B 15 3262A–SEEPR–02/02 8S1 – JEDEC SOIC 3 2 1 H N Top View e B A D COMMON DIMENSIONS (Unit of Measure = mm) Side View A2 C L SYMBOL MIN NOM MAX A – – 1.75 B – – 0.51 C – – 0.25 D – – 5.00 E – – 4.00 e E End View NOTE 1.27 BSC H – – 6.20 L – – 1.27 Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 10/10/01 R 16 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. 8S1 A AT25128/256 3262A–SEEPR–02/02 AT25128/256 8S2 – EIAJ SOIC 1 H N Top View e b A2 D COMMON DIMENSIONS (Unit of Measure = mm) Side View SYMBOL MIN NOM MAX A2 1.01 1.70 4.00 A1 0.05 0.15 0.25 b 0.35 0.51 5 C 0.10 0.35 5 C A1 L E D End View 6.05 E 5.02 5.22 6.22 H 7.62 8.42 8.89 L 0.25 e Notes: 1. 2. 3. 4. 5. 5.08 NOTE 2, 3 0.80 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm. 1/9/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. 8S2 REV. A 17 3262A–SEEPR–02/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. 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