ETC ATF16V8BQL-15PI

Features
• Industry-standard Architecture
– Emulates Many 20-pin PALs®
– Low-cost Easy-to-use Software Tools
• High-speed Electrically-erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-pin Delay
• Several Power Saving Options
Device
ICC, Standby
ICC, Active
ATF16V8B
50 mA
55 mA
ATF16V8BQ
35 mA
40 mA
ATF16V8BQL
5 mA
20 mA
Highperformance
EE PLD
• CMOS and TTL Compatible Inputs and Outputs
– Input and I/O Pull-up Resistors
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Commercial, and Industrial Temperature Ranges
Dual-in-line and Surface Mount Packages in Standard Pinouts
PCI-compliant
•
•
•
•
ATF16V8B
ATF16V8BQ
ATF16V8BQL
Block Diagram
TSSOP
Function
CLK
Clock
I
Logic Inputs
I/O
Bi-directional Buffers
OE
Output Enable
VCC
+5V Supply
DIP/SOIC
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PLCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
I2
I1
I/CLK
VCC
I/O
Pin Name
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
20
19
18
17
16
15
14
13
12
11
I3
I4
I5
I6
I7
4
5
6
7
8
3
2
1
20
19
All Pinouts Top View
1
2
3
4
5
6
7
8
9
10
18
17
16
15
14
9
10
11
12
13
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
I/O
I/O
I/O
I/O
I/O
Rev. 0364I–04/01
I8
GND
I9/OE
I/O
I/O
Pin Configurations
1
Description
The ATF16V8B is a high-performance CMOS (electricallyerasable) programmable logic device (PLD) that utilizes
Atmel’s proven electrically-erasable Flash memory technology. Speeds down to 7.5 ns are offered. All speed ranges
are specified over the full 5V ± 10% range for industrial
temperature ranges, and 5V ± 5% for commercial temperature ranges.
Several low-power options allow selection of the best solution for various types of power-limited applications. Each of
these options significantly reduces total system power and
enhances system reliability.
The ATF16V8Bs incorporate a superset of the generic
architectures, which allows direct replacement of the 16R8
family and most 20-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with software, allow highly complex logic functions to be realized.
Absolute Maximum Ratings*
Temperature Under Bias.................................-55oC to +125oC
*NOTICE:
Storage Temperature ......................................-65oC to +150oC
Voltage on Any Pin with
Respect to Ground .......................................-2.0 V to +7.0 V(1)
Voltage on Input Pins
with Respect to Ground
During Programming...................................-2.0 V to +14.0 V(1)
Note:
Programming Voltage with
Respect to Ground .....................................-2.0 V to +14.0 V(1)
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
DC and AC Operating Conditions
Commercial
Operating Temperature (Ambient)
VCC Power Supply
2
ATF16V8B(QL)
o
o
Industrial
0 C - 70 C
-40oC - 85oC
5V=± 5%
5V=± 10%
ATF16V8B(QL)
DC Characteristics
Symbol
Parameter
Condition
IIL
Input or I/O Low
Leakage Current
0 ≤=VIN ≤=VIL(Max)
IIH
Input or I/O High
Leakage Current
3.5 ≤=VIN ≤=VCC
Min
Typ
Max
Units
-35
-100
µA
10
µA
Com.
55
85
mA
Ind.
55
95
mA
B-15
Com.
50
75
mA
B-15
Ind.
50
80
mA
B-25
Com.
50
75
mA
B-25
Ind.
50
80
mA
BQ-10
Com.
35
55
mA
BQL-15
Com.
5
10
mA
BQL-15
Ind.
5
15
mA
BQL-25
Com.
5
10
mA
BQL-25
Ind.
5
15
mA
Com.
60
90
mA
Ind.
60
100
mA
B-15
Com.
55
85
mA
B-15
Ind.
55
95
mA
B-25
Com.
55
85
mA
B-25
Ind.
55
95
mA
BQ-10
Com.
40
55
mA
BQL-15
Com.
20
35
mA
BQL-15
Ind.
20
40
mA
BQL-25
Com.
20
35
mA
BQL-25
Ind.
20
40
mA
-130
mA
B-7, -10
ICC
Power Supply
Current, Standby
VCC = Max,
VIN = Max,
Outputs Open
B-7, -10
ICC2
Clocked Power
Supply Current
VCC = Max,
Outputs Open,
f=15 MHz
IOS(1)
Output Short
Circuit Current
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC+0.75
V
VOL
Output High Voltage
0.5
V
VOH
Notes:
VOUT = 0.5 V
VIN=VIH or VIL,
VCC=Min
IOL = -24 mA
Com., Ind.
VIN=VIH or VIL,
2.4
IOH = -4.0 mA
VCC=Min
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. Shaded parts are obsolete with a last time buy date of 19 August 1999.
Output High Voltage
V
3
AC Waveforms(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified.
AC Characteristics(1)
-10
Symbol
Parameter
tPD
Input or Feedback to
Non-Registered Output
tCF
Clock to Feedback
tCO
Clock to Output
tS
Input or Feedback
Setup Time
tH
8 outputs switching
-25
-15
Min
Max
Min
Max
Min
Max
Units
3
10
3
15
3
25
ns
ns
1 output switching
6
2
7
8
2
10
2
10
ns
12
ns
7.5
12
15
ns
Hold Time
0
0
0
ns
tP
Clock Period
12
16
24
ns
tW
Clock Width
6
8
12
ns
fMAX
External Feedback 1/(tS+tCO)
68
45
37
MHz
Internal Feedback 1/(tS + tCF)
74
50
40
MHz
No Feedback 1/(tP)
83
62
41
MHz
tEA
Input to Output Enable —
Product Term
3
10
3
15
3
20
ns
tER
Input to Output Disable —
Product Term
2
10
2
15
2
20
ns
tPZX
OE pin to Output Enable
2
10
2
15
2
20
ns
1.5
15
1.5
20
ns
tPXZ
Note:
OE pin to Output Disable
1.5
10
1. See ordering information for valid part numbers and speed grades.
2. Shaded parts are obsolete with a last time buy date of 19 August 1999.
4
ATF16V8B(QL)
ATF16V8B(QL)
Input Test Waveforms and
Measurement Levels:
Output Test Loads:
Commercial
tR, tF < 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C(1)
CIN
COUT
Note:
Typ
Max
Units
Conditions
5
8
pF
VIN = 0 V
6
8
pF
VOUT = 0 V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF16V8Bs are designed to reset during power-up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3. The clock must remain stable during tPR.
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Parameter
Description
Typ
Max
Units
tPR
Power-up
Reset Time
600
1,000
ns
VRST
Power-up
Reset Voltage
3.8
4.5
V
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF16V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
5
Electronic Signature Word
I/O Diagram
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. See CMOS PLD Programming Hardware
and Software Support for information on
software/programming.
Functional Logic Diagram Description
Input and I/O Pull-ups
All ATF16V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to V CC . This
ensures that all logic array inputs are at known states.
These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible drivers (see input and I/O
diagrams below).
Input Diagram
The Logic Option and Functional Diagrams describe the
ATF16V8B architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.
The ATF16V8B can be configured in one of three different
modes. Each mode makes the ATF16V8B look like a different device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The determining factors would be the usage of register versus
combinatorial outputs and dedicated outputs versus
outputs with output enable control.
The ATF16V8B universal architecture can be programmed
to emulate many 20-pin PAL devices. These architectural
subsets can be found in each of the configuration modes
described in the following pages. The user can download
the listed subset device JEDEC programming file to the
PLD programmer, and the ATF16V8B can be configured to
act like the chosen device. Check with your programmer
manufacturer for this capability.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the content of the ATF16V8B.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision, or date. The User Signature is accessible
regardless of the state of the security fuse.
Compiler Mode Selection
Registered
Complex
Simple
Auto Select
ABEL, Atmel-ABEL
P16V8R
P16V8C
P16V8AS
P16V8
CUPL
G16V8MS
LOG/iC
GAL16V8_R
OrCAD-PLD
“Registered”
PLDesigner
P16V8R
G16V8MA
(1)
Tango-PLD
G16V8R
Note:
1. Only applicable for version 3.4 or lower.
6
ATF16V8B(QL)
GAL16V8_C7
G16V8AS
(1)
G16V8
(1)
GAL16V8_C8
GAL16V8
“Complex”
“Simple”
GAL16V8A
P16V8C
P16V8C
P16V8A
G16V8C
G16V8AS
G16V8
ATF16V8B(QL)
Macrocell Configuration
Software compilers support the three different OMC
modes as different device types. Most compilers have the
ability to automatically select the device type, generally
based on the register usage and output enable (OE) usage.
Register usage on the device forces the software to choose
the registered mode. All combinatorial outputs with OE
controlled by the product term will force the software to
choose the complex mode. The software will choose the
simple mode only when all outputs are dedicated combinatorial without OE control. The different device types can be
used to override the automatic device selection by the software. For further details, refer to the compiler software
manuals.
When using compiler software to configure the device, the
user must pay special attention to the following restrictions
in each mode.
In registered mode pin 1 and pin 11 are permanently
configured as clock and output enable, respectively. These
pins cannot be configured as dedicated inputs in the
registered mode.
In simple mode all feedback paths of the output pins are
routed via the adjacent pins. In doing so, the two inner most
pins (pins 15 and 16) will not have the feedback option as
these pins are always configured as dedicated combinatorial output.
ATF16V8B Registered Mode
PAL Device Emulation/PAL Replacement. The registered
mode is used if one or more registers are required. Each
macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered
output or I/O, the output is enabled by the OE pin, and the
register is clocked by the CLK pin. Eight product terms are
allocated to the sum term. For a combinatorial output or
I/O, the output enable is controlled by a product term, and
seven product terms are allocated to the sum term. When
the macrocell is configured as an input, the output enable is
permanently disabled.
Any register usage will make the compiler select this mode.
The following registered devices can be emulated using
this mode:
In complex mode pin 1 and pin 11 become dedicated
inputs and use the feedback paths of pin 19 and pin 12
respectively. Because of this feedback path usage, pin 19
and pin 12 do not have the feedback option in this mode.
16R8
Registered Configuration for
Registered Mode(1)(2)
Combinatorial Configuration for
Registered Mode(1)(2)
Notes:
Notes:
1. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the registered
outputs. Pin 1 and Pin 11 are permanently
configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin usage
automatically.
16RP8
16R6
16RP6
16R4
16RP4
1. Pin 1 and Pin 11 are permanently configured as CLK
and OE.
2. The development software configures all the architecture control bits and checks for proper pin usage
automatically.
7
Registered Mode Logic Diagram
8
ATF16V8B(QL)
ATF16V8B(QL)
ATF16V8B Complex Mode
PAL Device Emulation/PAL Replacement. In the complex
mode, combinatorial output and I/O functions are possible.
Pins 1 and 11 are regular inputs to the array. Pins 13
through 18 have pin feedback paths back to the AND-array,
which makes full I/O capability possible. Pins 12 and 19
(outermost macrocells) are outputs only. They do not have
input capability. In this mode, each macrocell has seven
product terms going to the sum term and one product term
enabling the output.
Combinatorial applications with an OE requirement will
make the compiler select this mode. The following devices
can be emulated using this mode:
16L8
16H8
16P8
Complex Mode Option
ATF16V8B Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple
Mode, 8 product terms are allocated to the sum term. Pins
15 and 16 (center macrocells) are permanently configured
as combinatorial outputs. Other macrocells can be either
inputs or combinatorial outputs with pin feedback to the
AND-array. Pins 1 and 11 are regular inputs.
The compiler selects this mode when all outputs are combinatorial without OE control. The following simple PALs can
be emulated using this mode:
10L8
10H8
10P8
12L6
12H6
12P6
14L4
14H4
14P4
16L2
16H2
16P2
Simple Mode Option
* - Pins 15 and 16 are always enabled.
9
Complex Mode Logic Diagram
10
ATF16V8B(QL)
ATF16V8B(QL)
Simple Mode Logic Diagram
11
SUPPLY CURRENT vs. INPUT FREQUENCY
SUPPLY CURRENT vs. INPUT FREQUENCY
ATF16V8BL/BQL (VCC = 5V, TA = 25C)
ATF16V8B/BQ (VCC = 5V, TA = 25C)
75
75
ATF16V8B
ATF16V8B
I
C
C
50
m
A
25
ATF16V8BQ
0
25
50
75
100
SUPPLY CURRENT vs. SUPPLY VOLTAGE
ATF16V8B/BQ (TA = 25C)
65
ATF16V8B
55
ATF16V8BQ
45
35
25
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. SUPPLY VOLTAGE (TA = 25C)
-10
-12
I
O
H
-14
-16
-18
m
A
-20
-22
-24
4.5
4.7
4.9
5.1
5.3
SUPPLY VOLTAGE (V)
12
m
A
25
ATF16V8BQL
0
20
40
60
FREQUENCY (MHz)
FREQUENCY (MHz)
m
A
50
0
0
I
C
C
I
C
C
ATF16V8B(QL)
5.5
80
100
ATF16V8B(QL)
NORMALIZED TCO
vs. SUPPLY VOLTAGE(TA=25°C)
1.3
N
O
1.15
ATF16V8B/BQ
R
M
1
ATF16V8BQL
T
C
0.85
O
0.7
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
NORMALIZED TPD
vs. SUPPLY VOLTAGE (TA=25°C)
1.3
N
O
R
M
T
P
D
1.15
ATF16V8B/BQ
1
ATF16V8BQL
0.85
0.7
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
13
14
ATF16V8B(QL)
ATF16V8B(QL)
15
ATF16V8B Ordering Information
tPD
(ns)
tS
(ns)
tCO
(ns)
10
7.5
7
15
25
Note:
12
15
10
12
Ordering Code
Package
ATF16V8B-10JC
ATF16V8B-10PC
ATF16V8B-10SC
ATF16V8B-10XC
20J
20P3
20S
20X
Commercial
(0°C to 70°C)
ATF16V8B-10JI
ATF16V8B-10PI
ATF16V8B-10SI
ATF16V8B-10XI
20J
20P3
20S
20X
Industrial
(-40°C to 85°C)
ATF16V8B-15JC
ATF16V8B-15PC
ATF16V8B-15SC
ATF16V8B-15XC
20J
20P3
20S
20X
Commercial
(0°C to 70°C)
ATF16V8B-15JI
ATF16V8B-15PI
ATF16V8B-15SI
ATF16V8B-15XI
20J
20P3
20S
20X
Industrial
(-40°C to 85°C)
ATF16V8B-25JC
ATF16V8B-25PC
ATF16V8B-25SC
ATF16V8B-25XC
20J
20P3
20S
20X
Commercial
(0°C to 70°C)
ATF16V8B-25JI
20J
ATF16V8B-25PI
20P3
ATF16V8B-25SI
20S
ATF16V8B-25XI
20X
1. Shaded parts are obsolete with a last time buy date of 19 August 1999.
Operation Range
Industrial
(-40°C to 85°C)
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20P3
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20S
20-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)
20X
20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
16
ATF16V8B(QL)
ATF16V8B(QL)
ATF16V8BQ and ATF16V8BQL Ordering Information
tPD
(ns)
tS
(ns)
tCO
(ns)
10
7.5
15
12
25
Note:
15
Ordering Code
Package
7
ATF16V8BQ-10JC
ATF16V8BQ-10PC
ATF16V8BQ-10SC
ATF16V8BQ-10XC
20J
20P3
20S
20X
Commercial
(0°C to 70°C)
10
ATF16V8BQL-15JC
ATF16V8BQL-15PC
ATF16V8BQL-15SC
ATF16V8BQL-15XC
20J
20P3
20S
20X
Commercial
(0°C to 70°C)
ATF16V8BQL-15JI
ATF16V8BQL-15PI
ATF16V8BQL-15SI
ATF16V8BQL-15XI
20J
20P3
20S
20X
Industrial
(-40°C to 85°C)
ATF16V8BQL-25JC
ATF16V8BQL-25PC
ATF16V8BQL-25SC
ATF16V8BQL-25XC
20J
20P3
20S
20X
Commercial
(0°C to 70°C)
12
ATF16V8BQL-25JI
20J
ATF16V8BQL-25PI
20P3
ATF16V8BQL-25SI
20S
ATF16V8BQL-25XI
20X
1. Shaded parts are obsolete with a last time buy date of 11 August 1999.
Operation Range
Industrial
(-40°C to 85°C)
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20P3
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20S
20-lead, 0.300" Wide, Plastic Gull-Wing Small Outline (SOIC)
20X
20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
17
Packaging Information
20J, 20-lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AA
20P3, 20-lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AD
1.060(26.9)
.980(24.9)
PIN
1
.280(7.11)
.240(6.10)
.090(2.29)
MAX
.900(22.86) REF
.210(5.33)
MAX
.005(.127)
MIN
SEATING
PLANE
.015(.381) MIN
.150(3.81)
.115(2.92)
.022(.559)
.014(.356)
.070(1.78)
.045(1.13)
.110(2.79)
.090(2.29)
.325(8.26)
.300(7.62)
0 REF
15
.014(.356)
.008(.203)
.430(10.92) MAX
20S, 20-lead, 0.300" Wide, Plastic Gull-Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)
20X, 20-lead, 4.4 mm Wide, Plastic Thin Shrink
Small Outline (TSSOP)
Dimensions in Millimeters and (Inches)
0.020 (0.508)
0.013 (0.330)
0.30(0.012)
0.18(0.007)
0.299 (7.60) 0.420 (10.7)
0.291 (7.39) 0.393 (9.98)
PIN 1
4.48(.176) 6.50(.256)
4.30(.169) 6.25(.246)
PIN 1 ID
.050 (1.27) BSC
0.65(.0256) BSC
0.513 (13.0)
0.497 (12.6)
0.105 (2.67)
0.092 (2.34)
6.60(.260)
6.40(.252)
0.15(.006)
0.05(.002)
0.012 (0.305)
0.003 (0.076)
0
REF
8
0.18(.007)
0.09(.003)
0.013 (0.330)
0.009 (0.229)
0.035 (0.889)
0.015 (0.381)
18
1.10(0.043) MAX
ATF16V8B(QL)
0 REF
8
0.70(.028)
0.50(.020)
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