AFE FOR CCD/CIS SIGNAL PROCESSOR GENERAL DESCRIPTION BW1224L FEATURES The samsung analog front end(AFE) for CCD/CIS - 12-bit 6MSPS A/D Converter image - Integrated Triple Correlated Double signal is an integrated analog signal processor for color image signal. Sampler The AFE converts CCD/CIS output signal to digital - 3-Channel 2 MSPS Color Mode data. - Analog Programmble Gain Amplifier The AFE CDS(Correlated includes Double three-channel Sampling) circuit, PGA(Programmable Gain Amplifier), and 12-bit - Internal Voltage Reference - Wide clamp level controllability for analog to digital converter with reference generator. CIS sensor A parallel data bus provides a simple interface to - No Missing Code Guaranteed 8-bit microcontroller. - Microcontroller-Compatible Control Interface - Operation by Single 5V Supply - CMOS Low Power Dissipation APPLICATIONS KEY SPECIFICATION - Color and B/W Scanner - Digital Copiers - Resolution: 12-bit - Facsimile - Conversion Rate: 6 MHz(2 MHz*3) - General Purpose CCD/CIS imager - Supply Voltage: 5 V ± 5% - Power Dissipation: 375 mW(Typical) FUNCTIONAL BLOCK DIAGRAM RED CDS PGA REF GREEN D[11:0] CDS PGA INPUT OFFSET MUX ADC REGISTER MPU PORT BLUE CDS PGA GAIN REGISTER Ver 1.4 (Dec., 1998) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD VDDA1 AP vdda 5 V Analog Supply VSSA1 AG vssa Analog Ground VDDA2 AP vdda 5 V Analog Supply(for ADC) VSSA2 AG vssa Analog Ground(for ADC) VBB AG vbba Substarte Ground VDDD DP vddd 5 V Digital Supply VSSD DG vssd Digital Ground REFT AB piar50_bb Reference Decoupling REFB AB piar50_bb Reference Decoupling VCOM AB piar50_bb Analog Common Voltage BGR AB piar50_bb Bandgap Refernce Voltage R_VIN AI piar10_bb Analog Input; Red G_VIN AI piar10_bb Analog Input; Green B_VIN AI piar10_bb Analog Input; Blue STRTLN DI picc_bb STRTLN indicates beginning of line CDS1_CLK DI picc_bb CDS Reset Clock Pulse Input CDS2_CLK DI picc_bb CDS Data Clock Pulse Input ADCCLK DI picc_bb A/D Converter Sample Clock Input CSB DI picc_bb Chip Select; Active Low WRB DI picc_bb Write Strobe; Active Low RDB DI picc_bb Read Strobe; Active Low OEB DI picc_bb Output Enable; Active Low D[11:0]/MPU[7:0] DB poa_bb Data Inputs/Outputs AD[2:0] DI picc_bb Register Select TEST_S1, TEST_S2 DI poa_bb Channel Select in Test Mode (Set to VDDD) TEST_CTL DI picc_bb Test Mode Control (Set to VDDD) TEST_OUT AO poa_bb Test Mode Output (Floating) MCTL1, MCTL2 DI picc_bb Channel Select in External MUX Control EXT_MCTL DI picc_bb External MUX Control; Active Low DESCRIPTION I/O TYPE ABBR. -AI : Analog Input -DI : Digital Input -AO : Analog Output -DO : Analog Output -AP : Analog Power -AG : Analog Ground SEC ASIC -DP -DG -AB -DB : : : : Digital Power Digital Ground Analog Bidirectional Port Digital Bidirectional Port 2 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR CORE PIN CONFIGURATION BGR REFT VCOM REFB VSSA2 VDDA2 VSSA1 VDDA1 EXT_MCTL MCTL1,MCTL2 R_VIN bw1224l G_VIN R_VIN B_VIN D[11:0]/MPU[7:0] AD[2:0] CSB WRB RDB OEB VDDD VSSD VBB ADCCLK STRTLN CDS1_CLK CDS2_CLK ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit Supply Voltage VDD 6.5 V Analog Input Voltage AIN VSS to VDD V Digital Input Voltage CLK VSS to VDD V VOH, VOL VSS to VDD V VRT/VRB VSS to VDD V Digital Output Voltage Reference Voltage Storage Temperature Range Tstg -45 to 150 ºC Operating Temperature Range Topr 0 to 70 ºC NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) SEC ASIC 3 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR ANALOG SPECIFICATIONS(VDDA=5V, VDDD=5V, ADCCLK=6MHz, CDS1_CLK=2MHz,CDS2_CLK=2MHz, PGA Gain=1 unless otherwise noted) Characteristics Symbol Resolution Signal-to-Noise & Distortion Ratio Min Typ Max 12 SNDR Unit Bits 54 60 dB 6 6 MSPS MSPS Conversion Rate 3-Channel with CDS 1-Channel with CDS Differential Nonlinearity DNL ±0.7 ±1 LSB Integral Nonlinearity INL ±2 ±4 LSB Unipolar Offset Error 1.0 %FSR Gain Error 2.0 %FSR Anlog Input Full-Scale Input Input Capacitance Reference Top Reference Bottom Power Supply Analog Voltage Digital Voltage Analog Current Digital Current 0.06 VDDA VDDD IDDA IDDD Power Consumption Temperature Range Comment 4.0 8 3.5 1.5 Vp-p pF V V 5 5 65 10 V V mA mA 375 mW 0 70 5V±5% 5V±5% ºC DIGITAL SPECIFICATIONS(VDDA=5V, VDDD=5V, ADCCLK=6MHz, CDS1_CLK=2MHz, CDS2_CLK=2MHz, CL=20pF unless otherwise noted) Characteristics Symbol Min High Level Input Voltage VIH 3.0 Low Level Input Voltage VIL High Level Input Current IIH 10 µA Low Level Input Current IIL 10 µA High Level Output Voltage VoH Low Level Output Voltage VOL SEC ASIC Typ Max Unit Comment V 0.8 4.5 0.5 4 /20 V V IoH = 0.5mA V IoL = -0.5mA ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING SPECIFICATIONS Characteristics (VDDA=5V, VDDD=5V unless otherwise noted) Symbol Min Typ Max Unit 3-Channel Conversion Rate 500 ns 1-Channel Conversion Rate 166 ns CDSCLK1 Pulse Width tC1CLK 60 ns CDSCLK2 Pulse Width tC2CLK 70 ns CDSCLK2B Pulse Width tC2CLKB 70 ns CDSCLK1 Falling to CDSCLK2 Rising tC1C2A 5 ns CDSCLK2 Falling to CDSCLK1 Rising tC2C1A 5 ns ADCCLK Pulse Width tADCLK 70 ns CDSCLK2 Rising to ADCCLK Rising tC2ADA 70 ns CDSCLK2 Falling to ADCCLK Falling tC2ADB 5 ns ADCCLK Rising to CDS2CLK Falling tADC2A 5 ns STRTLN Rising, Falling Setup & Hold tS, tH 15 ns ADC Output Delay tADDT 20 ns Register Address Setup Time tAS 15 ns Register Address Hold Time tAH 15 ns Data Hold Time tDH 15 ns Register Chip Select Setup Time tCSS 15 ns Register Chip Select Hold Time tCSH 15 ns Register Read Pulse Width tPWR 50 ns Write Pulse Width tPWW 25 ns Register Read To Data Valid tDD 40 ns Output Enable High to Tri-State tHZ 10 ns Tri-State to Data Valid tDEV 15 ns Aperture Delay tAD 2 ns Latency for 1 Channel mode 4 ADCCLK Cycles * Aperture delay is a timing measurement between the sampling clocks and CDS. It is measured from the falling edge of the CDS2_CLK input to when the input signal is held for data conversion SEC ASIC 5 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING DIAGRAM 3-CHANNEL CDS MODE Analog Input R0,G0,B0 tC1C2A R1,G1,B1 R2,G2,B2 t C2C1A tC1CLK CDS1_CLK tC2ADA tADC2A tC2CLKB CDS2_CLK tADCLK ADCCLK tH STRTLN tS 3-CHANNEL SHA MODE Analog Input R0,G0,B0 tC2ADA R1,G1,B1 tADC2A R2,G2,B2 tC2CLKB CDS2_CLK tADCLK ADCCLK tH STRTLN tS 1-CHANNEL CDS MODE Analog Input tC1CLK tC1C2A tC2C1A CDS1_CLK tC2CLK CDS2_CLK tC2ADA tC2ADB tADCLK ADCCLK SEC ASIC 6 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING DIGRAM 1-CHANNEL SHA MODE Analog Input R0,G0,B0 R1,G1,B1 R2,G2,B2 tC2CLK CDS2_CLK tC2ADA tADCLK tC2ADB ADCCLK ADC TIMING A(n) ADC Input A(n+1) ADCCLK tADDT ADCOUT A(n-3)[11:0] A(n-2)[11:0] A(n-1)[11:0] A(n)[11:0] WRITE TIMING OEB CSB tAS tAH AD[2:0] tCSS WRB tCSH tPWW t DD tDH MPU[7:0] SEC ASIC 7 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING DIAGRAM READ(1) TIMING CSB tAS tAH AD[2:0] tCSS tPWR tCSH RDB tDH tDD MPU[7:0] 'Read(1)' means microcontroller reads MPU[7:0] CSB should keep 'High' to read. READ(2) TIMING ADCCLK tADDT D[11:0] tHZ tDEV OEB SEC ASIC 8 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR FUNCTIONAL DESCRIPTION 1) 3-Channel Operation with CDS 4) 1-Channel SHA Operation This mode enables simultaneous sampling of a This mode enables single-channel or triple output CCD. The CCD waveforms are ac monochrome sampling. The CDS function is coupled to the VINR, VING and VINB pins where replaced with the sample and hold amplifier. they are automatically biased at an appropriate The input waveforms are either dc coupled or dc voltage using the on-chip clamp. The internal restored to the analog input pin. The input CDSs take two samples of the incoming pixel reference voltage in this mode will be defined by data; the first samples are taken during the reset clamp level control register. time while the second samples are taken during Bit2 and bit2 in configuration register select the data portion of the input pixels. When STRTLN is desired input among red, green and blue. low, the internal circuitry is reset on the next rising edge of ADCCLK; the multiplexer is MAIN BLOCK DESCRIPTION switched to red channel. 1) Programmable Gain Amplifier The analog programmable gain can 2) 3-Channel SHA Operation This mode enables simultaneous sampling of a accommodate a wide range of input voltage triple output CIS or something like that. The CDS spans. The transfer function of the PGA is as functions are replaced with the sample and follows. H(X) = 1/6*X + 5/6, hold amplifiers. The input waveforms are either dc coupled or dc restored to the VINR, VING where the range of X is 0 to 31. and VINB pins. The input reference voltage in this Thus, the minimum gain value is equal to mode will be defined by clamp level control 5/6, and the maximum gain value is equal to 6. register. The transfer function has linearity in linear scale. When STRTLN is low, the internal circuitry is The overall gain is equal to analog gain reset on the next rising edge of ADCCLK; the multiplied by digital gain. So, the multiplier multiplexer is switched to red channel. should be required in back end of AFE. 3) 1-Channel Operation with CDS This mode enables single channel or monochrome sampling. The CCD waveforms are ac coupled to the analog input pin where they are automatically biased at an appropriate voltage using the on-chip clamp. Bit2 and bit3 in configuration register select the desired input among red, green and blue. 2) REGISTER OVERVIEW The MPU port map is accessed through pins A0, A1 and A2. See MPU port map format.(next page) SEC ASIC 9 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR VDDA1 VSSA1 VDDA2 VSSA2 VDDD VSSD VBB BGR REFT VCOM REFB MCTL2 MCTL1 RED R_VIN EXT_MCTL CDS CLAMP PGA TEST_S2 + R_OFFSET[7:0] TEST_S1 R_CLAMP[2:0]; For only SHA mode REF R_GAIN[4:0] TEST_CTL TEST_OUT GREEN G_VIN 12 CDS CLAMP MUX PGA 12 ADC + D[11:0] G_OFFSET[7:0] 8 G_CLAMP[2:0]; For only SHA mode /MPU[7:0] G_GAIN[4:0] BLUE B_VIN CDS CLAMP CSB PGA + Configuration B_OFFSET[7:0] R_OFFSET[7:0] B_CLAMP[2:0]; For only SHA mode OEB Register RDB B_GAIN[4:0] R_OFFSET[7:0] Input Offset G_OFFSET[7:0] Register B_OFFSET[7:0] (R,G,B) 8 MPU PORT WRB AD[2] AD[1] R_CLAMP[2:0], R_GAIN[4:0] Gain & Clamp Level Register (R,G,B) G_CLAMP[2:0], G_GAIN[4:0] AD[0] B_CLAMP[2:0], B_GAIN[4:0] CDS1_CLK CDS2_CLK STRTLN ADCCLK BLOCK DIAGRAM Table: MPU Port Map Format A2 A1 A0 0 0 0 Configuration Register 0 0 1 Red Input Offset register 0 1 0 Green Input Offset Register 0 1 1 Blue Input Offset Register 1 0 0 Red Gain & CIS Clamp Control Register 1 0 1 Green Gain & CIS Clamp Control Register 1 1 0 Blue Gain & CIS Clamp Control Register 1 1 1 Reserved SEC ASIC Register 10 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR Configuration Register Bit 7 Bit 6 Clamp Clamp mode mode select1 select0 Bit 5 Bit 4 External Set to 0 Reference Bit 3 Bit 2 Color1 Color0 (Single (Single Channel) Channel) Bit 1 Bit 0 Single CDS Channel Enable Single Channel Color Pointer Bit3 Bit2 Color 0 0 Red 0 1 Green 1 0 Blue 1 1 Reserved Clamp Mode Selection Bit7 Bit6 Clamp Mode 0 0 Line Clamp 0 1 Pixel Clamp 1 0 No Clamp 1 1 Reserved Input Offset Register MSB Bit 7 LSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Gain & CIS Clamp Control Register MSB LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CCC2 CCC1 CCC0 PGA4 PGA3 PGA2 PGA1 PGA0 * CCCn: CIS Clamp Control n EXTERNAL MULTIPLEXER CONTROL MODE EXT_MCTL = "LOW" MCTL2 SEC ASIC MCTL1 Color 0 0 Red 0 1 Green 1 0 Blue 1 1 Reserved 11 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR INPUT COUPLING CAPACITOR OVERALL TRANSFER FUNCTION The overall transfer function can be calculated as Because of the DC offset present at the output of follows. CCD, some kind of DC restoration is required. In case of CDS enable mode, to ADCout=[(Vin+Input_Offset)* PGA_Gain]/(2*REF)*4096, simplify input level shifting, a DC decoupling capacitor is used in conjuction with the where REF is equal to (REFT-REFB) and Input _Offset means the DAC value of the input offset register. The analog offset range of the input offset register is varied between 150mV and -150 mV. The 8-bit data format for the input offset register is straight binary coding. Thus, an all 'zeros' data word corresponds to -150 mV. An all 'ones' data word corresponds to 150 mV. To maximize the dynamic range of the ADC input, T is the period of assertion. CDSCLK2 should not it is necessary to program the input offset register be asserted during clamping time. And, code must be low in line clamp mode for clamping to move the ADC code corresponding to internal input circuitry. The capacitor charging or discharging depends on the clamping time, the AFE and the analog input resistance of the output resistance of the circuit driving the coupling capacitor. The clamping time is typically (n*T), where n is the number of periods CDSCLK1 is asserted and STRTLN the black level towards operation. The analog input resistance of the AFE 'zero'. In case of processing CIS signal, 3bits of the gain is equal to 1 kΩ. The recommended input coupling capacitor is more than 0.01uF. Thus, to extend the & clamp control register clamping time, CIS clamp level. are allocated to control Like the input offset register, the time a transport motor moves the scanner carriage can be available, for example. the 3-bit data format is straight binary coding. An all 'zeros' data word corresponds to 0.1 V and an all 'ones' data word corresponds to 1.5 V. SEC ASIC 12 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR POWER-ON INITIALIZATION CALIBRATION Decide clamp level for SHA mode (Refer to next page) Set PGA gain (Input offset = 0 mV) Write to configuration register Set CDS or SHA operation Set 3 or 1 channel mode Set color pointer Set clamp mode Scan dark line Compute pixel offsets Write to PGA gain register Set to gain of one(00001) Set input offset Write to input offset register Set to 0mV(10000000) Set odd/even offset in back end YES YES Set another color Set another color NO NO Set gain/offset bus size in back end Set external pixel offset in back end Scan white line Compute pixel gains in back end YES Adjust PGA gain NO SEC ASIC 13 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR CIS CLAMP LEVEL DECISION FOR EACH INPUT *Assume that PGA gain = 1 *This flow chart is not fixed, but recommended. User can modify this algorithm. Write CIS clamp control register Set to (111) Decrease CIS clamp control register by 1 [Repeatedly, scan clamp level. Scan clamp level input NO Average ADC output] ADC output > 0 YES Scan dark line [MIN(ADC output) = Minimum value of all pixels] YES MIN(ADC output) > 204 YES MIN(ADC output) > 102 NO Increase CIS clamp control register by 1 [(100mV)/(4V) * 4096 -1 = 102] NO MIN(ADC output) > 0 NO Decrease CIS clamp control register by 1. Scan dark line YES Increase CIS clamp control register by 1 NO MIN(ADC output) > 102 YES Increase CIS clamp control register by 1 Go to calibration SEC ASIC 14 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR CORE EVALUATION GUIDE -Refer to PACKAGE CONFIGURATION(Next Page) BGR REFT VCOM REFB VSSA2 EXT_MCTL MCTL1,MCTL 2 VDDA 2 VSSA1 R_VIN VDDA G_VIN R_VIN B_VIN 1 D[11:0] bw1224l VDDD AD[2:0] CSB VSSD VBB CDS1_CLK CDS2_CLK ADCCLK WRB RDB OEB STRTLN TIMING GENERATOR MPU INTERFACE MUX DSP ASIC MUX Externally forced digital input/output SEC ASIC 15 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR PACKAGE CONFIGURATION The digital pins should be well decoupled to the analog ground plane. 50 50 50 0.1u 0.1u 10u 50 10u 0.1u 10u 10u 0.1u 0.1u 0.1u 0.01u R E F B 50 R E F T V C O M B G R V S S D V S S D V D D D V D D D S T R T L N R_VIN 0.01u C D S 1 _ C L K C D S 2 _ C L K A D C C L K O E B W R B R D B C S B AD[2] AD[1] G_VIN 50 AD[0] B_VIN MCTL2 IBIAS 0.01u 50 10u 0.1u VDDA1 EXT_MCT VDDA1 MCTL1 NC VSSA1 BW1224L VSSA1 NC VDDD TEST_CTL VBB NC TEST_S2 NC TEST_S1 NC D[11] NC D[10] SPEEDUP D[9] STBY D[8] ITEST N C V D D A 2 V D D A 2 V S S A 2 V S S A 2 D[7] V S S O V S S O V D D O V D D 0 0.1u 0.1u 10u 10u D[0] D[1] D[2] D[3] D[4] D[5] D[6] : Analog Ground : Digital Ground SEC ASIC 16 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR PACKAGE PIN DESCRIPTION PIN NO. PIN NAME I/O TYPE DESCRIPTION 1 NC AO Not Connected(Test Pin) 2 VDDA2 AP Analog Power for A/D Converter 3 VDDA2 AP Analog Power for A/D Converter 4 VSSA2 AG Analog Ground for A/D Converter 5 VSSA2 AG Analog Ground for A/D Converter 6 VSSO DG Output Buffer Ground 7 VSSO DG Output Buffer Ground 8 VDDO DP Output Buffer Power 9 VDDO DP Output Buffer Power 10 D[0]/MPU[0] DB Digital Output LSB/Register Input LSB 11 D[1]/MPU[1] DB Digital Output/Register Input 12 D[2]/MPU[2] DB Digital Output/Register Input 13 D[3]/MPU[3] DB Digital Output/Register Input 14 D[4]/MPU[4] DB Digital Output/Register Input 15 D[5]/MPU[5] DB Digital Output/Register Input 16 D[6]/MPU[6] DB Digital Output/Register Input 17 D[7]/MPU[7] DB Digital Output/Register Input MSB 18 D[8] DB Digital Output 19 D[9] DB Digital Output 20 D[10] DB Digital Output 21 D[11] DB Digital Output MSB 22 TEST_S1 DI Test Pin (Set to VDDD) 23 TEST_S2 DI Test Pin (Set to VDDD) 24 TEST_CTL DI Test Pin (Set to VDDD) 25 NC - Not Connected 26 NC - Not Connected 27 MCTL1 DI MUX Control Mode Selection 28 EXT_MCTL DI MUX Control Mode Selection 29 MCTL2 DI Color Pointer for MUX Control 30 AD[0] DI Register Selection Pin 31 AD[1] DI Register Selection Pin 32 AD[2] DI Register Selection Pin SEC ASIC 17 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR PACKAGE PIN DESCRIPTION PIN NO PIN NAME I/O TYPE DESCRIPTION 33 CSB DI Chip Selection (Active Low) 34 RDB DI Read Strobe (Active Low) 35 WRB DI Write Strobe (Active Low) 36 OEB DI Output Enable (Active Low) 37 ADCCLK DI A/D Converter Clock Input 38 CDS2_CLK DI CDS Data Clock Input 39 CDS1_CLK DI CDS Reset Clock Input 40 STRTLN DI Start Line (Active Low) 41 VDDD DP Digital Power 42 VDDD DP Digital Power 43 VSSD DG Digital Ground 44 VSSD DG Digital Ground 45 BGR AB Bandgap Reference Voltage 46 VCOM AB Reference Middle Voltage 47 REFT AB Reference Top Voltage 48 REFB AB Reference Bottom Voltage 49 R_VIN AI Red Analog Input 50 G_VIN AI Green Analog Input 51 B_VIN AI Blue Analog Input 52 IBIAS AB Current Bias Control for CDS & PGA 53 VDDA1 AP Analog Power 54 VDDA1 AP Analog Power 55 VSSA1 AG Analog Ground 56 VSSA1 AG Analog Ground 57 VBB AG Analog Ground 58 NC - Not Connected 59 NC - Not Connected 60 NC - Not Connected 61 NC - Not Connected 62 SPEEDUP AI Speed-Up Selection for A/D Converter 63 STBY AI Power Down Mode for A/D Converter 64 ITEST AB Current Bias Control for A/D Converter SEC ASIC 18 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR USER GUIDE SYSTEM CONFIGURATION It is necessary that output signal of analog front end be shading-compensated by back end logic block including subtracter and multiplier. (Shading-Compensation Block) Memory Subtracter Multiplier AFE CCD/CIS Controller (Output Bus Controls) CSB 0 0 0 0 1 1 WRB 0 1 1 1 x x RDB 1 x 0 x x x OEB 1 0 x 1 0 1 DOUT MPU Input x: Don't Care X MPU Output Z ADC Output Z X: Unknown (Not recommended) Z: High Impedance SEC ASIC 19 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR Questionnaire for Analog Core Characteristics Symbol Min Typ Max Resolution Signal-to-Noise & Distortion Ratio Unit Bits SNDR dB Conversion Rate 3-Channel with CDS 1-Channel with CDS MSPS MSPS Differential Nonlinearity DNL LSB Integral Nonlinearity INL LSB Unipolar Offset Error %FSR Gain Error %FSR Anlog Input Full-Scale Input Power Supply Analog Voltage Digital Voltage Comment Vp-p VDDA VDDD V V Power Consumption mW Temperature Range ºC - What do you want to choose as power supply voltages? For example, the analog VDD needs to be 5V. The digital VDD can be 3.3V/5V. - Which modes of AFE do you use for overall system ? (Refer to page 9) For example: 3channel operation with CDS / 3channel SHI(CIS) operation 1channel operation with CDS / 1channel SHI(CIS) operation - Would you define the gain range and input offset range ? - Could you explain external/internal pin configurations as required? - Should the bus interface be compatible with TTL ? - When STRTLN is low,the internal circuit is reset on the rising edge of ADCCLK. Which channel is multiplexer switched to on the next rising edge of ADCCLK,after STRTLN goes high? - If possible, present other requirements below. SEC ASIC 20 /20 ANALOG