CLC410 Fast Settling, Video Op Amp with Disable General Description Features The current-feedback CLC410 is a fast settling, wideband, monolithic op amp with fast disable/enable feature. Designed for low gain applications (AV = ± 1 to ± 8), the CLC410 consumes only 160mW of power (180mW max) yet provides a -3dB bandwidth of 200MHz (AV = +2) and 0.05% settling in 12ns (15ns max). Plus, the disable feature provides fast turn on (100ns) and turn off (200ns). In addition, the CLC410 offers both high performance and stability without compensation - even at a gain of +1. The CLC410 provides a simple, high performance solution for video switching and distribution applications, especially where analog buses benefit from use of the disable function to “multiplex” signals onto the bus. Differential gain/phase of 0.01%/0.01˚ provide high fidelity and the 60mA output current offers ample drive capability. The CLC410’s fast settling, low distortion, and high drive capabilities make it an ideal ADC driver. The low 160mW quiescent power consumption and very low 40mW disabled power consumption suggest use where power is critical and/or “system off” power consumption must be minimized. The CLC410 is available in several versions to meet a variety of requirements. A three letter suffix determines the version. Enhanced Solutions (Military/Aerospace) SMD Number: 5962-90600 Space level versions also available. For more information, visit http://www.national.com/mil n n n n n n n -3dB bandwidth of 200MHz 0.05% settling in 12ns Low Power, 160mW (40mW disabled) Low distortion, -60dBc at 20MHz Fast disable (200ns) Differential gain/phase: 0.01%/0.01˚ ± 1 to ± 8 closed-loop gain range Applications n n n n n n n Video switching and distribution Analog bus driving (with disable) Low power “standby” using Disable Fast, precision A/D conversion D/A current-to-voltage conversion IF processors High speed communications Enable/Disable Response DS012749-10 Connection Diagram DS012749-21 Pinout DIP & SOIC © 2001 National Semiconductor Corporation DS012749 www.national.com CLC410 Fast Settling, Video Op Amp with Disable February 2001 CLC410 Connection Diagram (Continued) DS012749-1 Non-Inverting Frequency Response Ordering Information Package Temperature Range Industrial Part Number Package Marking 8-pin plastic DIP −40˚C to +85˚C CLC410AJP CLC410AJP N08A 8-pin plastic SOIC −40˚C to +85˚C CLC410AJE CLC410AJE M08A www.national.com 2 NSC Drawing Junction Temperature Operating Temperature Range Storage Temperature Range Lead Solder Duration (+300˚C) ESD Rating (human body model) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ± 7V Supply Voltage (VCC) IOUT Output is short circuit protected to ground, but maximum reliability will be maintained if IOUT does not exceed... Common Mode Input Voltage Differential Input Voltage Disable Input Voltage (pin 8) Applied output voltage when disabled +150˚C −40˚C to +85˚C −65˚C to +150˚C 10 sec 500V Operating Ratings Thermal Resistance Package MDIP SOIC 60mA ± VCC 5V ± VCC−1V ± VCC (θJC) 65˚C/W 60˚C/W (θJA) 120˚C/W 140˚C/W Electrical Characteristics AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω; unless specified Symbol Parameter Ambient Temperature Conditions Typ CLC410AJ +25˚C −40˚C Max/Min (Note 2) +25˚C +85˚C Units VOUT < 0.5VPP 200 50 > 150 > 35 > 120 > 35 MHz VOUT < 5VPP, AV = +5 > 150 > 35 < 0.4 < 0.7 <1 <1 < 0.3 < 0.5 <1 <1 < 0.4 < 0.7 < 1.3 < 1.2 dB < 2.4 < 10 < 13 < 15 < 10 > 430 < 2.4 < 10 < 13 < 15 < 10 > 430 V/µs Frequency Domain Response SSBW -3dB Bandwidth LSBW VOUT < 0.5VPP Gain Flatness GFPL Peaking DC to 40MHz 0 GFPH Peaking > 40MHz 0 Rolloff DC to 75MHz 0.6 DC to 75MHz 0.2 0.5V Step 1.6 5V Step 6.5 2V Step 10 2V Step 12 GFR LPD MHz linear phase deviation dB dB deg Time Domain Response TRS AV = +2 700 < 2.4 < 10 < 13 < 15 < 15 > 430 AV = −2 1600 – – – V/µs Rise and Fall Time TRL TSP Settling Time to TS OS Overshoot SR Slew Rate SR1 ± 0.1% ± 0.05% 0.5V Step 0 ns ns ns ns % Distortion And Noise Response HD2 2nd Harmonic Distortion 2VPP, 20MHz −60 3rd harmonic distortion 2VPP, 20MHz −60 < −40 < −50 < −45 < −50 < −45 < −50 dBc HD3 dBc Equivalent Input Noise SNF Noise Floor > 1MHz (Note 4) −157 < −154 < −154 < −153 dBm (1Hz) INV Integrated Noise 1MHz to 200MHz (Note 4) 40 < 54 < 57 < 63 µV DG Differential Gain (Note 5) (See Plots) 0.01 0.05 0.04 0.04 % DP Differential Phase (Note 5) (See Plots) 0.01 0.1 0.02 0.02 deg Disable Time to > 50dB Attenuation at 10MHz 200 < 1000 < 1000 < 1000 ns Enable Time 100 < 200 < 200 < 200 ns Disable/Enable Performance TOFF TON DIS Voltage VDIS To Disable 1.0 0.5 0.5 0.5 V VEN To Enable 2.6 2.3 3.2 4.0 V 3 www.national.com CLC410 Absolute Maximum Ratings (Note 1) CLC410 Electrical Characteristics (Continued) AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω; unless specified Symbol Parameter Conditions Typ Max/Min (Note 2) Units Disable/Enable Performance DIS current (sourced from CLC410, see Figure 5) IDIS To Disable 200 250 250 250 µA IEN To Enable 80 60 60 60 µA 59 > 55 > 55 > 55 dB 2 < ± 8.2 < ± 40 < ± 36 < ± 200 < ± 36 < ± 200 > 45 > 45 < 18 <6 < ± 5.0 > 45 > 45 < 18 <6 < ± 9.0 < ± 40 < ± 20 < ± 100 < ± 30 < ± 100 > 45 > 45 < 18 <6 > 100 <2 < 0.2 < 100 <2 > ± 3.2 > ±2 > 100 <2 < 0.2 < 100 <2 > ± 3.2 > ±2 kΩ ± 3.5 ± 2.1 > 50 <2 < 0.2 < 100 <2 > ±3 > ± 1.2 ± 70 ± 60 > ± 30 > ± 30 > ± 50 > ± 50 > ± 50 > ± 50 mA OSD Off Isolation At 10MHz Static, DC Performance VIO Input Offset Voltage (Note 3) DVIO IBN average temperature coefficient Input Bias Current (Note 3) DIBN IBI 20 Non Inverting Average Temperature Coefficient Input Bias Current (Note 3) DIBI 10 100 Inverting Average Temperature Coefficient 10 50 PSRR Power Supply Rejection Ratio 50 CMRR Common Mode Rejection Ratio ICC Supply Current (Note 3) No Load,Quiescent 16 ISD Supply Current, Disabled No Load,Quiescent 4 50 – < ± 20 – < ± 20 – mV µV/˚C µA nA/˚C µA nA/˚C dB dB mA mA Miscellaneous Performance RIN Non-Inverting Input CIN RO Output Impedance ROD Output Impedance, Disabled COD Resistance 200 Capacitance 0.5 At DC 0.1 Resistance,at DC 200 Capacitance,at DC 0.5 VO Output Voltage Range No Load CMIR Common Mode Input Range For Rated Performance IO Output Current IO −40˚C to +85˚C −55˚C to +125˚C pF Ω kΩ pF V V mA Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C, sample at 85˚C. Note 4: Noise tests are performed from 5MHz to 200MHz. Note 5: Differential gain and phase measured at: AV = +2, Rf = 250Ω, RL = 150Ω 1VPP equivalent video signal, 0-100 IRE, 40 IREPP, 3.58 MHz,) IRE =0 volts, at 75Ω load. See text. www.national.com 4 (TA = 25˚, AV = +2, VCC = ± 5V, RL = 100Ω; Unless Specified). Non-Inverting Frequency Response Inverting Frequency Response DS012749-1 Frequency Response for Various RLS DS012749-2 Forward and Reverse Gain During Disable DS012749-3 DS012749-4 2nd and 3rd Harmonic Distortion 2-Tone, 3rd Order, Intermodulation Intercept DS012749-6 DS012749-5 5 www.national.com CLC410 Typical Performance Characteristics CLC410 Typical Performance Characteristics (TA = 25˚, AV = +2, VCC = ± 5V, RL = 100Ω; Unless Specified).. (Continued) Equivalent Input Noise CMRR and PSRR DS012749-7 Pulse Response DS012749-8 Settling Time DS012749-28 DS012749-23 Long-Term Settling Time Settling Time vs. Capacitive Load DS012749-9 DS012749-24 www.national.com 6 CLC410 Typical Performance Characteristics (TA = 25˚, AV = +2, VCC = ± 5V, RL = 100Ω; Unless Specified).. (Continued) Enable/Disable Response Differential Gain and Phase (3.58MHz) DS012749-10 DS012749-11 Differential Gain and Phase (4.43MHz) DS012749-12 Application Division DS012749-13 FIGURE 1. Recommended Non-Inverting Gain Circuit 7 www.national.com CLC410 Application Division (Continued) DS012749-14 FIGURE 2. Recommended Inverting Gain Circuit Enable/Disable Operation The CLC410 has an enable/disable feature that is useful for conserving power and for multiplexing the outputs of several amplifiers onto an analog bus (Figure 3). Disabling an amplifier while not in use reduces power supply current and the output and inverting input pins become a high impedance. DS012749-16 FIGURE 4. Pin 8, the DIS pin, can be driven from either open-collector TTL or from 5V CMOS. A logic low disables the amplifier and an internal 15kΩ pull-up resistor ensures that the amplifier is enabled if pin 8 is not connected (Figure 5). Both TTL and 5V CMOS logic are guaranteed to drive a high enough high-level output voltage (VOH) to ensure that the CLC410 is enabled. Whichever type used, “break-before-make” operation should be established when outputs of several amplifiers are connected together. This is important for avoiding large, transient currents flowing between amplifiers when two or more are simultaneously enabled. Typically, proper operation is ensured if all the amplifiers are driven from the same decoder integrated circuit because logic output rise times tend to be longer than fall times. As a result, the DS012749-15 FIGURE 3. www.national.com 8 CLC410 Application Division (Continued) amplifier being disabled will reach the 2V threshold sooner than the amplifier being enabled (see tD of Figure 4 timing diagram). DS012749-19 Open-Loop Transimpedance Gain, Z(s) Developing the non-inverting frequency response for the topology of Figure 3 yields: DS012749-17 FIGURE 5. Equivalent of (not) DIS input During disable, supply current drops to approximately 4mA and the inverting input and output pin impedances become 200kΩ\ 0.5pF each. The total impedance that a disabled amplifier and its associated feedback network presents to the analog bus is determined from Figure 6. For example, at a non-inverting gain of 1, the output impedance at video frequencies is 100kΩ\ 1pF since the 250Ω feedback resistor is a negligible impedance. Similarly, output impedance is 500Ω\ 0.5pF at a non-inverting gain of 2 (with Rf = Rg = 250Ω). (1) where LG is the loop gain defined by, (2) Equation 1 has a form identical to that for a voltage feedback amplifier with the differences occurring in the LG expression, eq.2. For an idealized treatment, set Zi = 0 which results in a very simple LG=Z(s)/Rf (Derivation of the transfer function for the case where Zi = 0 is given in Application Note AN300-1). Using the Z(s) (open-loop transimpedance gain) plot shown on the previous page and dividing by the recommended Rf = 250Ω, yields a large loop gain at DC. As a result, Equation 1 shows that the closed-loop gain at DC is very close to (1+Rf/Rg). DS012749-18 FIGURE 6. Differential Gain and Phase Plots on the preceding page illustrate the differential gain and phase performance of the CLC410 at both 3.58MHz and 4.43MHz. Application Note OA-08 presents a measurement technique for measuring the very low differential gain and phase of the CLC410. Observe that the gain and phase errors remain low even as the output loading increases, making the device attractive for driving multiple video outputs. Understanding the Loop Gain The CLC410 is a current-feedback op amp. Referring to the equivalent circuit of Figure 7, any current flowing in the inverting input is amplified to a voltage at the output through the transimpedance gain shown below. This Z(s) is analogous to the open-loop gain of a voltage feedback amplifier. DS012749-20 FIGURE 7. Current Feedback Topology At higher frequencies, the roll-off of Z(s) determines the closed-loop frequency response which, ideally, is dependent only on Rf. The specifications reported on the previous pages are therefore valid only for the specified Rf = 250Ω. Increasing Rf from 250Ω will decrease the loop gain and band width, while decreasing it will increase the loop gain possibly leading to inadequate phase margin and 9 www.national.com CLC410 Application Division DC operation. Output noise is determined similarly except that a root-sum-of-squares replaces the algebraic sum. Rs is the non-inverting pin resistance. (Continued) closed-loop peaking. Conversely, fixing Rf will hold the frequency response constant while the closed-loop gain can be adjusted using Rg. Equation 4 Output Offset VO = ± IBNx RS(1+Rf/Rg) ± The CLC410 departs from this idealized analysis to the extent that the inverting input impedance is finite. With the low quiescent power of the CLC410, Zi)50Ω leading to drop in loop gain and bandwidth at high gain settlings, as given by equation 2. The second term in Equation 2 accounts for the division in feedback current that occurs between Zi and RfiRg at the inverting node of the CLC410. This decrease in bandwidth can be circumvented as described in “Increasing Bandwidth at High Gains.” Also see “Current Feedback Amplifiers” in the National Databook for a thorough discussion of current feedback op amps. Increasing Bandwidth At High Gains Bandwidth may be increased at high closed-loop gains by adjusting Rf and Rg to make up for the losses in loop gain that occur at these high gain settlings due to current division at the inverting input. An approximate relationship may be obtained by holding the LG expression constant as the gain is changed from the design point used in the specifications (that is, Rf = 250Ω and Rg = 250Ω). For the CLC400 this gives, VIO (1+Rf/Rg) ± IBIx Rf An important observation is that for fixed Rf, offsets as referred to the input improve as the gain is increased (divide all terms by 1+Rf/Rg). A similar result is obtained for noise where noise figure improves as a gain increases. The input noise plot shown in the CLC400 datasheet applies equally as well to the CLC410. Capacitive Feedback Capacitive feedback should not be used with the CLC410 because of the potential for loop instability. See Application Note OA-7 for active filter realizations with the CLC410. Offset Adjustment Pin Pin 1 can be connected to a potentiometer as shown in Figure 1 and used to adjust the input offset of the CLC410. Full range adjustment of ± 5V on pin 1 will yield a ± 10mV input offset adjustment range. Pin 1 should always be bypassed to ground with a ceramic capacitor located close to the package for best settling performance. Printed Circuit Layout As with any high frequency device, a good PCB layout will enhance performance. Ground plane construction and good power supply bypassing close to the package are critical to achieving full performance. In the non-inverting configuration, the amplifier is sensitive to stray capacitance to ground at the inverting input. Hence, the inverting node connections should be small with minimal coupling to the ground plane. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. Parasitic or load capacitance directly on the output will introduce additional phase shift in the loop degrading the loop phase margin and leading to frequency response peaking. A small series resistor before the capacitance effectively decouples this effect. The graphs on the preceding page illustrates the required resistor value and resulting performance vs. capacitance. Precision buffed resistors (PRP8351 series from Precision Resistive Products) with low parasitic reactances were used to develop the data sheet specifications. Precision carbon composition resistors will also yield excellent results. Standard spirally-trimmed RN55D metal film resistors will work with a slight decrease in bandwidth due to their reactive nature at high frequencies. Evaluation PC boards (part no. 730013 for through-hole and 730027 for SOIC) for the CLC404 are available. (3) where AVis the non-inverting gain. Note that with AV = +2 we get the specified Rf = 250Ω, while at higher gains, a lower value gives stable performance with improved bandwidth. DC Accuracy and Noise Since the two inputs for the CLC410 are quite dissimilar, the noise and offset error performance differs somewhat from that of a standard differential input amplifier. Specifically, the inverting input current noise is much larger than the non-inverting current noise. Also the two input bias currents are physically unrelated rendering bias current cancellation through matching of the inverting and non-inverting pin resistors ineffective. In Equation 4, the output offset is the algebraic sum of the equivalent input voltage and current sources that influence www.national.com 10 CLC410 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 11 www.national.com CLC410 Fast Settling, Video Op Amp with Disable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Pin MDIP NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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