CS5124, CS5126 High Performance, Integrated Current Mode PWM Controllers The CS5124/6 is a fixed frequency current mode controller designed specifically for DC–DC converters found in the telecommunications industry. The CS5124/6 integrates many commonly required current mode power supply features and allows the power supply designer to realize substantial cost and board space savings. The product matrix is as follows: CS5124: 400 kHz w/VBIAS Pin, 195 mV first current sense threshold. CS5126: 200 kHz w/SYNC Pin, 335 mV first current sense threshold. The CS5124/6 integrates the following features: Internal Oscillator, Slope Compensation, Sleep On/Off, Undervoltage Lock Out, Thermal Shutdown, Soft Start Timer, Low Voltage Current Sense for Resistive Sensing, Second Current Threshold for Pulse by Pulse Over Current Protection, a Direct Optocoupler Interface and Leading Edge Current Blanking. The CS5124/6 has supply range of 7.7 V to 20 V and is available in 8 pin SO narrow package. 8 1 SO–8 D SUFFIX CASE 751 PIN CONNECTIONS AND MARKING DIAGRAM VCC 1 BIAS UVLO SS VCC SS A WL, L YY, Y WW, W 1 CS5126 8 5126 ALYWX UVLO SYNC CS5124 8 5124 ALYWX Features • Line UVLO Monitoring • Low Current Sense Voltage for Resistive Current Sensing • External Synchronization to Higher or Lower Frequency Oscillator (CS5126 Only) • Bias for Start Up Circuitry (CS5124 Only) • Thermal Shutdown • Sleep On/Off Pin • Soft Start Timer • Leading Edge Blanking • Direct Optocoupler Interface • 90 ns Propagation Delay • 35 ns Driver Rise and Fall Times • Sleep Mode http://onsemi.com GND GATE ISENSE VFB GND GATE ISENSE VFB = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping SO–8 95 Units/Rail CS5124XDR8 SO–8 2500 Tape & Reel CS5126XD8 SO–8 95 Units/Rail CS5126XDR8 SO–8 2500 Tape & Reel CS5124XD8 Semiconductor Components Industries, LLC, 2000 December, 2000 – Rev. 3 1 Publication Order Number: CS5124/D CS5124, CS5126 36–75VIN CTX15–14514 T1 L1 5VOUT 10 µH R2 200 k C1 0.1 µF 100 V D1 R1 510 k MBRD360CT Q1 ZVN3310A D4 C2 1.5 µF 100 V R4 10 Ω R3 47 Ω BAS16LT1 Q2 IRFR220 R5 17.4 k C4 0.47 µF 25 V VCC GND BIAS GATE R7 30.1 k R6 1.0 k R8 0.39 Ω C5 47 µF 10 V C6 U2 IS UVLO ENABLE C3 0.022 µF 0.01 µF CS5124 C9 1000 pF VFB SS C7 0.1 µF C8 1000 pF TPS5908 R9 10 k 48VRTN ISOLATED RTN Figure 1. Application Diagram ABSOLUTE MAXIMUM RATINGS* Rating Value Unit Operating Junction Temperature, TJ –40 to 135 °C Storage Temperature Range, TS –40 to 150 °C 2.0 kV 230 peak °C ESD Susceptibility (Human Body Model) Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1.) 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. ABSOLUTE MAXIMUM RATINGS PIN NAME PIN SYMBOL VMAX VMIN ISOURCE ISINK VCC Power Input VCC 20 V –0.3 V 1.0 mA 1.5 A Peak 200 mA DC Clock Synchronization Input SYNC (CS5126) 20 V –0.3 V 1.0 mA 1.0 mA VCC Clamp Output VBIAS (CS5124) 20 V –0.3 V 1.0 mA 1.0 mA UVLO Shutdown Input UVLO 6.0 V –0.3 V 1.0 mA 1.0 mA Soft Start Capacitor Input SS 6.0 V –0.3 V 1.0 mA 2.0 mA Voltage Feedback Input VFB 6.0 V –0.3 V 3.0 mA 20 mA Current Sense Input ISENSE 6.0 V –0.3 V 1.0 mA 1.0 mA Ground GROUND 0V 0V 1.5 A peak 200 mA DC 1.0 mA Gate Drive Output GATE 20 V –0.3 V 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC http://onsemi.com 2 CS5124, CS5126 ELECTRICAL CHARACTERISTICS (–40°C ≤ TJ ≤ 125°C; –40°C ≤ TA ≤ 105°C, 7.60 V ≤ VCC ≤ 20 V, UVLO = 3.0 V, ISENSE = 0 V, CV(CC) = 0.33 µF, CGATE = 1.0 nF (ESR = 10 Ω); CSS = 470 pF; CV(FB) = 100 pF, unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit – – 10 13 mA General ICC Operating – VGATE not switching ICC at VCC Low VCC = 6.0 V – 500 750 µA ICC Sleep VUVL = 1.0 V – 210 275 µA Low VCC Lockout VCC Turn–on Threshold Voltage – 7.2 7.7 8.3 V VCC Turn–off Threshold Voltage – 6.8 7.3 7.8 V VCC Hysteresis – 350 425 500 mV UVLO Sleep Threshold Voltage UVLO decreasing 1.5 1.8 2.3 V Sleep Threshold Voltage UVLO increasing – 1.88 2.45 V 35 85 150 mV Sleep Hysteresis – UVLO Turn–off Threshold Voltage Note 2. 2.3 2.45 2.6 V UVLO Turn–on Threshold Voltage Note 2. 2.50 2.63 2.76 V UVLO Hysteresis Turn–on – Turn–off (–40°C ≤ TJ ≤ 100°C) Note 2. 170 185 200 mV UVLO Hysteresis Turn–on – Turn–off (100°C ≤ TJ ≤ 125°C) Note 2. 50 185 400 mV – –1.0 – 1.0 µA 5.0 7.5 12 V UVLO Input Bias Current UVLO Clamp With UVLO sinking 1.0 mA VCC Clamp and BIAS Pin CS5124 Only. Connect an NFET as follows: BIAS = G, VCC = S, VIN = D. VCC Clamp Voltage 36 V ≤ VIN ≤ 60 V, 200 nF ≤ CSS ≤ 500 nF, R = 500 k BIAS Minimum Voltage 7.275 7.9 8.625 V Measure Voltage on BIAS with: 10 V ≤ VCC ≤ 20 V & 50 µA ≤ IBIAS ≤ 1.0 mA 1.6 2.8 4.0 V BIAS Clamp With BIAS pin sinking 1.0 mA 12 15 20 V 200 kHz Oscillator CS5126 Only Operating Frequency – 175 200 225 kHz Max Duty Cycle Clamp – 78 82.5 85 % Slope Compensation (Normal operation) – 12 18 23 mV/µs 7.0 12 16 mV/µs 1.0 2.0 3.0 V 50 120 230 kΩ Slope Compensation (Synchronized operation) Note 2. SYNC Input Threshold Voltage SYNC Input Impedance 400 kHz Oscillator – Measured with SYNC = 1.0 V & 10 V CS5124 Only Operating Frequency – 360 400 440 kHz Max Duty Cycle Clamp – 80.0 82.5 85.0 % Slope Compensation – 15 21 26 mV/µs 2. Not tested in production. Specification is guaranteed by design. http://onsemi.com 3 CS5124, CS5126 ELECTRICAL CHARACTERISTICS (continued) (–40°C ≤ TJ ≤ 125°C; –40°C ≤ TA ≤ 105°C, 7.60 V ≤ VCC ≤ 20 V, UVLO = 3.0 V, ISENSE = 0 V, CV(CC) = 0.33 µF, CGATE = 1.0 nF (ESR = 10 Ω); CSS = 470 pF; CV(FB) = 100 pF, unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Soft Start Charge Current – 7.0 10 13 µA Soft Start Discharge Current – 0.5 10.0 – mA 1.40 1.62 1.80 V Soft Start VSS Voltage when VFB Begins to Rise VFB = 300 mV Peak Soft Start Charge Voltage – 4.7 4.9 – V Valley Soft Start Discharge Voltage – 200 275 400 mV 170 195 215 mV – 250 275 315 mV ISENSE to GATE Prop. Delay 0 to 700 mV pulse into ISENSE (after blanking time) 60 90 130 ns Leading Edge Blanking Time 0 to 400 mV pulse into ISENSE 90 130 180 ns Internal Offset Note 3. – 60 – mV 300 335 360 mV – 485 525 575 mV ISENSE to GATE Prop. Delay 0 to 800 mV pulse into ISENSE (after blanking time) 60 90 130 ns Leading Edge Blanking Time 0 to 550 mV pulse into ISENSE 110 175 210 ns Internal Offset Note 3. – 125 – mV 2.9 4.3 8.1 kΩ Current Sense First Current Sense Threshold CS5124 Only At max duty cycle Second Current Sense Threshold Current Sense First Current Sense Threshold CS5126 Only At max duty cycle Second Current Sense Threshold Voltage Feedback VFB Pull–up Res. – VFB Clamp Voltage CS5124 Only 2.63 2.90 3.15 V VFB Clamp Voltage CS5126 Only 2.40 2.65 290 V 460 490 520 mV – 1.2 2.0 V VFB Fault Voltage Threshold – Output Gate Drive Maximum Sleep Pull–down Voltage VCC = 6.0 V, IOUT = 1.0 mA GATE High (AC) Series resistance < 1.0 Ω, Note 3. VCC – 1.0 VCC – 0.5 – V GATE Low (AC) Series resistance < 1.0 Ω, Note 3. – 0.0 0.5 V GATE High Clamp Voltage VCC = 20 V 11.0 13.5 16.0 V Rise Time Measure GATE rise time, 1.0 V < GATE < 9.0 V VCC = 12 V – 45 65 ns Fall TIme Measure GATE fall time, 9.0 V > GATE > 1.0 V VCC = 12 V – 25 55 ns Thermal Shutdown Thermal Shutdown Temperature Note 3. GATE low 135 150 165 °C Thermal Enable Temperature Note 3. GATE switching 100 125 150 °C Thermal Hysteresis Note 3. 15 25 35 °C 3. Not tested in production. Specification is guaranteed by design. http://onsemi.com 4 CS5124, CS5126 PACKAGE PIN DESCRIPTION PACKAGE PIN # 8 Lead SO Narrow CS5124 CS5126 PIN SYMBOL 1 1 VCC VCC Power Input Pin. 2 – BIAS VCC Clamp Output Pin. This pin will control the gate of an N–channel MOSFET that in turn regulates Vcc. This pin is internally clamped at 15 V when the IC is in sleep mode. – 3 SYNC Clock Synchronization Pin. A positive edge will terminate the current PWM cycle. Ground this pin when it is not used. 3 2 UVLO Sleep and under voltage lockout pin. A voltage greater than 1.8 V causes the chip to “wake up” however the GATE remains low. A voltage greater than 2.6 V on this pin allows the output to switch. 4 4 SS Soft Start Capacitor Pin. A capacitor placed between SS and GROUND is charged with 10 µA and discharged with 10 mA. The Soft Start capacitor controls both Soft Start time and hiccup mode frequency. 5 5 VFB Voltage Feedback Pin. The collector of an optocoupler is typically tied to this pin. This pin is pulled up internally by a 4.3 kΩ resistor to 5.0 V and is clamped internally at 2.9 V (2.65 V). If VFB is pulled > 4.0 V, the oscillator is disabled and GATE will stay high. If the VFB pin is pulled < 0.49 V, GATE will stay low. 6 6 ISENSE Current Sense Pin. This pin is connected to the current sense resistor on the primary side. If VFB is floating, the GATE will go low if ISENSE = 195 mV (335 mV). If ISENSE > 275 mV (525 mV), Soft Start will be initiated. 7 7 GATE Gate Drive Output Pin. Capable of driving a 3.0 nF load. GATE is nominally clamped to 13.5 V. 8 8 GND Ground Pin. FUNCTION http://onsemi.com 5 CS5124, CS5126 SYNC (CS5126 ONLY) VCC UVLO COMP VCC G2 – VREF = 5.0 V V 7.7 V/7.275 V TSHUT V5REF – + 10 µA 2.62 V/2.45 V VFB COMP PWM COMP + (1/5) V 490 mV 1/10 ÷ – VFB + + – (CS5124 ONLY) 4500 Ω G3 REMOTE (SLEEP) COMP BIAS V5REF G7 + V + UVLO R 85 mV/µs 170 mV/µs + 150°C/125°C + V GATE Q RESET DOMAIN – VREFOK + – S S V5REF LINE UVLO COMP G1 Q F1 ENABLE + DRIVER F3 R RAMP + VCC OSC DIS (125 mV) 60 mV + + 2ND ICOMP V 1.91 V/1.83 V SOFT START LATCH V 1000 Ω ISENSE (525 mV) 275 mV – + V F2 G5 VCC S BLANKING Q BLANK R 2.9 R SET DOMAIN LINE AMP (2.65 V) 2.90 V – + R SS COMP + V + GND SS AMP + 275 mV V + 2.0 V V5REF – + G6 – V 1.32 V + SS V Figure 2. Block Diagram THEORY OF OPERATION Powering the IC on the UVLO pin rises to between 1.8 V and 2.6 V the reference for the VCC UVLO is enabled and VCC is regulated to 8.0 V by the BIAS pin (CS5124 only), but the IC remains in a UVLO state and the output driver does not switch. When the UVLO pin exceeds 2.6 V and the VCC pin exceeds 7.7 V, the GATE pin is released from a low state and can begin switching based on the comparison of the ISENSE and VFB pins. The Soft Start capacitor begins charging from 0 V at 10 µA. As the capacitor charges, a buffered version of the capacitor voltage appears on the VFB pin and the VFB voltage begins to rise. As VFB rises the duty cycle increases until the supply comes into regulation. VCC can be powered directly from a regulated supply and requires 500 µA of start–up current. The CS5124/6 includes a line bias pin (BIAS) that can be used to control a series pass transistor for operation over a wide input voltage. The BIAS pin will control the gate voltage of an N–channel MOSFET placed between VIN and VCC to regulate VCC at 8.0 V. VCC and UVLO Pins The UVLO pin has three different modes; low power shutdown, Line UVLO, and normal operation. To illustrate how the UVLO pin works; assume that VIN, as shown in the application schematic, is ramped up starting at 0 V with the UVLO pin open. The SS and ISENSE pins also start at 0 V. While the UVLO is below 1.8 V, the IC will remain in a low current sleep mode and the BIAS pin of the CS5124 is internally clamped to a maximum of 15 V. When the voltage Soft Start Soft Start is accomplished by clamping the VFB pin 1.32 V below the SS pin during normal start up and during restart after a fault condition. When the CS5124/6 starts, the Soft http://onsemi.com 6 CS5124, CS5126 Start capacitor is charged from a 10 µA source from 0 V to 4.9 V. The VFB pin follows the Soft Start pin offset by –1.32 V until the supply comes into regulation or until the Soft Start error amp is clamped at 2.9 V (2.65 V for the CS5126). During fault conditions the Soft Start capacitor is discharged at 10 mA. Second Threshold Comparator Since the maximum dynamic range of the ISENSE signal in normal operation is 195 mV (335 mV for the CS5126), any voltage exceeding this threshold on the ISENSE pin is considered a fault and the PWM cycle is terminated. The 2nd ICOMP compares the ISENSE signal with a 275 mV (525 mV for the CS5126) threshold. If the ISENSE voltage exceeds the second threshold, F2 is set, the driver turns off, and the Soft Start capacitor discharges. After the Soft Start capacitor has discharged to less than 0.275 V Soft Start will begin. If the fault condition has been removed the supply will operate normally. If the fault remains the supply will operate in hiccup mode until the fault condition is removed. Fault Conditions The CS5124/6 recognizes the following faults: UVLO off, Thermal Shutdown, VREF(OK), and Second Current Threshold. Once a fault is recognized, fault latch F2 is set and the IC immediately shuts down the output driver and discharges the Soft Start capacitor. Soft Start will begin only after all faults have been removed and the Soft Start capacitor has been discharged to less than 0.275 V. Each fault will be explained in the following sections. VFB Comparator The VFB comparator detects when the output voltage is too high. When the regulated output voltage is too high, the feedback loop will drive VFB low. If VFB is less than 0.49 V the output of the VFB comparator will go high and shut the output driver off. Under Voltage Lockout (UVLO) The UVLO pin is tied to typically the midpoint of a resistive divider between VIN and GROUND. During a start up sequence, this pin must be above 2.6 V in order for the IC to begin normal operation. If the IC is running and this pin is pulled below 1.8 V, F2 shuts down the output driver and discharges the Soft Start capacitor in order to insure proper start–up. If the UVLO pin is pulled high again before the Soft Start capacitor discharges, the IC will complete the Soft Start discharge and, if no other faults are present, will immediately restart the power supply. If the UVLO pin stays low, then it will enter either the low current sleep mode or the UVLO state depending on the level of the UVLO pin. Oscillator The internally trimmed, 400 kHz (CS5124) or 200 kHz (CS5126) provides the slope compensation ramp as well as the pulse for enabling the output driver. PWM Comparator and Slope Compensation The CS5124/6 provides a fixed internal slope compensation ramp that is subtracted from the feedback signal. The PWM comparator compares peak primary current to a portion of the difference of the feedback voltage and slope compensation ramp. The 170 mV/µs (85 mV/µs for the CS5126) slope compensation ramp is subtracted from the voltage feedback signal internally. The difference signal is then divided by ten (five for the CS5126) before the PWM comparator to provide high noise rejection with a low voltage across the current sense network. (The effective ramp is 21 mV/µs for the CS5124, and 18 mV/µs for the CS5126). A 60 mV (125 mV for the CS5126) nominal offset on the positive input to the PWM comparator allows for operation with the ISENSE pin at, or even slightly below GND. A 4.3 kΩ pull–up resistor internally connected to a 5.0 V nominal reference provides the bias current to for an optocoupler connection to the VFB pin. Thermal Shutdown If the IC junction temperature exceeds approximately 150°C the thermal shutdown circuit sets F2, which shuts down the output driver and discharges the Soft Start capacitor. If no other faults are present the IC will initiate Soft Start when the IC junction temperature has been reduced by 25°C. VREF(OK) VREF(OK) is an internal monitor that insures the internal regulator is running before any switching occurs. This function does not trip the fault comparator like the other fault functions. To insure that Soft Start will occur at low line conditions the UVLO divider should be set up so that the VCC UVLO comparator turns on before the LINE UVLO comparator. http://onsemi.com 7 CS5124, CS5126 APPLICATION INFORMATION 0.82 UVLO and Thermal Shutdown Interaction Maximum Duty Cycle The UVLO pin and thermal shutdown circuit share the same internal comparator. During high temperature operation (TJ > 100°C) the UVLO pin will interact with the thermal shutdown circuit. This interaction increases the turn–on threshold (and hysteresis) of the UVLO circuit. If the UVLO pin shuts down the IC during high temperature operation, higher hysteresis (see hysteresis specification) might be required to enable the IC. 125°C 25°C 0.77 –40°C BIAS Pin (CS5124 Only) The bias pin can be used to control VCC as shown in the main application diagram in Figure 1. In order to provide adequate phase margin for the bias control loop, the pole created by the series pass transistor and the VCC bypass capacitor should be kept above 10 kHz. The frequency of this pole can be calculated by Formula (1). Pole Frequency Transconductance of pass Transistor 2 CV(CC) 0.72 200 kHz 300 kHz 400 kHz Frequency 500 kHz 600 kHz Figure 4. CS5126 Maximum Duty Cycle vs. Frequency (Synchronized Operation) If the converter is initially free running and a sync signal is applied, the current oscillator cycle will terminate and the oscillator will lock on to the sync signal. The SYNC pin works with a positive edge triggered signal. When the sync signal transitions high the current PWM cycle terminates and a new cycle begins as shown in Figure 5. The typical phase lag between the rising edge of the SYNC signal and the rising edge of the Gate is shown in Figure 6. When this pin is held high or low the internal clock determines the oscillator frequency. (1) The Line BIAS pin shows a significant change in the regulated VCC voltage when sinking large currents. This will show up as poor line regulation with a low value pull–up resistor. Typical regulated VCC vs BIAS pin sink current is shown in Figure 3. 8.3 SYNC 8.2 VCC OSC GATE 8.1 Figure 5. Synchronized Operation 8.0 140 130 10 µΑ 20 µΑ 50 µΑ 100 µΑ 200 µΑ Phase Lag° 7.9 5.0 µΑ Bias Current (IBIAS) Figure 3. Regulated VCC vs. BIAS Sink Current The BIAS pin and associated components form a high impedance node. Care should be taken during PCB layout to avoid connections that could couple noise into this node. 120 110 100 90 80 Clock Synchronization Pin (CS5126 Only) The CS5126 can be synchronized to signals ranging from 30% slower to several times faster than the internal oscillator frequency. If the part is synchronized to a fast signal, maximum duty cycle will be reduced as the frequency increases as shown in Figure 4. 70 200 kHZ 300 kHZ 400 kHZ 500 kHZ 600 kHZ Figure 6. Typical Phase Lag between SYNC and GATE on http://onsemi.com 8 CS5124, CS5126 Gate Drive When the output current is high enough for the ISENSE pin to exceed the first threshold, the PWM cycle terminates early and the converter begins to function more like a current source. The current sense network must be chosen so that the peak current during normal operation does not exceed the first current sense threshold. Rail to rail gate driver operation can be obtained (up to 13.5 V) over a range of MOSFET input capacitance if the gate resistor value is kept low. Figure 5 shows the high gate drive level vs. the series gate resistance with VCC = 8.0 V driving an IRF220. Second Current Sense Threshold 8.5 The second threshold is intended to protect the converter from over–heating by switching to a low duty cycle mode when there are abnormally high fast rise currents in the converter. If the second current sense threshold is tripped, the converter will shut off and restart in Soft Start mode until the high current condition is removed. The dead time after a second threshold over–current condition will primarily be determined by the time required to charge the Soft Start cap from 0.275 V nominal to 1.32 V. The second threshold will only be reached when a high dv/dt is present at the current sense pin. The signal must be fast enough to reach the second threshold before the first threshold turns off the driver. This will normally happen if the forward inductor saturates or when there is a shorted load. Excessive filtering of the current sense signal, a low value current sense resistor, or even an inductor that does not saturate during heavy output currents can prevent the second threshold from being reached. In this case the first current sense threshold will trip during each cycle of high output current conditions. The first threshold will limit output current but some components, especially the output rectifier, can overheat due to higher than normal average output current. Peak Voltage 8.0 7.5 7.0 6.5 6.0 0 0.3 0.5 2.5 Gate Resistor Value 5.0 11 Figure 7. Gate Drive vs. Gate Resistor Driving an IRF220 (VCC = 8.0 V) A large negative dv/dt on the power MOSFET drain will couple current into the gate driver through the gate to drain capacitance. If this current is kept within absolute maximum ratings for the GATE pin it will not damage the IC. However if a high negative dv/dt coincides with the start of a PWM duty cycle, there will be small variations in oscillator frequency due to current in the controller substrate. If required, this can be avoided by choosing the transformer ratio and reset circuit so that a high dv/dt does not coincide with the start of a PWM cycle, or by clamping the negative voltage on the GATE pin with a schottky diode Slope Compensation Current mode converters operating at duty cycles in excess of 50% require an artificial ramp to be added to the current waveform or subtracted from the feedback waveform. For the current loop to be stable the artificial ramp must be equivalent to at least 50% of the inductor current down slope and is typically chosen between 75% to 100% of the inductor down current down slope. To choose an inductor value such that the internal slope compensation ramp will be equal to a certain fraction of the inductor down current slope use the Formula (4). First Current Sense Threshold During normal operation the peak primary current is controlled by the level of the VFB pin (as determined by the control loop) and the current sense network. Once the signal on the ISENSE pin exceeds the level determined by VFB pin the PWM cycle terminates. During high output currents the VFB pin will rise until it reaches the VFB clamp. The first current sense threshold determines the maximum signal allowed on the ISENSE pin before the PWM cycle is terminated. Under this condition the maximum peak current is determined by the VFB Clamp, the slope compensation ramp, the PWM comparator offset voltage and the PWM on time. The nominal first current threshold varies with on time and can be calculated from Formulas (2) & (3) below. N 1 (VOUT VRECTIFIER) SECONDARY Internal Ramp NPRIMARY RSENSE Slope Value Factor Inductor Value(H) Calculating the nominal inductor value for an artificial ramp equivalent to 100% of the current inductor down slope at CS5126 nominal conditions, a 5.0 V output, a 200 mΩ current sense resistor and a 4:1 transformer ratio yields CS5124 1st Threshold CS5126 1st Threshold 2.9 V 170 mVs TON 60 mV 10 (2) 2.65 V 85 mVs TON 125 mV 5.0 (3) (4) 1 (5.0 V 0.3 V) 1 0.2 1.0 13.2 H 4 20 mVs (5) To check that the slope compensation ramp will be greater than 50% of the inductor down under all conditions, http://onsemi.com 9 CS5124, CS5126 winding is phased to conduct during the off time of the forward converter and performs the same function as the flyback winding above. A flyback winding from a forward transformer can also be used to power VCC. Ideally the transformer volt–second product of a forward converter would be constant over the range of line voltages and load currents; and the transformer inductance could be chosen to store the required level of energy during each cycle to power VCC. Even though the flyback energy is not directly regulated it would remain constant. Unfortunately in a real converter there are many non–ideal effects that degrade regulation. Transformer inductance varies, converter frequency varies, energy stored in primary leakage inductance varies with output current, stray transformer capacitances and various parasitics all effect the level of energy available for VCC. If too little energy is provided to VCC, the bootstrapping circuit must provide power and efficiency will be reduced. If too much energy is provided VCC rises and may damage the controller. If this approach is taken the circuit must be carefully designed and component values must be controlled for good regulation. substitute the minimum internal slope compensation value and use 0.5 for the slope compensation value. Then check that the actual inductor value will always be greater than the inductor value calculated. During synchronized operation of the CS5126 the slope compensation ramp is reduced by 33%. If the CS5126 will be used in synchronized operation, the inductor value should be recalculated to work with the slope compensation ramp reduced to 67% of the normal value. Powering the CS5124/6 from a Transformer Winding There are numerous ways to power the CS5124/6 from a transformer winding to enable the converter to be operated at high efficiency over a wide input range. Two ways are shown in the application circuits. The CS5124 application circuit in Figure 1 is a flyback converter that uses a second flyback winding to power VCC. R4 improves VCC regulation with load changes by snubbing the turn off spike. Once the turn off spike has subsided the voltage of this winding is voltage proportional to the voltage on the main flyback winding. This voltage is regulated because the main winding is clamped by the regulated output voltage. In the CS5126 application circuit in Figure 8 an extra winding is added to the forward inductor to power VCC. This 36–75VIN CTX15–14526 L1 10 µH C3 0.2 µF 100 V C1 1.5 µF 100 V R2 200 k R6 17.4 k D3 11 V C5 1.0 µF 25 V Q1 F2T493 T2 R9 10 k C4 1000 pF R4 0.2 Ω 1/4W C6 390 pF MMBD6100L MBRB2060CT Q2 IRF634 VCC GND UVLO GATE IS SYNC SS VFB ENABLE SYNC 5VOUT R1 39 k D2 C2 1.5 µF 100 V R10 10 k C11 0.1 µF T1 CTX15–14527 CS5126 C12 0.01 µF R7 2.0 k R3 30.1 k C7 47 µF C9 C8 47 µF U2 0.01 µF C10 1000 pF TPS5908 R8 10 k ISOLATED RTN 48VRTN Figure 8. Additional Application Diagram, 48 V to 5.0 V, 5.0 A Forward Converter using the CS5126 http://onsemi.com 10 CS5124, CS5126 PACKAGE DIMENSIONS SO–8 D SUFFIX CASE 751–07 ISSUE V –X– A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 5 0.25 (0.010) S B 1 M Y M 4 K –Y– G C N X 45 SEATING PLANE –Z– 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S PACKAGE THERMAL DATA Parameter SO–8 Unit RΘJC Typical 45 °C/W RΘJA Typical 165 °C/W http://onsemi.com 11 CS5124, CS5126 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. American Technical Support: 800–282–9855 Toll Free USA/Canada CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–[email protected] ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit–[email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2745 Email: [email protected] EUROPE: LDC for ON Semiconductor – European Support German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET) Email: ONlit–[email protected] French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET) Email: ONlit–[email protected] English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT) Email: [email protected] ON Semiconductor Website: http://onsemi.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, UK, Ireland For additional information, please contact your local Sales Representative. http://onsemi.com 12 CS5124/D